locore.h revision 1.78.36.1.2.35
1 /* locore.h,v 1.78.36.1.2.29 2011/04/29 08:26:21 matt Exp */ 2 3 /* 4 * This file should not be included by MI code!!! 5 */ 6 7 /* 8 * Copyright 1996 The Board of Trustees of The Leland Stanford 9 * Junior University. All Rights Reserved. 10 * 11 * Permission to use, copy, modify, and distribute this 12 * software and its documentation for any purpose and without 13 * fee is hereby granted, provided that the above copyright 14 * notice appear in all copies. Stanford University 15 * makes no representations about the suitability of this 16 * software for any purpose. It is provided "as is" without 17 * express or implied warranty. 18 */ 19 20 /* 21 * Jump table for MIPS CPU locore functions that are implemented 22 * differently on different generations, or instruction-level 23 * architecture (ISA) level, the Mips family. 24 * 25 * We currently provide support for MIPS I and MIPS III. 26 */ 27 28 #ifndef _MIPS_LOCORE_H 29 #define _MIPS_LOCORE_H 30 31 #ifndef _LKM 32 #include "opt_cputype.h" 33 #endif 34 35 #include <sys/kcore.h> 36 37 #include <mips/mutex.h> 38 #include <mips/cpuregs.h> 39 #include <mips/reg.h> 40 41 struct tlbmask; 42 struct trapframe; 43 44 void trap(uint32_t, uint32_t, vaddr_t, vaddr_t, struct trapframe *); 45 void ast(void); 46 47 /* 48 * Perform a trapsignal, and if cpu_printfataltraps is true, print the trap info 49 * to the console. 50 */ 51 extern bool cpu_printfataltraps; 52 void cpu_trapsignal(struct lwp *, ksiginfo_t *, struct trapframe *); 53 54 void mips_fpu_trap(vaddr_t, struct trapframe *); 55 void mips_fpu_intr(vaddr_t, struct trapframe *); 56 57 vaddr_t mips_emul_branch(struct trapframe *, vaddr_t, uint32_t, bool); 58 void mips_emul_inst(uint32_t, uint32_t, vaddr_t, struct trapframe *); 59 60 void mips_emul_fp(uint32_t, struct trapframe *, uint32_t); 61 void mips_emul_branchdelayslot(uint32_t, struct trapframe *, uint32_t); 62 63 void mips_emul_lwc0(uint32_t, struct trapframe *, uint32_t); 64 void mips_emul_swc0(uint32_t, struct trapframe *, uint32_t); 65 void mips_emul_special(uint32_t, struct trapframe *, uint32_t); 66 void mips_emul_special3(uint32_t, struct trapframe *, uint32_t); 67 68 void mips_emul_lwc1(uint32_t, struct trapframe *, uint32_t); 69 void mips_emul_swc1(uint32_t, struct trapframe *, uint32_t); 70 void mips_emul_ldc1(uint32_t, struct trapframe *, uint32_t); 71 void mips_emul_sdc1(uint32_t, struct trapframe *, uint32_t); 72 73 void mips_emul_lb(uint32_t, struct trapframe *, uint32_t); 74 void mips_emul_lbu(uint32_t, struct trapframe *, uint32_t); 75 void mips_emul_lh(uint32_t, struct trapframe *, uint32_t); 76 void mips_emul_lhu(uint32_t, struct trapframe *, uint32_t); 77 void mips_emul_lw(uint32_t, struct trapframe *, uint32_t); 78 void mips_emul_lwl(uint32_t, struct trapframe *, uint32_t); 79 void mips_emul_lwr(uint32_t, struct trapframe *, uint32_t); 80 #if defined(__mips_n32) || defined(__mips_n64) || defined(__mips_o64) 81 void mips_emul_lwu(uint32_t, struct trapframe *, uint32_t); 82 void mips_emul_ld(uint32_t, struct trapframe *, uint32_t); 83 void mips_emul_ldl(uint32_t, struct trapframe *, uint32_t); 84 void mips_emul_ldr(uint32_t, struct trapframe *, uint32_t); 85 #endif 86 void mips_emul_sb(uint32_t, struct trapframe *, uint32_t); 87 void mips_emul_sh(uint32_t, struct trapframe *, uint32_t); 88 void mips_emul_sw(uint32_t, struct trapframe *, uint32_t); 89 void mips_emul_swl(uint32_t, struct trapframe *, uint32_t); 90 void mips_emul_swr(uint32_t, struct trapframe *, uint32_t); 91 #if defined(__mips_n32) || defined(__mips_n64) || defined(__mips_o64) 92 void mips_emul_sd(uint32_t, struct trapframe *, uint32_t); 93 void mips_emul_sdl(uint32_t, struct trapframe *, uint32_t); 94 void mips_emul_sdr(uint32_t, struct trapframe *, uint32_t); 95 #endif 96 97 uint32_t mips_cp0_cause_read(void); 98 void mips_cp0_cause_write(uint32_t); 99 uint32_t mips_cp0_status_read(void); 100 void mips_cp0_status_write(uint32_t); 101 102 void softint_process(uint32_t); 103 void softint_fast_dispatch(struct lwp *, int); 104 105 /* 106 * Convert an address to an offset used in a MIPS jump instruction. The offset 107 * contains the low 28 bits (allowing a jump to anywhere within the same 256MB 108 * segment of address space) of the address but since mips instructions are 109 * always on a 4 byte boundary the low 2 bits are always zero so the 28 bits 110 * get shifted right by 2 bits leaving us with a 26 bit result. To make the 111 * offset, we shift left to clear the upper four bits and then right by 6. 112 */ 113 #define fixup_addr2offset(x) ((((uint32_t)(uintptr_t)(x)) << 4) >> 6) 114 typedef bool (*mips_fixup_callback_t)(int32_t, uint32_t [2]); 115 struct mips_jump_fixup_info { 116 uint32_t jfi_stub; 117 uint32_t jfi_real; 118 }; 119 120 void fixup_splcalls(void); /* splstubs.c */ 121 bool mips_fixup_exceptions(mips_fixup_callback_t); 122 bool mips_fixup_zero_relative(int32_t, uint32_t [2]); 123 intptr_t 124 mips_fixup_addr(const uint32_t *); 125 void mips_fixup_stubs(uint32_t *, uint32_t *); 126 127 /* 128 * Define these stubs... 129 */ 130 void mips_cpu_switch_resume(struct lwp *); 131 void tlb_set_asid(uint32_t); 132 void tlb_invalidate_all(void); 133 void tlb_invalidate_globals(void); 134 void tlb_invalidate_asids(uint32_t, uint32_t); 135 void tlb_invalidate_addr(vaddr_t); 136 u_int tlb_record_asids(u_long *, uint32_t); 137 int tlb_update(vaddr_t, uint32_t); 138 void tlb_enter(size_t, vaddr_t, uint32_t); 139 void tlb_read_indexed(size_t, struct tlbmask *); 140 void tlb_write_indexed(size_t, const struct tlbmask *); 141 void wbflush(void); 142 143 #ifdef MIPS1 144 void mips1_tlb_invalidate_all(void); 145 146 uint32_t tx3900_cp0_config_read(void); 147 #endif 148 149 #if (MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2 + MIPS64_RMIXL + MIPS64R2_RMIXL) > 0 150 uint32_t mips3_cp0_compare_read(void); 151 void mips3_cp0_compare_write(uint32_t); 152 153 uint32_t mips3_cp0_config_read(void); 154 void mips3_cp0_config_write(uint32_t); 155 156 #if (MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2 + MIPS64_RMIXL + MIPS64R2_RMIXL) > 0 157 uint32_t mipsNN_cp0_config1_read(void); 158 void mipsNN_cp0_config1_write(uint32_t); 159 uint32_t mipsNN_cp0_config2_read(void); 160 void mipsNN_cp0_config2_write(uint32_t); 161 uint32_t mipsNN_cp0_config3_read(void); 162 void mipsNN_cp0_config3_write(uint32_t); 163 uint32_t mipsNN_cp0_config4_read(void); 164 void mipsNN_cp0_config4_write(uint32_t); 165 uint32_t mipsNN_cp0_config5_read(void); 166 void mipsNN_cp0_config5_write(uint32_t); 167 uint32_t mipsNN_cp0_config6_read(void); 168 void mipsNN_cp0_config6_write(uint32_t); 169 uint32_t mipsNN_cp0_config7_read(void); 170 void mipsNN_cp0_config7_write(uint32_t); 171 uint64_t mips64_cp0_config7_read(void); 172 void mips64_cp0_config7_write(uint32_t); 173 174 uintptr_t mipsNN_cp0_watchlo_read(u_int); 175 void mipsNN_cp0_watchlo_write(u_int, uintptr_t); 176 uint32_t mipsNN_cp0_watchhi_read(u_int); 177 void mipsNN_cp0_watchhi_write(u_int, uint32_t); 178 179 #if (MIPS32R2 + MIPS64R2 + MIPS64R2_RMIXL) > 0 180 void mipsNN_cp0_hwrena_write(uint32_t); 181 void mipsNN_cp0_userlocal_write(void *); 182 #endif 183 #endif 184 185 uint32_t mips3_cp0_count_read(void); 186 void mips3_cp0_count_write(uint32_t); 187 188 uint32_t mips3_cp0_random_read(void); 189 190 uint32_t mips3_cp0_wired_read(void); 191 void mips3_cp0_wired_write(uint32_t); 192 void mips3_cp0_pg_mask_write(uint32_t); 193 194 #if defined(__GNUC__) && !defined(__mips_o32) 195 static inline uint64_t 196 mips3_ld(const volatile uint64_t *va) 197 { 198 uint64_t rv; 199 #if defined(__mips_o32) 200 uint32_t sr; 201 202 sr = mips_cp0_status_read(); 203 mips_cp0_status_write(sr & ~MIPS_SR_INT_IE); 204 205 __asm volatile( 206 ".set push \n\t" 207 ".set mips3 \n\t" 208 ".set noreorder \n\t" 209 ".set noat \n\t" 210 "ld %M0,0(%1) \n\t" 211 "dsll32 %L0,%M0,0 \n\t" 212 "dsra32 %M0,%M0,0 \n\t" /* high word */ 213 "dsra32 %L0,%L0,0 \n\t" /* low word */ 214 "ld %0,0(%1) \n\t" 215 ".set pop" 216 : "=d"(rv) 217 : "r"(va)); 218 219 mips_cp0_status_write(sr); 220 #elif defined(_LP64) 221 rv = *va; 222 #else 223 __asm volatile("ld %0,0(%1)" : "=d"(rv) : "r"(va)); 224 #endif 225 226 return rv; 227 } 228 static inline void 229 mips3_sd(volatile uint64_t *va, uint64_t v) 230 { 231 #if defined(__mips_o32) 232 uint32_t sr; 233 234 sr = mips_cp0_status_read(); 235 mips_cp0_status_write(sr & ~MIPS_SR_INT_IE); 236 237 __asm volatile( 238 ".set push \n\t" 239 ".set mips3 \n\t" 240 ".set noreorder \n\t" 241 ".set noat \n\t" 242 "dsll32 %M0,%M0,0 \n\t" 243 "dsll32 %L0,%L0,0 \n\t" 244 "dsrl32 %L0,%L0,0 \n\t" 245 "or %0,%L0,%M0 \n\t" 246 "sd %0,0(%1) \n\t" 247 ".set pop" 248 : "=d"(v) : "0"(v), "r"(va)); 249 250 mips_cp0_status_write(sr); 251 #elif defined(_LP64) 252 *va = v; 253 #else 254 __asm volatile("sd %0,0(%1)" :: "r"(v), "r"(va)); 255 #endif 256 } 257 #else 258 uint64_t mips3_ld(volatile uint64_t *va); 259 void mips3_sd(volatile uint64_t *, uint64_t); 260 #endif /* __GNUC__ */ 261 #endif /* (MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2 + MIPS64_RMIXL + MIPS64R2_RMIXL) > 0 */ 262 263 #if (MIPS3 + MIPS4 + MIPS64 + MIPS64R2 + MIPS64_RMIXL + MIPS64R2_RMIXL) > 0 264 static __inline uint32_t mips3_lw_a64(uint64_t addr) __unused; 265 static __inline void mips3_sw_a64(uint64_t addr, uint32_t val) __unused; 266 267 static __inline uint32_t 268 mips3_lw_a64(uint64_t addr) 269 { 270 uint32_t rv; 271 #if defined(__mips_o32) 272 uint32_t sr; 273 274 sr = mips_cp0_status_read(); 275 mips_cp0_status_write((sr & ~MIPS_SR_INT_IE) | MIPS3_SR_KX); 276 277 __asm volatile ( 278 ".set push \n\t" 279 ".set mips3 \n\t" 280 ".set noreorder \n\t" 281 ".set noat \n\t" 282 "dsll32 %M1,%M1,0 \n\t" 283 "dsll32 %L1,%L1,0 \n\t" 284 "dsrl32 %L1,%L1,0 \n\t" 285 "or %1,%M1,%L1 \n\t" 286 "lw %0, 0(%1) \n\t" 287 ".set pop" 288 : "=r"(rv), "=d"(addr) 289 : "1"(addr) 290 ); 291 292 mips_cp0_status_write(sr); 293 #elif defined(__mips_n32) 294 uint32_t sr = mips_cp0_status_read(); 295 mips_cp0_status_write((sr & ~MIPS_SR_INT_IE) | MIPS3_SR_KX); 296 __asm volatile("lw %0, 0(%1)" : "=r"(rv) : "d"(addr)); 297 mips_cp0_status_write(sr); 298 #elif defined(_LP64) 299 rv = *(const uint32_t *)addr; 300 #else 301 #error unknown ABI 302 #endif 303 return (rv); 304 } 305 306 static __inline void 307 mips3_sw_a64(uint64_t addr, uint32_t val) 308 { 309 #if defined(__mips_o32) 310 uint32_t sr; 311 312 sr = mips_cp0_status_read(); 313 mips_cp0_status_write((sr & ~MIPS_SR_INT_IE) | MIPS3_SR_KX); 314 315 __asm volatile ( 316 ".set push \n\t" 317 ".set mips3 \n\t" 318 ".set noreorder \n\t" 319 ".set noat \n\t" 320 "dsll32 %M0,%M0,0 \n\t" 321 "dsll32 %L0,%L0,0 \n\t" 322 "dsrl32 %L0,%L0,0 \n\t" 323 "or %0,%M0,%L0 \n\t" 324 "sw %1, 0(%0) \n\t" 325 ".set pop" 326 : "=d"(addr): "r"(val), "0"(addr) 327 ); 328 329 mips_cp0_status_write(sr); 330 #elif defined(__mips_n32) 331 uint32_t sr = mips_cp0_status_read(); 332 mips_cp0_status_write((sr & ~MIPS_SR_INT_IE) | MIPS3_SR_KX); 333 __asm volatile("sw %1, 0(%0)" :: "d"(addr), "r"(val)); 334 mips_cp0_status_write(sr); 335 #elif defined(_LP64) 336 *(uint32_t *)addr = val; 337 #else 338 #error unknown ABI 339 #endif 340 } 341 #endif /* (MIPS3 + MIPS4 + MIPS64 + MIPS64R2 + MIPS64_RMIXL + MIPS64R2_RMIXL) > 0 */ 342 343 /* 344 * A vector with an entry for each mips-ISA-level dependent 345 * locore function, and macros which jump through it. 346 */ 347 typedef struct { 348 void (*ljv_cpu_switch_resume)(struct lwp *); 349 intptr_t ljv_lwp_trampoline; 350 intptr_t ljv_setfunc_trampoline; 351 void (*ljv_wbflush)(void); 352 void (*ljv_tlb_set_asid)(uint32_t pid); 353 void (*ljv_tlb_invalidate_asids)(uint32_t, uint32_t); 354 void (*ljv_tlb_invalidate_addr)(vaddr_t); 355 void (*ljv_tlb_invalidate_globals)(void); 356 void (*ljv_tlb_invalidate_all)(void); 357 u_int (*ljv_tlb_record_asids)(u_long *, uint32_t); 358 int (*ljv_tlb_update)(vaddr_t, uint32_t); 359 void (*ljv_tlb_enter)(size_t, vaddr_t, uint32_t); 360 void (*ljv_tlb_read_indexed)(size_t, struct tlbmask *); 361 void (*ljv_tlb_write_indexed)(size_t, const struct tlbmask *); 362 lwp_t * (*ljv_cpu_switchto)(lwp_t *, lwp_t *, bool); 363 } mips_locore_jumpvec_t; 364 365 typedef struct { 366 u_int (*lav_atomic_cas_uint)(volatile u_int *, u_int, u_int); 367 u_long (*lav_atomic_cas_ulong)(volatile u_long *, u_long, u_long); 368 int (*lav_ucas_uint)(volatile u_int *, u_int, u_int, u_int *); 369 int (*lav_ucas_ulong)(volatile u_long *, u_long, u_long, u_long *); 370 void (*lav_mutex_enter)(kmutex_t *); 371 void (*lav_mutex_exit)(kmutex_t *); 372 void (*lav_mutex_spin_enter)(kmutex_t *); 373 void (*lav_mutex_spin_exit)(kmutex_t *); 374 } mips_locore_atomicvec_t; 375 376 void mips_set_wbflush(void (*)(void)); 377 void mips_wait_idle(void); 378 379 void stacktrace(void); 380 void logstacktrace(void); 381 382 struct cpu_info; 383 struct splsw; 384 385 struct locoresw { 386 void (*lsw_wbflush)(void); 387 void (*lsw_cpu_idle)(void); 388 int (*lsw_send_ipi)(struct cpu_info *, int); 389 void (*lsw_cpu_offline_md)(void); 390 void (*lsw_cpu_init)(struct cpu_info *); 391 void (*lsw_cpu_run)(struct cpu_info *); 392 int (*lsw_bus_error)(unsigned int); 393 }; 394 395 struct mips_vmfreelist { 396 paddr_t fl_start; 397 paddr_t fl_end; 398 int fl_freelist; 399 }; 400 401 /* 402 * The "active" locore-function vector, and 403 */ 404 extern const mips_locore_atomicvec_t mips_llsc_locore_atomicvec; 405 extern const mips_locore_atomicvec_t mips_ras_locore_atomicvec; 406 407 extern mips_locore_atomicvec_t mips_locore_atomicvec; 408 extern mips_locore_jumpvec_t mips_locore_jumpvec; 409 extern struct locoresw mips_locoresw; 410 411 struct splsw; 412 struct mips_vmfreelist; 413 struct phys_ram_seg; 414 415 void mips_vector_init(const struct splsw *, bool); 416 void mips_init_msgbuf(void); 417 void mips_init_lwp0_uarea(void); 418 void mips_page_physload(vaddr_t, vaddr_t, 419 const struct phys_ram_seg *, size_t, 420 const struct mips_vmfreelist *, size_t); 421 422 paddr_t kvtophys(vaddr_t); 423 424 extern struct phys_ram_seg mem_clusters[]; 425 extern u_int mem_cluster_cnt; 426 427 /* 428 * Helper routines for kernel coredumps. 429 */ 430 vaddr_t mips_kcore_window_map(paddr_t, vsize_t *); 431 #ifndef _LP64 432 bool mips_kcore_window_vtophys(vaddr_t, paddr_t *); 433 #endif 434 435 436 /* 437 * CPU identification, from PRID register. 438 */ 439 #define MIPS_PRID_REV(x) (((x) >> 0) & 0x00ff) 440 #define MIPS_PRID_IMPL(x) (((x) >> 8) & 0x00ff) 441 442 /* pre-MIPS32/64 */ 443 #define MIPS_PRID_RSVD(x) (((x) >> 16) & 0xffff) 444 #define MIPS_PRID_REV_MIN(x) ((MIPS_PRID_REV(x) >> 0) & 0x0f) 445 #define MIPS_PRID_REV_MAJ(x) ((MIPS_PRID_REV(x) >> 4) & 0x0f) 446 447 /* MIPS32/64 */ 448 #define MIPS_PRID_CID(x) (((x) >> 16) & 0x00ff) /* Company ID */ 449 #define MIPS_PRID_CID_PREHISTORIC 0x00 /* Not MIPS32/64 */ 450 #define MIPS_PRID_CID_MTI 0x01 /* MIPS Technologies, Inc. */ 451 #define MIPS_PRID_CID_BROADCOM 0x02 /* Broadcom */ 452 #define MIPS_PRID_CID_ALCHEMY 0x03 /* Alchemy Semiconductor */ 453 #define MIPS_PRID_CID_SIBYTE 0x04 /* SiByte */ 454 #define MIPS_PRID_CID_SANDCRAFT 0x05 /* SandCraft */ 455 #define MIPS_PRID_CID_PHILIPS 0x06 /* Philips */ 456 #define MIPS_PRID_CID_TOSHIBA 0x07 /* Toshiba */ 457 #define MIPS_PRID_CID_LSI 0x08 /* LSI */ 458 /* 0x09 unannounced */ 459 /* 0x0a unannounced */ 460 #define MIPS_PRID_CID_LEXRA 0x0b /* Lexra */ 461 #define MIPS_PRID_CID_RMI 0x0c /* RMI / NetLogic */ 462 #define MIPS_PRID_COPTS(x) (((x) >> 24) & 0x00ff) /* Company Options */ 463 464 #ifdef _KERNEL 465 /* 466 * Global variables used to communicate CPU type, and parameters 467 * such as cache size, from locore to higher-level code (e.g., pmap). 468 */ 469 void mips_pagecopy(void *dst, void *src); 470 void mips_pagezero(void *dst); 471 472 #ifdef __HAVE_MIPS_MACHDEP_CACHE_CONFIG 473 void mips_machdep_cache_config(void); 474 #endif 475 476 /* 477 * trapframe argument passed to trap() 478 */ 479 480 #if 0 481 #define TF_AST 0 /* really zero */ 482 #define TF_V0 _R_V0 483 #define TF_V1 _R_V1 484 #define TF_A0 _R_A0 485 #define TF_A1 _R_A1 486 #define TF_A2 _R_A2 487 #define TF_A3 _R_A3 488 #define TF_T0 _R_T0 489 #define TF_T1 _R_T1 490 #define TF_T2 _R_T2 491 #define TF_T3 _R_T3 492 493 #if defined(__mips_n32) || defined(__mips_n64) 494 #define TF_A4 _R_A4 495 #define TF_A5 _R_A5 496 #define TF_A6 _R_A6 497 #define TF_A7 _R_A7 498 #else 499 #define TF_T4 _R_T4 500 #define TF_T5 _R_T5 501 #define TF_T6 _R_T6 502 #define TF_T7 _R_T7 503 #endif /* __mips_n32 || __mips_n64 */ 504 505 #define TF_TA0 _R_TA0 506 #define TF_TA1 _R_TA1 507 #define TF_TA2 _R_TA2 508 #define TF_TA3 _R_TA3 509 510 #define TF_T8 _R_T8 511 #define TF_T9 _R_T9 512 513 #define TF_RA _R_RA 514 #define TF_SR _R_SR 515 #define TF_MULLO _R_MULLO 516 #define TF_MULHI _R_MULLO 517 #define TF_EPC _R_PC /* may be changed by trap() call */ 518 519 #define TF_NREGS (sizeof(struct reg) / sizeof(mips_reg_t)) 520 #endif 521 522 struct trapframe { 523 struct reg tf_registers; 524 #define tf_regs tf_registers.r_regs 525 uint32_t tf_ppl; /* previous priority level */ 526 mips_reg_t tf_pad; /* for 8 byte aligned */ 527 }; 528 529 CTASSERT(sizeof(struct trapframe) % (4*sizeof(mips_reg_t)) == 0); 530 531 /* 532 * Stack frame for kernel traps. four args passed in registers. 533 * A trapframe is pointed to by the 5th arg, and a dummy sixth argument 534 * is used to avoid alignment problems 535 */ 536 537 struct kernframe { 538 #if defined(__mips_o32) || defined(__mips_o64) 539 register_t cf_args[4 + 1]; 540 #if defined(__mips_o32) 541 register_t cf_pad; /* (for 8 byte alignment) */ 542 #endif 543 #endif 544 #if defined(__mips_n32) || defined(__mips_n64) 545 register_t cf_pad[2]; /* for 16 byte alignment */ 546 #endif 547 register_t cf_sp; 548 register_t cf_ra; 549 struct trapframe cf_frame; 550 }; 551 552 CTASSERT(sizeof(struct kernframe) % (2*sizeof(mips_reg_t)) == 0); 553 554 /* 555 * PRocessor IDentity TABle 556 */ 557 558 struct pridtab { 559 int cpu_cid; 560 int cpu_pid; 561 int cpu_rev; /* -1 == wildcard */ 562 int cpu_copts; /* -1 == wildcard */ 563 int cpu_isa; /* -1 == probed (mips32/mips64) */ 564 int cpu_ntlb; /* -1 == unknown, 0 == probed */ 565 int cpu_flags; 566 u_int cpu_cp0flags; /* presence of some cp0 regs */ 567 u_int cpu_cidflags; /* company-specific flags */ 568 const char *cpu_name; 569 }; 570 571 /* 572 * bitfield defines for cpu_cp0flags 573 */ 574 #define MIPS_CP0FL_USE __BIT(0) /* use these flags */ 575 #define MIPS_CP0FL_ECC __BIT(1) 576 #define MIPS_CP0FL_CACHE_ERR __BIT(2) 577 #define MIPS_CP0FL_EIRR __BIT(3) 578 #define MIPS_CP0FL_EIMR __BIT(4) 579 #define MIPS_CP0FL_EBASE __BIT(5) 580 #define MIPS_CP0FL_CONFIG __BIT(6) 581 #define MIPS_CP0FL_CONFIG1 __BIT(7) 582 #define MIPS_CP0FL_CONFIG2 __BIT(8) 583 #define MIPS_CP0FL_CONFIG3 __BIT(9) 584 #define MIPS_CP0FL_CONFIG4 __BIT(10) 585 #define MIPS_CP0FL_CONFIG5 __BIT(11) 586 #define MIPS_CP0FL_CONFIG6 __BIT(12) 587 #define MIPS_CP0FL_CONFIG7 __BIT(13) 588 #define MIPS_CP0FL_USERLOCAL __BIT(14) 589 #define MIPS_CP0FL_HWRENA __BIT(15) 590 591 /* 592 * cpu_cidflags defines, by company 593 */ 594 /* 595 * RMI company-specific cpu_cidflags 596 */ 597 #define MIPS_CIDFL_RMI_TYPE __BITS(2,0) 598 # define CIDFL_RMI_TYPE_XLR 0 599 # define CIDFL_RMI_TYPE_XLS 1 600 # define CIDFL_RMI_TYPE_XLP 2 601 #define MIPS_CIDFL_RMI_THREADS_MASK __BITS(6,3) 602 #define MIPS_CIDFL_RMI_CORES_MASK __BITS(10,7) 603 # define LOG2_1 0 604 # define LOG2_2 1 605 # define LOG2_4 2 606 # define LOG2_8 3 607 # define MIPS_CIDFL_RMI_CPUS(ncores, nthreads) \ 608 (__SHIFTIN(LOG2_ ## ncores, MIPS_CIDFL_RMI_CORES_MASK) \ 609 |__SHIFTIN(LOG2_ ## nthreads, MIPS_CIDFL_RMI_THREADS_MASK)) 610 # define MIPS_CIDFL_RMI_NTHREADS(cidfl) \ 611 (1 << __SHIFTOUT((cidfl), MIPS_CIDFL_RMI_THREADS_MASK)) 612 # define MIPS_CIDFL_RMI_NCORES(cidfl) \ 613 (1 << __SHIFTOUT((cidfl), MIPS_CIDFL_RMI_CORES_MASK)) 614 #define MIPS_CIDFL_RMI_L2SZ_MASK __BITS(14,11) 615 # define RMI_L2SZ_256KB 0 616 # define RMI_L2SZ_512KB 1 617 # define RMI_L2SZ_1MB 2 618 # define RMI_L2SZ_2MB 3 619 # define RMI_L2SZ_4MB 4 620 # define MIPS_CIDFL_RMI_L2(l2sz) \ 621 __SHIFTIN(RMI_L2SZ_ ## l2sz, MIPS_CIDFL_RMI_L2SZ_MASK) 622 # define MIPS_CIDFL_RMI_L2SZ(cidfl) \ 623 ((256*1024) << __SHIFTOUT((cidfl), MIPS_CIDFL_RMI_L2SZ_MASK)) 624 #define MIPS_CIDFL_RMI_L3SZ_MASK __BITS(18,15) 625 # define RMI_L3SZ_256KB 0 626 # define RMI_L3SZ_512KB 1 627 # define RMI_L3SZ_1MB 2 628 # define RMI_L3SZ_2MB 3 629 # define RMI_L3SZ_4MB 4 630 # define MIPS_CIDFL_RMI_L3(l3sz) \ 631 __SHIFTIN(RMI_L3SZ_ ## l3sz, MIPS_CIDFL_RMI_L3SZ_MASK) 632 # define MIPS_CIDFL_RMI_L3SZ(cidfl) \ 633 ((256*1024) << __SHIFTOUT((cidfl), MIPS_CIDFL_RMI_L3SZ_MASK)) 634 635 #endif /* _KERNEL */ 636 #endif /* _MIPS_LOCORE_H */ 637
Indexes created Mon Oct 20 10:10:01 GMT 2025