locore.h revision 1.78.36.1.2.9
1 /* $NetBSD: locore.h,v 1.78.36.1.2.9 2010/01/20 06:58:35 matt Exp $ */ 2 3 /* 4 * Copyright 1996 The Board of Trustees of The Leland Stanford 5 * Junior University. All Rights Reserved. 6 * 7 * Permission to use, copy, modify, and distribute this 8 * software and its documentation for any purpose and without 9 * fee is hereby granted, provided that the above copyright 10 * notice appear in all copies. Stanford University 11 * makes no representations about the suitability of this 12 * software for any purpose. It is provided "as is" without 13 * express or implied warranty. 14 */ 15 16 /* 17 * Jump table for MIPS CPU locore functions that are implemented 18 * differently on different generations, or instruction-level 19 * archtecture (ISA) level, the Mips family. 20 * 21 * We currently provide support for MIPS I and MIPS III. 22 */ 23 24 #ifndef _MIPS_LOCORE_H 25 #define _MIPS_LOCORE_H 26 27 #ifndef _LKM 28 #include "opt_cputype.h" 29 #endif 30 31 #include <mips/cpuregs.h> 32 33 struct tlbmask; 34 35 uint32_t mips_cp0_cause_read(void); 36 void mips_cp0_cause_write(uint32_t); 37 uint32_t mips_cp0_status_read(void); 38 void mips_cp0_status_write(uint32_t); 39 40 int _splraise(int); 41 int _spllower(int); 42 int _splset(int); 43 int _splget(void); 44 void _splnone(void); 45 void _setsoftintr(int); 46 void _clrsoftintr(int); 47 48 #ifdef MIPS1 49 void mips1_tlb_set_asid(uint32_t); 50 void mips1_tlb_invalidate_all(size_t); 51 void mips1_tlb_invalidate_asids(size_t, uint32_t, uint32_t); 52 void mips1_tlb_invalidate_addr(vaddr_t); 53 int mips1_tlb_update(vaddr_t, uint32_t); 54 void mips1_tlb_read_indexed(size_t, struct tlbmask *); 55 void mips1_wbflush(void); 56 void mips1_lwp_trampoline(void); 57 void mips1_setfunc_trampoline(void); 58 void mips1_cpu_switch_resume(void); 59 60 uint32_t tx3900_cp0_config_read(void); 61 #endif 62 63 #if defined(MIPS3) || defined(MIPS4) 64 void mips3_tlb_set_asid(uint32_t); 65 void mips3_tlb_invalidate_all(size_t); 66 void mips3_tlb_invalidate_asids(size_t, uint32_t, uint32_t); 67 void mips3_tlb_invalidate_addr(vaddr_t); 68 int mips3_tlb_update(vaddr_t, uint32_t); 69 void mips3_tlb_read_indexed(size_t, struct tlbmask *); 70 void mips3_tlb_write_indexed_VPS(size_t, struct tlbmask *); 71 void mips3_wbflush(void); 72 void mips3_lwp_trampoline(void); 73 void mips3_setfunc_trampoline(void); 74 void mips3_cpu_switch_resume(void); 75 void mips3_pagezero(void *dst); 76 77 #ifdef MIPS3_5900 78 void mips5900_tlb_set_asid(uint32_t); 79 void mips5900_tlb_invalidate_all(size_t); 80 void mips5900_tlb_invalidate_asids(size_t, uint32_t, uint32_t); 81 void mips5900_tlb_invalidate_addr(vaddr_t); 82 int mips5900_tlb_update(vaddr_t, uint32_t); 83 void mips5900_tlb_read_indexed(size_t, struct tlbmask *); 84 void mips5900_tlb_write_indexed_VPS(size_t, struct tlbmask *); 85 void mips5900_wbflush(void); 86 void mips5900_lwp_trampoline(void); 87 void mips5900_setfunc_trampoline(void); 88 void mips5900_cpu_switch_resume(void); 89 void mips5900_pagezero(void *dst); 90 #endif 91 #endif 92 93 #ifdef MIPS32 94 void mips32_tlb_set_asid(uint32_t); 95 void mips32_tlb_invalidate_all(size_t); 96 void mips32_tlb_invalidate_asids(size_t, uint32_t, uint32_t); 97 void mips32_tlb_invalidate_addr(vaddr_t); 98 int mips32_tlb_update(vaddr_t, uint32_t); 99 void mips32_tlb_read_indexed(size_t, struct tlbmask *); 100 void mips32_tlb_write_indexed_VPS(size_t, struct tlbmask *); 101 void mips32_wbflush(void); 102 void mips32_lwp_trampoline(void); 103 void mips32_setfunc_trampoline(void); 104 void mips32_cpu_switch_resume(void); 105 #endif 106 107 #ifdef MIPS64 108 void mips64_tlb_set_asid(uint32_t); 109 void mips64_tlb_invalidate_all(size_t); 110 void mips64_tlb_invalidate_asids(size_t, uint32_t, uint32_t); 111 void mips64_tlb_invalidate_addr(vaddr_t); 112 int mips64_tlb_update(vaddr_t, uint32_t); 113 void mips64_tlb_read_indexed(size_t, struct tlbmask *); 114 void mips64_tlb_write_indexed_VPS(size_t, struct tlbmask *); 115 void mips64_wbflush(void); 116 void mips64_lwp_trampoline(void); 117 void mips64_setfunc_trampoline(void); 118 void mips64_cpu_switch_resume(void); 119 void mips64_pagezero(void *dst); 120 #endif 121 122 #if defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64) 123 uint32_t mips3_cp0_compare_read(void); 124 void mips3_cp0_compare_write(uint32_t); 125 126 uint32_t mips3_cp0_config_read(void); 127 void mips3_cp0_config_write(uint32_t); 128 #if defined(MIPS32) || defined(MIPS64) 129 uint32_t mipsNN_cp0_config1_read(void); 130 void mipsNN_cp0_config1_write(uint32_t); 131 uint32_t mipsNN_cp0_config2_read(void); 132 uint32_t mipsNN_cp0_config3_read(void); 133 #endif 134 135 uint32_t mips3_cp0_count_read(void); 136 void mips3_cp0_count_write(uint32_t); 137 138 uint32_t mips3_cp0_wired_read(void); 139 void mips3_cp0_wired_write(uint32_t); 140 void mips3_cp0_pg_mask_write(uint32_t); 141 142 #if defined(__GNUC__) && !defined(__mips_o32) 143 static inline uint64_t 144 mips3_ld(const volatile uint64_t *va) 145 { 146 uint64_t rv; 147 #if defined(__mips_o32) 148 uint32_t sr; 149 150 sr = mips_cp0_status_read(); 151 mips_cp0_status_write(sr & ~MIPS_SR_INT_IE); 152 153 __asm volatile( 154 ".set push \n\t" 155 ".set mips3 \n\t" 156 ".set noreorder \n\t" 157 ".set noat \n\t" 158 "ld %M0,0(%1) \n\t" 159 "dsll32 %L0,%M0,0 \n\t" 160 "dsra32 %M0,%M0,0 \n\t" /* high word */ 161 "dsra32 %L0,%L0,0 \n\t" /* low word */ 162 "ld %0,0(%1) \n\t" 163 ".set pop" 164 : "=d"(rv) 165 : "r"(va)); 166 167 mips_cp0_status_write(sr); 168 #elif defined(_LP64) 169 rv = *va; 170 #else 171 __asm volatile("ld %0,0(%1)" : "=d"(rv) : "r"(va)); 172 #endif 173 174 return rv; 175 } 176 static inline void 177 mips3_sd(volatile uint64_t *va, uint64_t v) 178 { 179 #if defined(__mips_o32) 180 uint32_t sr; 181 182 sr = mips_cp0_status_read(); 183 mips_cp0_status_write(sr & ~MIPS_SR_INT_IE); 184 185 __asm volatile( 186 ".set push \n\t" 187 ".set mips3 \n\t" 188 ".set noreorder \n\t" 189 ".set noat \n\t" 190 "dsll32 %M0,%M0,0 \n\t" 191 "dsll32 %L0,%L0,0 \n\t" 192 "dsrl32 %L0,%L0,0 \n\t" 193 "or %0,%L0,%M0 \n\t" 194 "sd %0,0(%1) \n\t" 195 ".set pop" 196 : "=d"(v) : "0"(v), "r"(va)); 197 198 mips_cp0_status_write(sr); 199 #elif defined(_LP64) 200 *va = v; 201 #else 202 __asm volatile("sd %0,0(%1)" :: "r"(v), "r"(va)); 203 #endif 204 } 205 #else 206 uint64_t mips3_ld(volatile uint64_t *va); 207 void mips3_sd(volatile uint64_t *, uint64_t); 208 #endif /* __GNUC__ */ 209 #endif /* MIPS3 || MIPS4 || MIPS32 || MIPS64 */ 210 211 #if defined(MIPS3) || defined(MIPS4) || defined(MIPS64) 212 static __inline uint32_t mips3_lw_a64(uint64_t addr) 213 __attribute__((__unused__)); 214 static __inline void mips3_sw_a64(uint64_t addr, uint32_t val) 215 __attribute__ ((__unused__)); 216 217 static __inline uint32_t 218 mips3_lw_a64(uint64_t addr) 219 { 220 uint32_t rv; 221 #if defined(__mips_o32) 222 uint32_t sr; 223 224 sr = mips_cp0_status_read(); 225 mips_cp0_status_write((sr & ~MIPS_SR_INT_IE) | MIPS3_SR_KX); 226 227 __asm volatile ( 228 ".set push \n\t" 229 ".set mips3 \n\t" 230 ".set noreorder \n\t" 231 ".set noat \n\t" 232 "dsll32 %M1,%M1,0 \n\t" 233 "dsll32 %L1,%L1,0 \n\t" 234 "dsrl32 $L1,%L1,0 \n\t" 235 "or %1,%M1,%L1 \n\t" 236 "lw %0, 0(%1) \n\t" 237 ".set pop" 238 : "=r"(rv), "=d"(addr) 239 : "1"(addr) 240 ); 241 242 mips_cp0_status_write(sr); 243 #elif defined(_LP64) 244 rv = *(const uint32_t *)addr; 245 #else 246 __asm volatile("lw %0, 0(%1)" : "=r"(rv) : "d"(addr)); 247 #endif 248 return (rv); 249 } 250 251 static __inline void 252 mips3_sw_a64(uint64_t addr, uint32_t val) 253 { 254 #if defined(__mips_o32) 255 uint32_t sr; 256 257 sr = mips_cp0_status_read(); 258 mips_cp0_status_write((sr & ~MIPS_SR_INT_IE) | MIPS3_SR_KX); 259 260 __asm volatile ( 261 ".set push \n\t" 262 ".set mips3 \n\t" 263 ".set noreorder \n\t" 264 ".set noat \n\t" 265 "dsll32 %M0,%M0,0 \n\t" 266 "dsll32 %L0,%L0,0 \n\t" 267 "dsrl32 $L0,%L0,0 \n\t" 268 "or %0,%M0,%L0 \n\t" 269 "sw %1, 0(%0) \n\t" 270 ".set pop" 271 : "=d"(addr): "r"(val), "0"(addr) 272 ); 273 274 mips_cp0_status_write(sr); 275 #elif defined(_LP64) 276 *(uint32_t *)addr = val; 277 #else 278 __asm volatile("sw %1, 0(%0)" :: "d"(addr), "r"(val)); 279 #endif 280 } 281 #endif /* MIPS3 || MIPS4 || MIPS64 */ 282 283 /* 284 * A vector with an entry for each mips-ISA-level dependent 285 * locore function, and macros which jump through it. 286 * 287 * XXX the macro names are chosen to be compatible with the old 288 * XXX Sprite coding-convention names used in 4.4bsd/pmax. 289 */ 290 typedef struct { 291 void (*ljv_tlb_set_asid)(uint32_t pid); 292 void (*ljv_tlb_invalidate_asids)(size_t, uint32_t, uint32_t); 293 void (*ljv_tlb_invalidate_addr)(vaddr_t); 294 int (*ljv_tlb_update)(vaddr_t, uint32_t); 295 void (*ljv_tlb_read_indexed)(size_t, struct tlbmask *); 296 void (*ljv_wbflush)(void); 297 } mips_locore_jumpvec_t; 298 299 void mips_set_wbflush(void (*)(void)); 300 void mips_wait_idle(void); 301 302 void stacktrace(void); 303 void logstacktrace(void); 304 305 struct locoresw { 306 uintptr_t lsw_cpu_switch_resume; 307 uintptr_t lsw_lwp_trampoline; 308 void (*lsw_cpu_idle)(void); 309 uintptr_t lsw_setfunc_trampoline; 310 void (*lsw_boot_secondary_processors)(void); 311 }; 312 313 struct mips_vmfreelist { 314 paddr_t fl_start; 315 paddr_t fl_end; 316 int fl_freelist; 317 }; 318 319 /* 320 * The "active" locore-fuction vector, and 321 */ 322 extern mips_locore_jumpvec_t mips_locore_jumpvec; 323 extern struct locoresw mips_locoresw; 324 325 #if defined(MIPS1) && !defined(MIPS3) && !defined(MIPS32) && !defined(MIPS64) 326 #define tlb_set_asid mips1_tlb_set_asid 327 #define tlb_invalidate_asids(asid_lo, asid_hi) \ 328 mips1_tlb_invalidate_asids(mips_options.mips_num_tlb_entries, asid_lo, asid_hi) 329 #define tlb_invalidate_addr mips1_tlb_invalidate_addr 330 #define tlb_invalidate_asid mips1_tlb_invalidate_asid 331 #define tlb_update mips1_tlb_update 332 #define tlb_read_indexed mips1_tlb_read_indexed 333 #define wbflush() mips1_wbflush() 334 #define lwp_trampoline mips1_lwp_trampoline 335 #define setfunc_trampoline mips1_setfunc_trampoline 336 #elif !defined(MIPS1) && defined(MIPS3) && !defined(MIPS32) && !defined(MIPS64) && !defined(MIPS3_5900) 337 #define tlb_set_asid mips3_tlb_set_asid 338 #define tlb_invalidate_asids(asid_lo, asid_hi) \ 339 mips3_tlb_invalidate_asids(mips_options.mips_num_tlb_entries, asid_lo, asid_hi) 340 #define tlb_invalidate_addr mips3_tlb_invalidate_addr 341 #define tlb_invalidate_asid mips3_tlb_invalidate_asid 342 #define tlb_update mips3_tlb_update 343 #define tlb_read_indexed mips3_tlb_read_indexed 344 #define tlb_write_indexed_VPS mips3_tlb_write_indexed_VPS 345 #define lwp_trampoline mips3_lwp_trampoline 346 #define setfunc_trampoline mips3_setfunc_trampoline 347 #define wbflush() mips3_wbflush() 348 #elif !defined(MIPS1) && !defined(MIPS3) && defined(MIPS32) && !defined(MIPS64) 349 #define tlb_set_asid mips32_tlb_set_asid 350 #define tlb_invalidate_asids(asid_lo, asid_hi) \ 351 mips32_tlb_invalidate_asids(mips_options.mips_num_tlb_entries, asid_lo, asid_hi) 352 #define tlb_invalidate_addr mips32_tlb_invalidate_addr 353 #define tlb_invalidate_asid mips32_tlb_invalidate_asid 354 #define tlb_update mips32_tlb_update 355 #define tlb_read_indexed mips32_tlb_read_indexed 356 #define tlb_write_indexed_VPS mips32_tlb_write_indexed_VPS 357 #define lwp_trampoline mips32_lwp_trampoline 358 #define setfunc_trampoline mips32_setfunc_trampoline 359 #define wbflush() mips32_wbflush() 360 #elif !defined(MIPS1) && !defined(MIPS3) && !defined(MIPS32) && defined(MIPS64) 361 /* all common with mips3 */ 362 #define tlb_set_asid mips64_tlb_set_asid 363 #define tlb_invalidate_asids(asid_lo, asid_hi) \ 364 mips64_tlb_invalidate_asids(mips_options.mips_num_tlb_entries, asid_lo, asid_hi) 365 #define tlb_invalidate_addr mips64_tlb_invalidate_addr 366 #define tlb_invalidate_asid mips64_tlb_invalidate_asid 367 #define tlb_update mips64_tlb_update 368 #define tlb_read_indexed mips64_tlb_read_indexed 369 #define tlb_write_indexed_VPS mips64_tlb_write_indexed_VPS 370 #define lwp_trampoline mips64_lwp_trampoline 371 #define setfunc_trampoline mips64_setfunc_trampoline 372 #define wbflush() mips64_wbflush() 373 #elif !defined(MIPS1) && defined(MIPS3) && !defined(MIPS32) && !defined(MIPS64) && defined(MIPS3_5900) 374 #define tlb_set_asid mips5900_tlb_set_asid 375 #define tlb_invalidate_asids(asid_lo, asid_hi) \ 376 mips5900_tlb_invalidate_asids(mips_options.mips_num_tlb_entries, asid_lo, asid_hi) 377 #define tlb_invalidate_addr mips5900_tlb_invalidate_addr 378 #define tlb_invalidate_asid mips5900_tlb_invalidate_asid 379 #define tlb_update mips5900_tlb_update 380 #define tlb_read_indexed mips5900_tlb_read_indexed 381 #define tlb_write_indexed_VPS mips5900_tlb_write_indexed_VPS 382 #define lwp_trampoline mips5900_lwp_trampoline 383 #define setfunc_trampoline mips5900_setfunc_trampoline 384 #define wbflush() mips5900_wbflush() 385 #else 386 #define tlb_set_asid (*(mips_locore_jumpvec.ljv_tlb_set_asid)) 387 #define tlb_invalidate_asids(asid_lo, asid_hi) \ 388 (*(mips_locore_jumpvec.ljv_tlb_invalidate_asids))(mips_options.mips_num_tlb_entries, asid_lo, asid_hi) 389 #define tlb_invalidate_addr (*(mips_locore_jumpvec.ljv_tlb_invalidate_addr)) 390 #define tlb_update (*(mips_locore_jumpvec.ljv_tlb_update)) 391 #define tlb_read_indexed (*(mips_locore_jumpvec.ljv_tlb_read_indexed)) 392 #define wbflush() (*(mips_locore_jumpvec.ljv_wbflush))() 393 #define lwp_trampoline mips_locoresw.lsw_lwp_trampoline 394 #define setfunc_trampoline mips_locoresw.lsw_setfunc_trampoline 395 #endif 396 397 #define CPU_IDLE mips_locoresw.lsw_cpu_idle 398 399 /* cpu_switch_resume is called inside locore.S */ 400 401 /* 402 * CPU identification, from PRID register. 403 */ 404 typedef int mips_prid_t; 405 406 #define MIPS_PRID_REV(x) (((x) >> 0) & 0x00ff) 407 #define MIPS_PRID_IMPL(x) (((x) >> 8) & 0x00ff) 408 409 /* pre-MIPS32/64 */ 410 #define MIPS_PRID_RSVD(x) (((x) >> 16) & 0xffff) 411 #define MIPS_PRID_REV_MIN(x) ((MIPS_PRID_REV(x) >> 0) & 0x0f) 412 #define MIPS_PRID_REV_MAJ(x) ((MIPS_PRID_REV(x) >> 4) & 0x0f) 413 414 /* MIPS32/64 */ 415 #define MIPS_PRID_CID(x) (((x) >> 16) & 0x00ff) /* Company ID */ 416 #define MIPS_PRID_CID_PREHISTORIC 0x00 /* Not MIPS32/64 */ 417 #define MIPS_PRID_CID_MTI 0x01 /* MIPS Technologies, Inc. */ 418 #define MIPS_PRID_CID_BROADCOM 0x02 /* Broadcom */ 419 #define MIPS_PRID_CID_ALCHEMY 0x03 /* Alchemy Semiconductor */ 420 #define MIPS_PRID_CID_SIBYTE 0x04 /* SiByte */ 421 #define MIPS_PRID_CID_SANDCRAFT 0x05 /* SandCraft */ 422 #define MIPS_PRID_CID_PHILIPS 0x06 /* Philips */ 423 #define MIPS_PRID_CID_TOSHIBA 0x07 /* Toshiba */ 424 #define MIPS_PRID_CID_LSI 0x08 /* LSI */ 425 /* 0x09 unannounced */ 426 /* 0x0a unannounced */ 427 #define MIPS_PRID_CID_LEXRA 0x0b /* Lexra */ 428 #define MIPS_PRID_CID_RMI 0x0c /* RMI / NetLogic */ 429 #define MIPS_PRID_COPTS(x) (((x) >> 24) & 0x00ff) /* Company Options */ 430 431 #ifdef _KERNEL 432 /* 433 * Global variables used to communicate CPU type, and parameters 434 * such as cache size, from locore to higher-level code (e.g., pmap). 435 */ 436 void mips_pagecopy(void *dst, void *src); 437 void mips_pagezero(void *dst); 438 439 #ifdef __HAVE_MIPS_MACHDEP_CACHE_CONFIG 440 void mips_machdep_cache_config(void); 441 #endif 442 443 /* 444 * trapframe argument passed to trap() 445 */ 446 447 #define TF_AST 0 448 #define TF_V0 1 449 #define TF_V1 2 450 #define TF_A0 3 451 #define TF_A1 4 452 #define TF_A2 5 453 #define TF_A3 6 454 #define TF_T0 7 455 #define TF_T1 8 456 #define TF_T2 9 457 #define TF_T3 10 458 459 #if defined(__mips_n32) || defined(__mips_n64) 460 #define TF_A4 11 461 #define TF_A5 12 462 #define TF_A6 13 463 #define TF_A7 14 464 #else 465 #define TF_T4 11 466 #define TF_T5 12 467 #define TF_T6 13 468 #define TF_T7 14 469 #endif /* __mips_n32 || __mips_n64 */ 470 471 #define TF_TA0 11 472 #define TF_TA1 12 473 #define TF_TA2 13 474 #define TF_TA3 14 475 476 #define TF_T8 15 477 #define TF_T9 16 478 479 #define TF_RA 17 480 #define TF_SR 18 481 #define TF_MULLO 19 482 #define TF_MULHI 20 483 #define TF_EPC 21 /* may be changed by trap() call */ 484 485 #define TF_NREGS 22 486 487 struct trapframe { 488 mips_reg_t tf_regs[TF_NREGS]; 489 uint32_t tf_ppl; /* previous priority level */ 490 mips_reg_t tf_pad; /* for 8 byte aligned */ 491 }; 492 493 /* 494 * Stack frame for kernel traps. four args passed in registers. 495 * A trapframe is pointed to by the 5th arg, and a dummy sixth argument 496 * is used to avoid alignment problems 497 */ 498 499 struct kernframe { 500 #if defined(__mips_o32) || defined(__mips_o64) 501 register_t cf_args[4 + 1]; 502 #if defined(__mips_o32) 503 register_t cf_pad; /* (for 8 word alignment) */ 504 #endif 505 #endif 506 #if defined(__mips_n32) || defined(__mips_n64) 507 register_t cf_pad[2]; /* for 16 byte alignment */ 508 #endif 509 register_t cf_sp; 510 register_t cf_ra; 511 struct trapframe cf_frame; 512 }; 513 #endif /* _KERNEL */ 514 #endif /* _MIPS_LOCORE_H */ 515
Indexes created Sun Sep 28 16:09:52 GMT 2025