locore.h revision 1.79
1 /* $NetBSD: locore.h,v 1.79 2009/05/30 18:26:06 martin Exp $ */ 2 3 /* 4 * Copyright 1996 The Board of Trustees of The Leland Stanford 5 * Junior University. All Rights Reserved. 6 * 7 * Permission to use, copy, modify, and distribute this 8 * software and its documentation for any purpose and without 9 * fee is hereby granted, provided that the above copyright 10 * notice appear in all copies. Stanford University 11 * makes no representations about the suitability of this 12 * software for any purpose. It is provided "as is" without 13 * express or implied warranty. 14 */ 15 16 /* 17 * Jump table for MIPS CPU locore functions that are implemented 18 * differently on different generations, or instruction-level 19 * archtecture (ISA) level, the Mips family. 20 * 21 * We currently provide support for MIPS I and MIPS III. 22 */ 23 24 #ifndef _MIPS_LOCORE_H 25 #define _MIPS_LOCORE_H 26 27 #ifndef _LKM 28 #include "opt_cputype.h" 29 #endif 30 31 #include <mips/cpuregs.h> 32 33 struct tlb; 34 35 uint32_t mips_cp0_cause_read(void); 36 void mips_cp0_cause_write(uint32_t); 37 uint32_t mips_cp0_status_read(void); 38 void mips_cp0_status_write(uint32_t); 39 40 int _splraise(int); 41 int _spllower(int); 42 int _splset(int); 43 int _splget(void); 44 void _splnone(void); 45 void _setsoftintr(int); 46 void _clrsoftintr(int); 47 48 #ifdef MIPS1 49 void mips1_SetPID(int); 50 void mips1_TBIA(int); 51 void mips1_TBIAP(int); 52 void mips1_TBIS(vaddr_t); 53 int mips1_TLBUpdate(u_int, u_int); 54 void mips1_wbflush(void); 55 void mips1_lwp_trampoline(void); 56 void mips1_setfunc_trampoline(void); 57 void mips1_cpu_switch_resume(void); 58 59 uint32_t tx3900_cp0_config_read(void); 60 #endif 61 62 #if defined(MIPS3) || defined(MIPS4) 63 void mips3_SetPID(int); 64 void mips3_TBIA(int); 65 void mips3_TBIAP(int); 66 void mips3_TBIS(vaddr_t); 67 int mips3_TLBUpdate(u_int, u_int); 68 void mips3_TLBRead(int, struct tlb *); 69 void mips3_TLBWriteIndexedVPS(int, struct tlb *); 70 void mips3_wbflush(void); 71 void mips3_lwp_trampoline(void); 72 void mips3_setfunc_trampoline(void); 73 void mips3_cpu_switch_resume(void); 74 void mips3_pagezero(void *dst); 75 76 #ifdef MIPS3_5900 77 void mips5900_SetPID(int); 78 void mips5900_TBIA(int); 79 void mips5900_TBIAP(int); 80 void mips5900_TBIS(vaddr_t); 81 int mips5900_TLBUpdate(u_int, u_int); 82 void mips5900_TLBRead(int, struct tlb *); 83 void mips5900_TLBWriteIndexedVPS(int, struct tlb *); 84 void mips5900_wbflush(void); 85 void mips5900_lwp_trampoline(void); 86 void mips5900_setfunc_trampoline(void); 87 void mips5900_cpu_switch_resume(void); 88 void mips5900_pagezero(void *dst); 89 #endif 90 #endif 91 92 #ifdef MIPS32 93 void mips32_SetPID(int); 94 void mips32_TBIA(int); 95 void mips32_TBIAP(int); 96 void mips32_TBIS(vaddr_t); 97 int mips32_TLBUpdate(u_int, u_int); 98 void mips32_TLBRead(int, struct tlb *); 99 void mips32_TLBWriteIndexedVPS(int, struct tlb *); 100 void mips32_wbflush(void); 101 void mips32_lwp_trampoline(void); 102 void mips32_setfunc_trampoline(void); 103 void mips32_cpu_switch_resume(void); 104 #endif 105 106 #ifdef MIPS64 107 void mips64_SetPID(int); 108 void mips64_TBIA(int); 109 void mips64_TBIAP(int); 110 void mips64_TBIS(vaddr_t); 111 int mips64_TLBUpdate(u_int, u_int); 112 void mips64_TLBRead(int, struct tlb *); 113 void mips64_TLBWriteIndexedVPS(int, struct tlb *); 114 void mips64_wbflush(void); 115 void mips64_lwp_trampoline(void); 116 void mips64_setfunc_trampoline(void); 117 void mips64_cpu_switch_resume(void); 118 void mips64_pagezero(void *dst); 119 #endif 120 121 #if defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64) 122 uint32_t mips3_cp0_compare_read(void); 123 void mips3_cp0_compare_write(uint32_t); 124 125 uint32_t mips3_cp0_config_read(void); 126 void mips3_cp0_config_write(uint32_t); 127 #if defined(MIPS32) || defined(MIPS64) 128 uint32_t mipsNN_cp0_config1_read(void); 129 void mipsNN_cp0_config1_write(uint32_t); 130 uint32_t mipsNN_cp0_config2_read(void); 131 uint32_t mipsNN_cp0_config3_read(void); 132 #endif 133 134 uint32_t mips3_cp0_count_read(void); 135 void mips3_cp0_count_write(uint32_t); 136 137 uint32_t mips3_cp0_wired_read(void); 138 void mips3_cp0_wired_write(uint32_t); 139 void mips3_cp0_pg_mask_write(uint32_t); 140 141 uint64_t mips3_ld(uint64_t *); 142 void mips3_sd(uint64_t *, uint64_t); 143 #endif /* MIPS3 || MIPS4 || MIPS32 || MIPS64 */ 144 145 #if defined(MIPS3) || defined(MIPS4) || defined(MIPS64) 146 static __inline uint32_t mips3_lw_a64(uint64_t addr) 147 __attribute__((__unused__)); 148 static __inline void mips3_sw_a64(uint64_t addr, uint32_t val) 149 __attribute__ ((__unused__)); 150 151 static __inline uint32_t 152 mips3_lw_a64(uint64_t addr) 153 { 154 uint32_t addrlo, addrhi; 155 uint32_t rv; 156 uint32_t sr; 157 158 sr = mips_cp0_status_read(); 159 mips_cp0_status_write(sr | MIPS3_SR_KX); 160 161 addrlo = addr & 0xffffffff; 162 addrhi = addr >> 32; 163 __asm volatile (" \n\ 164 .set push \n\ 165 .set mips3 \n\ 166 .set noreorder \n\ 167 .set noat \n\ 168 dsll32 $3, %1, 0 \n\ 169 dsll32 $1, %2, 0 \n\ 170 dsrl32 $3, $3, 0 \n\ 171 or $1, $1, $3 \n\ 172 lw %0, 0($1) \n\ 173 .set pop \n\ 174 " : "=r"(rv) : "r"(addrlo), "r"(addrhi) : "$1", "$3" ); 175 176 mips_cp0_status_write(sr); 177 178 return (rv); 179 } 180 181 static __inline void 182 mips3_sw_a64(uint64_t addr, uint32_t val) 183 { 184 uint32_t addrlo, addrhi; 185 uint32_t sr; 186 187 sr = mips_cp0_status_read(); 188 mips_cp0_status_write(sr | MIPS3_SR_KX); 189 190 addrlo = addr & 0xffffffff; 191 addrhi = addr >> 32; 192 __asm volatile (" \n\ 193 .set push \n\ 194 .set mips3 \n\ 195 .set noreorder \n\ 196 .set noat \n\ 197 dsll32 $3, %1, 0 \n\ 198 dsll32 $1, %2, 0 \n\ 199 dsrl32 $3, $3, 0 \n\ 200 or $1, $1, $3 \n\ 201 sw %0, 0($1) \n\ 202 .set pop \n\ 203 " : : "r"(val), "r"(addrlo), "r"(addrhi) : "$1", "$3" ); 204 205 mips_cp0_status_write(sr); 206 } 207 #endif /* MIPS3 || MIPS4 || MIPS64 */ 208 209 /* 210 * A vector with an entry for each mips-ISA-level dependent 211 * locore function, and macros which jump through it. 212 * 213 * XXX the macro names are chosen to be compatible with the old 214 * XXX Sprite coding-convention names used in 4.4bsd/pmax. 215 */ 216 typedef struct { 217 void (*setTLBpid)(int pid); 218 void (*TBIAP)(int); 219 void (*TBIS)(vaddr_t); 220 int (*tlbUpdate)(u_int highreg, u_int lowreg); 221 void (*wbflush)(void); 222 } mips_locore_jumpvec_t; 223 224 void mips_set_wbflush(void (*)(void)); 225 void mips_wait_idle(void); 226 227 void stacktrace(void); 228 void logstacktrace(void); 229 230 /* 231 * The "active" locore-fuction vector, and 232 */ 233 extern mips_locore_jumpvec_t mips_locore_jumpvec; 234 extern long *mips_locoresw[]; 235 236 #if defined(MIPS1) && !defined(MIPS3) && !defined(MIPS32) && !defined(MIPS64) 237 #define MachSetPID mips1_SetPID 238 #define MIPS_TBIAP() mips1_TBIAP(mips_num_tlb_entries) 239 #define MIPS_TBIS mips1_TBIS 240 #define MachTLBUpdate mips1_TLBUpdate 241 #define wbflush() mips1_wbflush() 242 #define lwp_trampoline mips1_lwp_trampoline 243 #define setfunc_trampoline mips1_setfunc_trampoline 244 #elif !defined(MIPS1) && defined(MIPS3) && !defined(MIPS32) && !defined(MIPS64) && !defined(MIPS3_5900) 245 #define MachSetPID mips3_SetPID 246 #define MIPS_TBIAP() mips3_TBIAP(mips_num_tlb_entries) 247 #define MIPS_TBIS mips3_TBIS 248 #define MachTLBUpdate mips3_TLBUpdate 249 #define MachTLBWriteIndexedVPS mips3_TLBWriteIndexedVPS 250 #define lwp_trampoline mips3_lwp_trampoline 251 #define setfunc_trampoline mips3_setfunc_trampoline 252 #define wbflush() mips3_wbflush() 253 #elif !defined(MIPS1) && !defined(MIPS3) && defined(MIPS32) && !defined(MIPS64) 254 #define MachSetPID mips32_SetPID 255 #define MIPS_TBIAP() mips32_TBIAP(mips_num_tlb_entries) 256 #define MIPS_TBIS mips32_TBIS 257 #define MachTLBUpdate mips32_TLBUpdate 258 #define MachTLBWriteIndexedVPS mips32_TLBWriteIndexedVPS 259 #define lwp_trampoline mips32_lwp_trampoline 260 #define setfunc_trampoline mips32_setfunc_trampoline 261 #define wbflush() mips32_wbflush() 262 #elif !defined(MIPS1) && !defined(MIPS3) && !defined(MIPS32) && defined(MIPS64) 263 /* all common with mips3 */ 264 #define MachSetPID mips64_SetPID 265 #define MIPS_TBIAP() mips64_TBIAP(mips_num_tlb_entries) 266 #define MIPS_TBIS mips64_TBIS 267 #define MachTLBUpdate mips64_TLBUpdate 268 #define MachTLBWriteIndexedVPS mips64_TLBWriteIndexedVPS 269 #define lwp_trampoline mips64_lwp_trampoline 270 #define setfunc_trampoline mips64_setfunc_trampoline 271 #define wbflush() mips64_wbflush() 272 #elif !defined(MIPS1) && defined(MIPS3) && !defined(MIPS32) && !defined(MIPS64) && defined(MIPS3_5900) 273 #define MachSetPID mips5900_SetPID 274 #define MIPS_TBIAP() mips5900_TBIAP(mips_num_tlb_entries) 275 #define MIPS_TBIS mips5900_TBIS 276 #define MachTLBUpdate mips5900_TLBUpdate 277 #define MachTLBWriteIndexedVPS mips5900_TLBWriteIndexedVPS 278 #define lwp_trampoline mips5900_lwp_trampoline 279 #define setfunc_trampoline mips5900_setfunc_trampoline 280 #define wbflush() mips5900_wbflush() 281 #else 282 #define MachSetPID (*(mips_locore_jumpvec.setTLBpid)) 283 #define MIPS_TBIAP() (*(mips_locore_jumpvec.TBIAP))(mips_num_tlb_entries) 284 #define MIPS_TBIS (*(mips_locore_jumpvec.TBIS)) 285 #define MachTLBUpdate (*(mips_locore_jumpvec.tlbUpdate)) 286 #define wbflush() (*(mips_locore_jumpvec.wbflush))() 287 #define lwp_trampoline (mips_locoresw[1]) 288 #define setfunc_trampoline (mips_locoresw[3]) 289 #endif 290 291 #define CPU_IDLE (mips_locoresw[2]) 292 293 /* cpu_switch_resume is called inside locore.S */ 294 295 /* 296 * CPU identification, from PRID register. 297 */ 298 typedef int mips_prid_t; 299 300 #define MIPS_PRID_REV(x) (((x) >> 0) & 0x00ff) 301 #define MIPS_PRID_IMPL(x) (((x) >> 8) & 0x00ff) 302 303 /* pre-MIPS32/64 */ 304 #define MIPS_PRID_RSVD(x) (((x) >> 16) & 0xffff) 305 #define MIPS_PRID_REV_MIN(x) ((MIPS_PRID_REV(x) >> 0) & 0x0f) 306 #define MIPS_PRID_REV_MAJ(x) ((MIPS_PRID_REV(x) >> 4) & 0x0f) 307 308 /* MIPS32/64 */ 309 #define MIPS_PRID_CID(x) (((x) >> 16) & 0x00ff) /* Company ID */ 310 #define MIPS_PRID_CID_PREHISTORIC 0x00 /* Not MIPS32/64 */ 311 #define MIPS_PRID_CID_MTI 0x01 /* MIPS Technologies, Inc. */ 312 #define MIPS_PRID_CID_BROADCOM 0x02 /* Broadcom */ 313 #define MIPS_PRID_CID_ALCHEMY 0x03 /* Alchemy Semiconductor */ 314 #define MIPS_PRID_CID_SIBYTE 0x04 /* SiByte */ 315 #define MIPS_PRID_CID_SANDCRAFT 0x05 /* SandCraft */ 316 #define MIPS_PRID_CID_PHILIPS 0x06 /* Philips */ 317 #define MIPS_PRID_CID_TOSHIBA 0x07 /* Toshiba */ 318 #define MIPS_PRID_CID_LSI 0x08 /* LSI */ 319 /* 0x09 unannounced */ 320 /* 0x0a unannounced */ 321 #define MIPS_PRID_CID_LEXRA 0x0b /* Lexra */ 322 #define MIPS_PRID_COPTS(x) (((x) >> 24) & 0x00ff) /* Company Options */ 323 324 #ifdef _KERNEL 325 /* 326 * Global variables used to communicate CPU type, and parameters 327 * such as cache size, from locore to higher-level code (e.g., pmap). 328 */ 329 330 extern mips_prid_t cpu_id; 331 extern mips_prid_t fpu_id; 332 extern int mips_num_tlb_entries; 333 334 void mips_pagecopy(void *dst, void *src); 335 void mips_pagezero(void *dst); 336 337 #ifdef __HAVE_MIPS_MACHDEP_CACHE_CONFIG 338 void mips_machdep_cache_config(void); 339 #endif 340 341 /* 342 * trapframe argument passed to trap() 343 */ 344 345 #define TF_AST 0 346 #define TF_V0 1 347 #define TF_V1 2 348 #define TF_A0 3 349 #define TF_A1 4 350 #define TF_A2 5 351 #define TF_A3 6 352 #define TF_T0 7 353 #define TF_T1 8 354 #define TF_T2 9 355 #define TF_T3 10 356 357 #if defined(__mips_n32) || defined(__mips_n64) 358 #define TF_A4 11 359 #define TF_A5 12 360 #define TF_A6 13 361 #define TF_A7 14 362 #else 363 #define TF_T4 11 364 #define TF_T5 12 365 #define TF_T6 13 366 #define TF_T7 14 367 #endif /* __mips_n32 || __mips_n64 */ 368 369 #define TF_TA0 11 370 #define TF_TA1 12 371 #define TF_TA2 13 372 #define TF_TA3 14 373 374 #define TF_T8 15 375 #define TF_T9 16 376 377 #define TF_RA 17 378 #define TF_SR 18 379 #define TF_MULLO 19 380 #define TF_MULHI 20 381 #define TF_EPC 21 /* may be changed by trap() call */ 382 383 #define TF_NREGS 22 384 385 struct trapframe { 386 mips_reg_t tf_regs[TF_NREGS]; 387 u_int32_t tf_ppl; /* previous priority level */ 388 int32_t tf_pad; /* for 8 byte aligned */ 389 }; 390 391 /* 392 * Stack frame for kernel traps. four args passed in registers. 393 * A trapframe is pointed to by the 5th arg, and a dummy sixth argument 394 * is used to avoid alignment problems 395 */ 396 397 struct kernframe { 398 register_t cf_args[4 + 1]; 399 register_t cf_pad; /* (for 8 word alignment) */ 400 register_t cf_sp; 401 register_t cf_ra; 402 struct trapframe cf_frame; 403 }; 404 #endif /* _KERNEL */ 405 #endif /* _MIPS_LOCORE_H */ 406
Indexes created Mon Sep 29 21:09:56 GMT 2025