locore.h revision 1.8
1 /* $NetBSD: locore.h,v 1.8 1997/06/16 23:41:43 jonathan Exp $ */ 2 3 /* 4 * Copyright 1996 The Board of Trustees of The Leland Stanford 5 * Junior University. All Rights Reserved. 6 * 7 * Permission to use, copy, modify, and distribute this 8 * software and its documentation for any purpose and without 9 * fee is hereby granted, provided that the above copyright 10 * notice appear in all copies. Stanford University 11 * makes no representations about the suitability of this 12 * software for any purpose. It is provided "as is" without 13 * express or implied warranty. 14 */ 15 16 /* 17 * Jump table for MIPS cpu locore functions that are implemented 18 * differently on different generations, or instruction-level 19 * archtecture (ISA) level, the Mips family. 20 * The following functions must be provided for each mips ISA level: 21 * 22 * 23 * MachConfigCache 24 * MachFlushCache 25 * MachFlushDCache 26 * MachFlushICache 27 * MachForceCacheUpdate 28 * MachSetPID 29 * MachTLBFlush 30 * MachTLBFlushAddr __P() 31 * MachTLBUpdate (u_int, (pt_entry_t?) u_int); 32 * MachTLBWriteIndexed 33 * wbflush 34 * proc_trampoline() 35 * 36 * We currently provide support for: 37 * 38 * r2000 and r3000 (mips ISA-I) 39 * r4000 and r4400 in 32-bit mode (mips ISA-III?) 40 */ 41 42 #ifndef _MIPS_LOCORE_H 43 #define _MIPS_LOCORE_H 44 45 /* 46 * locore service routine for exeception vectors. Used outside locore 47 * only to print them by name in stack tracebacks 48 */ 49 50 extern void mips1_ConfigCache __P((void)); 51 extern void mips1_FlushCache __P((void)); 52 extern void mips1_FlushDCache __P((vm_offset_t addr, vm_offset_t len)); 53 extern void mips1_FlushICache __P((vm_offset_t addr, vm_offset_t len)); 54 extern void mips1_ForceCacheUpdate __P((void)); 55 extern void mips1_SetPID __P((int pid)); 56 extern void mips1_TLBFlush __P((void)); 57 extern void mips1_TLBFlushAddr __P( /* XXX Really pte highpart ? */ 58 (vm_offset_t addr)); 59 extern int mips1_TLBUpdate __P((u_int, /*pt_entry_t*/ u_int)); 60 extern void mips1_TLBWriteIndexed __P((u_int index, u_int high, 61 u_int low)); 62 extern void mips1_wbflush __P((void)); 63 extern void mips1_proc_trampoline __P((void)); 64 65 extern void mips3_ConfigCache __P((void)); 66 extern void mips3_FlushCache __P((void)); 67 extern void mips3_FlushDCache __P((vm_offset_t addr, vm_offset_t len)); 68 extern void mips3_FlushICache __P((vm_offset_t addr, vm_offset_t len)); 69 extern void mips3_ForceCacheUpdate __P((void)); 70 extern void mips3_HitFlushDCache __P((vm_offset_t, int)); 71 extern void mips3_SetPID __P((int pid)); 72 extern void mips3_TLBFlush __P((void)); 73 extern void mips3_TLBFlushAddr __P( /* XXX Really pte highpart ? */ 74 (vm_offset_t addr)); 75 extern int mips3_TLBUpdate __P((u_int, /*pt_entry_t*/ u_int)); 76 extern void mips3_TLBWriteIndexedVPS __P((u_int index, void *tlb)); 77 extern void mips3_TLBWriteIndexed __P((u_int index, u_int high, 78 u_int lo0, u_int lo1)); 79 extern void mips3_wbflush __P((void)); 80 extern void mips3_proc_trampoline __P((void)); 81 82 extern void MachHitFlushDCache __P((caddr_t, int)); 83 extern void mips3_SetWIRED __P((int)); 84 85 86 /* 87 * A vector with an entry for each mips-ISA-level dependent 88 * locore function, and macros which jump through it. 89 * XXX the macro names are chosen to be compatible with the old 90 * Sprite coding-convention names used in 4.4bsd/pmax. 91 */ 92 typedef struct { 93 void (*configCache) __P((void)); 94 void (*flushCache) __P((void)); 95 void (*flushDCache) __P((vm_offset_t addr, vm_offset_t len)); 96 void (*flushICache) __P((vm_offset_t addr, vm_offset_t len)); 97 void (*forceCacheUpdate) __P((void)); 98 void (*setTLBpid) __P((int pid)); 99 void (*tlbFlush) __P((void)); 100 void (*tlbFlushAddr) __P((vm_offset_t)); /* XXX Really pte highpart ? */ 101 int (*tlbUpdate) __P((u_int highreg, u_int lowreg)); 102 #ifdef MIPS3 103 void (*tlbWriteIndexed) __P((u_int, u_int, u_int, u_int)); 104 #else 105 void (*tlbWriteIndexed) __P((u_int, u_int, u_int)); 106 #endif 107 void (*wbflush) __P((void)); 108 void (*proc_trampoline) __P((void)); 109 } mips_locore_jumpvec_t; 110 111 112 /* 113 * The "active" locore-fuction vector, and 114 115 */ 116 extern mips_locore_jumpvec_t mips_locore_jumpvec; 117 extern mips_locore_jumpvec_t r2000_locore_vec; 118 extern mips_locore_jumpvec_t r4000_locore_vec; 119 120 #define MachConfigCache (*(mips_locore_jumpvec.configCache)) 121 #define MachFlushCache (*(mips_locore_jumpvec.flushCache)) 122 #define MachFlushDCache (*(mips_locore_jumpvec.flushDCache)) 123 #define MachFlushICache (*(mips_locore_jumpvec.flushICache)) 124 #define MachForceCacheUpdate (*(mips_locore_jumpvec.forceCacheUpdate)) 125 #define MachSetPID (*(mips_locore_jumpvec.setTLBpid)) 126 #define MachTLBFlush (*(mips_locore_jumpvec.tlbFlush)) 127 #define MachTLBFlushAddr (*(mips_locore_jumpvec.tlbFlushAddr)) 128 #define MachTLBUpdate (*(mips_locore_jumpvec.tlbUpdate)) 129 #define MachTLBWriteIndexed (*(mips_locore_jumpvec.tlbWriteIndexed)) 130 #define wbflush (*(mips_locore_jumpvec.wbflush)) 131 #define proc_trampoline (mips_locore_jumpvec.proc_trampoline) 132 133 134 /* 135 * CPU identification, from PRID register. 136 */ 137 union cpuprid { 138 int cpuprid; 139 struct { 140 #if BYTE_ORDER == BIG_ENDIAN 141 u_int pad1:16; /* reserved */ 142 u_int cp_imp:8; /* implementation identifier */ 143 u_int cp_majrev:4; /* major revision identifier */ 144 u_int cp_minrev:4; /* minor revision identifier */ 145 #else 146 u_int cp_minrev:4; /* minor revision identifier */ 147 u_int cp_majrev:4; /* major revision identifier */ 148 u_int cp_imp:8; /* implementation identifier */ 149 u_int pad1:16; /* reserved */ 150 #endif 151 } cpu; 152 }; 153 154 155 #ifdef _KERNEL 156 157 /* 158 * Global variables used to communicate CPU type, and parameters 159 * such as cache size, from locore to higher-level code (e.g., pmap). 160 */ 161 extern union cpuprid cpu_id; 162 extern union cpuprid fpu_id; 163 extern int cpu_arch; 164 extern u_int machDataCacheSize; 165 extern u_int machInstCacheSize; 166 extern u_int machPrimaryDataCacheSize; 167 extern u_int machPrimaryInstCacheSize; 168 extern u_int machPrimaryDataCacheLSize; 169 extern u_int machPrimaryInstCacheLSize; 170 extern u_int machSecondaryCacheSize; 171 extern u_int machSecondaryCacheLSize; 172 extern u_int machCacheAliasMask; 173 extern struct intr_tab intr_tab[]; 174 #endif 175 176 #endif /* _MIPS_LOCORE_H */ 177
Indexes created Mon Sep 29 21:09:56 GMT 2025