locore.h revision 1.80
1 /* $NetBSD: locore.h,v 1.80 2009/12/14 00:46:04 matt Exp $ */ 2 3 /* 4 * Copyright 1996 The Board of Trustees of The Leland Stanford 5 * Junior University. All Rights Reserved. 6 * 7 * Permission to use, copy, modify, and distribute this 8 * software and its documentation for any purpose and without 9 * fee is hereby granted, provided that the above copyright 10 * notice appear in all copies. Stanford University 11 * makes no representations about the suitability of this 12 * software for any purpose. It is provided "as is" without 13 * express or implied warranty. 14 */ 15 16 /* 17 * Jump table for MIPS CPU locore functions that are implemented 18 * differently on different generations, or instruction-level 19 * archtecture (ISA) level, the Mips family. 20 * 21 * We currently provide support for MIPS I and MIPS III. 22 */ 23 24 #ifndef _MIPS_LOCORE_H 25 #define _MIPS_LOCORE_H 26 27 #ifndef _LKM 28 #include "opt_cputype.h" 29 #endif 30 31 #include <mips/cpuregs.h> 32 33 struct tlb; 34 35 uint32_t mips_cp0_cause_read(void); 36 void mips_cp0_cause_write(uint32_t); 37 uint32_t mips_cp0_status_read(void); 38 void mips_cp0_status_write(uint32_t); 39 40 int _splraise(int); 41 int _spllower(int); 42 int _splset(int); 43 int _splget(void); 44 void _splnone(void); 45 void _setsoftintr(int); 46 void _clrsoftintr(int); 47 48 #ifdef MIPS1 49 void mips1_SetPID(int); 50 void mips1_TBIA(int); 51 void mips1_TBIAP(int); 52 void mips1_TBIS(vaddr_t); 53 int mips1_TLBUpdate(vaddr_t, uint32_t); 54 void mips1_wbflush(void); 55 void mips1_lwp_trampoline(void); 56 void mips1_setfunc_trampoline(void); 57 void mips1_cpu_switch_resume(void); 58 59 uint32_t tx3900_cp0_config_read(void); 60 #endif 61 62 #if defined(MIPS3) || defined(MIPS4) 63 void mips3_SetPID(int); 64 void mips3_TBIA(int); 65 void mips3_TBIAP(int); 66 void mips3_TBIS(vaddr_t); 67 int mips3_TLBUpdate(vaddr_t, uint32_t); 68 void mips3_TLBRead(int, struct tlb *); 69 void mips3_TLBWriteIndexedVPS(int, struct tlb *); 70 void mips3_wbflush(void); 71 void mips3_lwp_trampoline(void); 72 void mips3_setfunc_trampoline(void); 73 void mips3_cpu_switch_resume(void); 74 void mips3_pagezero(void *dst); 75 76 #ifdef MIPS3_5900 77 void mips5900_SetPID(int); 78 void mips5900_TBIA(int); 79 void mips5900_TBIAP(int); 80 void mips5900_TBIS(vaddr_t); 81 int mips5900_TLBUpdate(vaddr_t, uint32_t); 82 void mips5900_TLBRead(int, struct tlb *); 83 void mips5900_TLBWriteIndexedVPS(int, struct tlb *); 84 void mips5900_wbflush(void); 85 void mips5900_lwp_trampoline(void); 86 void mips5900_setfunc_trampoline(void); 87 void mips5900_cpu_switch_resume(void); 88 void mips5900_pagezero(void *dst); 89 #endif 90 #endif 91 92 #ifdef MIPS32 93 void mips32_SetPID(int); 94 void mips32_TBIA(int); 95 void mips32_TBIAP(int); 96 void mips32_TBIS(vaddr_t); 97 int mips32_TLBUpdate(vaddr_t, uint32_t); 98 void mips32_TLBRead(int, struct tlb *); 99 void mips32_TLBWriteIndexedVPS(int, struct tlb *); 100 void mips32_wbflush(void); 101 void mips32_lwp_trampoline(void); 102 void mips32_setfunc_trampoline(void); 103 void mips32_cpu_switch_resume(void); 104 #endif 105 106 #ifdef MIPS64 107 void mips64_SetPID(int); 108 void mips64_TBIA(int); 109 void mips64_TBIAP(int); 110 void mips64_TBIS(vaddr_t); 111 int mips64_TLBUpdate(vaddr_t, uint32_t); 112 void mips64_TLBRead(int, struct tlb *); 113 void mips64_TLBWriteIndexedVPS(int, struct tlb *); 114 void mips64_wbflush(void); 115 void mips64_lwp_trampoline(void); 116 void mips64_setfunc_trampoline(void); 117 void mips64_cpu_switch_resume(void); 118 void mips64_pagezero(void *dst); 119 #endif 120 121 #if defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64) 122 uint32_t mips3_cp0_compare_read(void); 123 void mips3_cp0_compare_write(uint32_t); 124 125 uint32_t mips3_cp0_config_read(void); 126 void mips3_cp0_config_write(uint32_t); 127 #if defined(MIPS32) || defined(MIPS64) 128 uint32_t mipsNN_cp0_config1_read(void); 129 void mipsNN_cp0_config1_write(uint32_t); 130 uint32_t mipsNN_cp0_config2_read(void); 131 uint32_t mipsNN_cp0_config3_read(void); 132 #endif 133 134 uint32_t mips3_cp0_count_read(void); 135 void mips3_cp0_count_write(uint32_t); 136 137 uint32_t mips3_cp0_wired_read(void); 138 void mips3_cp0_wired_write(uint32_t); 139 void mips3_cp0_pg_mask_write(uint32_t); 140 141 #if defined(__GNUC__) && !defined(__mips_o32) 142 static inline uint64_t 143 mips3_ld(const volatile uint64_t *va) 144 { 145 uint64_t rv; 146 #if defined(__mips_o32) 147 uint32_t sr; 148 149 sr = mips_cp0_status_read(); 150 mips_cp0_status_write(sr & ~MIPS_SR_INT_IE); 151 152 __asm volatile( 153 ".set push \n\t" 154 ".set mips3 \n\t" 155 ".set noreorder \n\t" 156 ".set noat \n\t" 157 "ld %M0,0(%1) \n\t" 158 "dsll32 %L0,%M0,0 \n\t" 159 "dsra32 %M0,%M0,0 \n\t" /* high word */ 160 "dsra32 %L0,%L0,0 \n\t" /* low word */ 161 "ld %0,0(%1) \n\t" 162 ".set pop" 163 : "=d"(rv) 164 : "r"(va)); 165 166 mips_cp0_status_write(sr); 167 #elif defined(_LP64) 168 rv = *va; 169 #else 170 __asm volatile("ld %0,0(%1)" : "=d"(rv) : "r"(va)); 171 #endif 172 173 return rv; 174 } 175 static inline void 176 mips3_sd(volatile uint64_t *va, uint64_t v) 177 { 178 #if defined(__mips_o32) 179 uint32_t sr; 180 181 sr = mips_cp0_status_read(); 182 mips_cp0_status_write(sr & ~MIPS_SR_INT_IE); 183 184 __asm volatile( 185 ".set push \n\t" 186 ".set mips3 \n\t" 187 ".set noreorder \n\t" 188 ".set noat \n\t" 189 "dsll32 %M0,%M0,0 \n\t" 190 "dsll32 %L0,%L0,0 \n\t" 191 "dsrl32 %L0,%L0,0 \n\t" 192 "or %0,%L0,%M0 \n\t" 193 "sd %0,0(%1) \n\t" 194 ".set pop" 195 : "=d"(v) : "0"(v), "r"(va)); 196 197 mips_cp0_status_write(sr); 198 #elif defined(_LP64) 199 *va = v; 200 #else 201 __asm volatile("sd %0,0(%1)" :: "r"(v), "r"(va)); 202 #endif 203 } 204 #else 205 uint64_t mips3_ld(volatile uint64_t *va); 206 void mips3_sd(volatile uint64_t *, uint64_t); 207 #endif /* __GNUC__ */ 208 #endif /* MIPS3 || MIPS4 || MIPS32 || MIPS64 */ 209 210 #if defined(MIPS3) || defined(MIPS4) || defined(MIPS64) 211 static __inline uint32_t mips3_lw_a64(uint64_t addr) 212 __attribute__((__unused__)); 213 static __inline void mips3_sw_a64(uint64_t addr, uint32_t val) 214 __attribute__ ((__unused__)); 215 216 static __inline uint32_t 217 mips3_lw_a64(uint64_t addr) 218 { 219 uint32_t rv; 220 #if defined(__mips_o32) 221 uint32_t sr; 222 223 sr = mips_cp0_status_read(); 224 mips_cp0_status_write((sr & ~MIPS_SR_INT_IE) | MIPS3_SR_KX); 225 226 __asm volatile ( 227 ".set push \n\t" 228 ".set mips3 \n\t" 229 ".set noreorder \n\t" 230 ".set noat \n\t" 231 "dsll32 %M1,%M1,0 \n\t" 232 "dsll32 %L1,%L1,0 \n\t" 233 "dsrl32 $L1,%L1,0 \n\t" 234 "or %1,%M1,%L1 \n\t" 235 "lw %0, 0(%1) \n\t" 236 ".set pop" 237 : "=r"(rv), "=d"(addr) 238 : "1"(addr) 239 ); 240 241 mips_cp0_status_write(sr); 242 #elif defined(_LP64) 243 rv = *(const uint32_t *)addr; 244 #else 245 __asm volatile("lw %0, 0(%1)" : "=r"(rv) : "d"(addr)); 246 #endif 247 return (rv); 248 } 249 250 static __inline void 251 mips3_sw_a64(uint64_t addr, uint32_t val) 252 { 253 #if defined(__mips_o32) 254 uint32_t sr; 255 256 sr = mips_cp0_status_read(); 257 mips_cp0_status_write((sr & ~MIPS_SR_INT_IE) | MIPS3_SR_KX); 258 259 __asm volatile ( 260 ".set push \n\t" 261 ".set mips3 \n\t" 262 ".set noreorder \n\t" 263 ".set noat \n\t" 264 "dsll32 %M0,%M0,0 \n\t" 265 "dsll32 %L0,%L0,0 \n\t" 266 "dsrl32 $L0,%L0,0 \n\t" 267 "or %0,%M0,%L0 \n\t" 268 "sw %1, 0(%0) \n\t" 269 ".set pop" 270 : "=d"(addr): "r"(val), "0"(addr) 271 ); 272 273 mips_cp0_status_write(sr); 274 #elif defined(_LP64) 275 *(uint32_t *)addr = val; 276 #else 277 __asm volatile("sw %1, 0(%0)" :: "d"(addr), "r"(val)); 278 #endif 279 } 280 #endif /* MIPS3 || MIPS4 || MIPS64 */ 281 282 /* 283 * A vector with an entry for each mips-ISA-level dependent 284 * locore function, and macros which jump through it. 285 * 286 * XXX the macro names are chosen to be compatible with the old 287 * XXX Sprite coding-convention names used in 4.4bsd/pmax. 288 */ 289 typedef struct { 290 void (*setTLBpid)(int pid); 291 void (*TBIAP)(int); 292 void (*TBIS)(vaddr_t); 293 int (*tlbUpdate)(vaddr_t, uint32_t); 294 void (*wbflush)(void); 295 } mips_locore_jumpvec_t; 296 297 void mips_set_wbflush(void (*)(void)); 298 void mips_wait_idle(void); 299 300 void stacktrace(void); 301 void logstacktrace(void); 302 303 struct locoresw { 304 uintptr_t lsw_cpu_switch_resume; 305 uintptr_t lsw_lwp_trampoline; 306 void (*lsw_cpu_idle)(void); 307 uintptr_t lsw_setfunc_trampoline; 308 }; 309 310 /* 311 * The "active" locore-fuction vector, and 312 */ 313 extern mips_locore_jumpvec_t mips_locore_jumpvec; 314 extern struct locoresw mips_locoresw; 315 316 #if defined(MIPS1) && !defined(MIPS3) && !defined(MIPS32) && !defined(MIPS64) 317 #define MachSetPID mips1_SetPID 318 #define MIPS_TBIAP() mips1_TBIAP(mips_num_tlb_entries) 319 #define MIPS_TBIS mips1_TBIS 320 #define MachTLBUpdate mips1_TLBUpdate 321 #define wbflush() mips1_wbflush() 322 #define lwp_trampoline mips1_lwp_trampoline 323 #define setfunc_trampoline mips1_setfunc_trampoline 324 #elif !defined(MIPS1) && defined(MIPS3) && !defined(MIPS32) && !defined(MIPS64) && !defined(MIPS3_5900) 325 #define MachSetPID mips3_SetPID 326 #define MIPS_TBIAP() mips3_TBIAP(mips_num_tlb_entries) 327 #define MIPS_TBIS mips3_TBIS 328 #define MachTLBUpdate mips3_TLBUpdate 329 #define MachTLBWriteIndexedVPS mips3_TLBWriteIndexedVPS 330 #define lwp_trampoline mips3_lwp_trampoline 331 #define setfunc_trampoline mips3_setfunc_trampoline 332 #define wbflush() mips3_wbflush() 333 #elif !defined(MIPS1) && !defined(MIPS3) && defined(MIPS32) && !defined(MIPS64) 334 #define MachSetPID mips32_SetPID 335 #define MIPS_TBIAP() mips32_TBIAP(mips_num_tlb_entries) 336 #define MIPS_TBIS mips32_TBIS 337 #define MachTLBUpdate mips32_TLBUpdate 338 #define MachTLBWriteIndexedVPS mips32_TLBWriteIndexedVPS 339 #define lwp_trampoline mips32_lwp_trampoline 340 #define setfunc_trampoline mips32_setfunc_trampoline 341 #define wbflush() mips32_wbflush() 342 #elif !defined(MIPS1) && !defined(MIPS3) && !defined(MIPS32) && defined(MIPS64) 343 /* all common with mips3 */ 344 #define MachSetPID mips64_SetPID 345 #define MIPS_TBIAP() mips64_TBIAP(mips_num_tlb_entries) 346 #define MIPS_TBIS mips64_TBIS 347 #define MachTLBUpdate mips64_TLBUpdate 348 #define MachTLBWriteIndexedVPS mips64_TLBWriteIndexedVPS 349 #define lwp_trampoline mips64_lwp_trampoline 350 #define setfunc_trampoline mips64_setfunc_trampoline 351 #define wbflush() mips64_wbflush() 352 #elif !defined(MIPS1) && defined(MIPS3) && !defined(MIPS32) && !defined(MIPS64) && defined(MIPS3_5900) 353 #define MachSetPID mips5900_SetPID 354 #define MIPS_TBIAP() mips5900_TBIAP(mips_num_tlb_entries) 355 #define MIPS_TBIS mips5900_TBIS 356 #define MachTLBUpdate mips5900_TLBUpdate 357 #define MachTLBWriteIndexedVPS mips5900_TLBWriteIndexedVPS 358 #define lwp_trampoline mips5900_lwp_trampoline 359 #define setfunc_trampoline mips5900_setfunc_trampoline 360 #define wbflush() mips5900_wbflush() 361 #else 362 #define MachSetPID (*(mips_locore_jumpvec.setTLBpid)) 363 #define MIPS_TBIAP() (*(mips_locore_jumpvec.TBIAP))(mips_num_tlb_entries) 364 #define MIPS_TBIS (*(mips_locore_jumpvec.TBIS)) 365 #define MachTLBUpdate (*(mips_locore_jumpvec.tlbUpdate)) 366 #define wbflush() (*(mips_locore_jumpvec.wbflush))() 367 #define lwp_trampoline mips_locoresw.lsw_lwp_trampoline 368 #define setfunc_trampoline mips_locoresw.lsw_setfunc_trampoline 369 #endif 370 371 #define CPU_IDLE mips_locoresw.lsw_cpu_idle 372 373 /* cpu_switch_resume is called inside locore.S */ 374 375 /* 376 * CPU identification, from PRID register. 377 */ 378 typedef int mips_prid_t; 379 380 #define MIPS_PRID_REV(x) (((x) >> 0) & 0x00ff) 381 #define MIPS_PRID_IMPL(x) (((x) >> 8) & 0x00ff) 382 383 /* pre-MIPS32/64 */ 384 #define MIPS_PRID_RSVD(x) (((x) >> 16) & 0xffff) 385 #define MIPS_PRID_REV_MIN(x) ((MIPS_PRID_REV(x) >> 0) & 0x0f) 386 #define MIPS_PRID_REV_MAJ(x) ((MIPS_PRID_REV(x) >> 4) & 0x0f) 387 388 /* MIPS32/64 */ 389 #define MIPS_PRID_CID(x) (((x) >> 16) & 0x00ff) /* Company ID */ 390 #define MIPS_PRID_CID_PREHISTORIC 0x00 /* Not MIPS32/64 */ 391 #define MIPS_PRID_CID_MTI 0x01 /* MIPS Technologies, Inc. */ 392 #define MIPS_PRID_CID_BROADCOM 0x02 /* Broadcom */ 393 #define MIPS_PRID_CID_ALCHEMY 0x03 /* Alchemy Semiconductor */ 394 #define MIPS_PRID_CID_SIBYTE 0x04 /* SiByte */ 395 #define MIPS_PRID_CID_SANDCRAFT 0x05 /* SandCraft */ 396 #define MIPS_PRID_CID_PHILIPS 0x06 /* Philips */ 397 #define MIPS_PRID_CID_TOSHIBA 0x07 /* Toshiba */ 398 #define MIPS_PRID_CID_LSI 0x08 /* LSI */ 399 /* 0x09 unannounced */ 400 /* 0x0a unannounced */ 401 #define MIPS_PRID_CID_LEXRA 0x0b /* Lexra */ 402 #define MIPS_PRID_CID_RMI 0x0c /* RMI / NetLogic */ 403 #define MIPS_PRID_COPTS(x) (((x) >> 24) & 0x00ff) /* Company Options */ 404 405 #ifdef _KERNEL 406 /* 407 * Global variables used to communicate CPU type, and parameters 408 * such as cache size, from locore to higher-level code (e.g., pmap). 409 */ 410 411 extern mips_prid_t cpu_id; 412 extern mips_prid_t fpu_id; 413 extern int mips_num_tlb_entries; 414 415 void mips_pagecopy(void *dst, void *src); 416 void mips_pagezero(void *dst); 417 418 #ifdef __HAVE_MIPS_MACHDEP_CACHE_CONFIG 419 void mips_machdep_cache_config(void); 420 #endif 421 422 /* 423 * trapframe argument passed to trap() 424 */ 425 426 #define TF_AST 0 427 #define TF_V0 1 428 #define TF_V1 2 429 #define TF_A0 3 430 #define TF_A1 4 431 #define TF_A2 5 432 #define TF_A3 6 433 #define TF_T0 7 434 #define TF_T1 8 435 #define TF_T2 9 436 #define TF_T3 10 437 438 #if defined(__mips_n32) || defined(__mips_n64) 439 #define TF_A4 11 440 #define TF_A5 12 441 #define TF_A6 13 442 #define TF_A7 14 443 #else 444 #define TF_T4 11 445 #define TF_T5 12 446 #define TF_T6 13 447 #define TF_T7 14 448 #endif /* __mips_n32 || __mips_n64 */ 449 450 #define TF_TA0 11 451 #define TF_TA1 12 452 #define TF_TA2 13 453 #define TF_TA3 14 454 455 #define TF_T8 15 456 #define TF_T9 16 457 458 #define TF_RA 17 459 #define TF_SR 18 460 #define TF_MULLO 19 461 #define TF_MULHI 20 462 #define TF_EPC 21 /* may be changed by trap() call */ 463 464 #define TF_NREGS 22 465 466 struct trapframe { 467 mips_reg_t tf_regs[TF_NREGS]; 468 uint32_t tf_ppl; /* previous priority level */ 469 mips_reg_t tf_pad; /* for 8 byte aligned */ 470 }; 471 472 /* 473 * Stack frame for kernel traps. four args passed in registers. 474 * A trapframe is pointed to by the 5th arg, and a dummy sixth argument 475 * is used to avoid alignment problems 476 */ 477 478 struct kernframe { 479 #if defined(__mips_o32) || defined(__mips_o64) 480 register_t cf_args[4 + 1]; 481 #if defined(__mips_o32) 482 register_t cf_pad; /* (for 8 word alignment) */ 483 #endif 484 #endif 485 #if defined(__mips_n32) || defined(__mips_n64) 486 register_t cf_pad[2]; /* for 16 byte alignment */ 487 #endif 488 register_t cf_sp; 489 register_t cf_ra; 490 struct trapframe cf_frame; 491 }; 492 #endif /* _KERNEL */ 493 #endif /* _MIPS_LOCORE_H */ 494
Indexes created Mon Sep 29 15:09:53 GMT 2025