locore.h revision 1.84
1 /* $NetBSD: locore.h,v 1.84 2011/03/03 18:44:58 matt Exp $ */ 2 3 /* 4 * This file should not be included by MI code!!! 5 */ 6 7 /* 8 * Copyright 1996 The Board of Trustees of The Leland Stanford 9 * Junior University. All Rights Reserved. 10 * 11 * Permission to use, copy, modify, and distribute this 12 * software and its documentation for any purpose and without 13 * fee is hereby granted, provided that the above copyright 14 * notice appear in all copies. Stanford University 15 * makes no representations about the suitability of this 16 * software for any purpose. It is provided "as is" without 17 * express or implied warranty. 18 */ 19 20 /* 21 * Jump table for MIPS CPU locore functions that are implemented 22 * differently on different generations, or instruction-level 23 * architecture (ISA) level, the Mips family. 24 * 25 * We currently provide support for MIPS I and MIPS III. 26 */ 27 28 #ifndef _MIPS_LOCORE_H 29 #define _MIPS_LOCORE_H 30 31 #ifndef _LKM 32 #include "opt_cputype.h" 33 #endif 34 35 #include <mips/mutex.h> 36 #include <mips/cpuregs.h> 37 #include <mips/reg.h> 38 39 struct tlbmask; 40 struct trapframe; 41 42 void trap(uint32_t, uint32_t, vaddr_t, vaddr_t, struct trapframe *); 43 void ast(void); 44 45 void mips_fpu_trap(vaddr_t, struct trapframe *); 46 void mips_fpu_intr(vaddr_t, struct trapframe *); 47 48 vaddr_t mips_emul_branch(struct trapframe *, vaddr_t, uint32_t, bool); 49 void mips_emul_inst(uint32_t, uint32_t, vaddr_t, struct trapframe *); 50 51 void mips_emul_fp(uint32_t, struct trapframe *, uint32_t); 52 void mips_emul_branchdelayslot(uint32_t, struct trapframe *, uint32_t); 53 54 void mips_emul_lwc0(uint32_t, struct trapframe *, uint32_t); 55 void mips_emul_swc0(uint32_t, struct trapframe *, uint32_t); 56 void mips_emul_special(uint32_t, struct trapframe *, uint32_t); 57 void mips_emul_special3(uint32_t, struct trapframe *, uint32_t); 58 59 void mips_emul_lwc1(uint32_t, struct trapframe *, uint32_t); 60 void mips_emul_swc1(uint32_t, struct trapframe *, uint32_t); 61 void mips_emul_ldc1(uint32_t, struct trapframe *, uint32_t); 62 void mips_emul_sdc1(uint32_t, struct trapframe *, uint32_t); 63 64 void mips_emul_lb(uint32_t, struct trapframe *, uint32_t); 65 void mips_emul_lbu(uint32_t, struct trapframe *, uint32_t); 66 void mips_emul_lh(uint32_t, struct trapframe *, uint32_t); 67 void mips_emul_lhu(uint32_t, struct trapframe *, uint32_t); 68 void mips_emul_lw(uint32_t, struct trapframe *, uint32_t); 69 void mips_emul_lwl(uint32_t, struct trapframe *, uint32_t); 70 void mips_emul_lwr(uint32_t, struct trapframe *, uint32_t); 71 #if defined(__mips_n32) || defined(__mips_n64) || defined(__mips_o64) 72 void mips_emul_lwu(uint32_t, struct trapframe *, uint32_t); 73 void mips_emul_ld(uint32_t, struct trapframe *, uint32_t); 74 void mips_emul_ldl(uint32_t, struct trapframe *, uint32_t); 75 void mips_emul_ldr(uint32_t, struct trapframe *, uint32_t); 76 #endif 77 void mips_emul_sb(uint32_t, struct trapframe *, uint32_t); 78 void mips_emul_sh(uint32_t, struct trapframe *, uint32_t); 79 void mips_emul_sw(uint32_t, struct trapframe *, uint32_t); 80 void mips_emul_swl(uint32_t, struct trapframe *, uint32_t); 81 void mips_emul_swr(uint32_t, struct trapframe *, uint32_t); 82 #if defined(__mips_n32) || defined(__mips_n64) || defined(__mips_o64) 83 void mips_emul_sd(uint32_t, struct trapframe *, uint32_t); 84 void mips_emul_sdl(uint32_t, struct trapframe *, uint32_t); 85 void mips_emul_sdr(uint32_t, struct trapframe *, uint32_t); 86 #endif 87 88 uint32_t mips_cp0_cause_read(void); 89 void mips_cp0_cause_write(uint32_t); 90 uint32_t mips_cp0_status_read(void); 91 void mips_cp0_status_write(uint32_t); 92 93 void softint_process(uint32_t); 94 void softint_fast_dispatch(struct lwp *, int); 95 96 /* 97 * Convert an address to an offset used in a MIPS jump instruction. The offset 98 * contains the low 28 bits (allowing a jump to anywhere within the same 256MB 99 * segment of address space) of the address but since mips instructions are 100 * always on a 4 byte boundary the low 2 bits are always zero so the 28 bits 101 * get shifted right by 2 bits leaving us with a 26 bit result. To make the 102 * offset, we shift left to clear the upper four bits and then right by 6. 103 */ 104 #define fixup_addr2offset(x) ((((uint32_t)(uintptr_t)(x)) << 4) >> 6) 105 typedef bool (*mips_fixup_callback_t)(int32_t, uint32_t [2]); 106 struct mips_jump_fixup_info { 107 uint32_t jfi_stub; 108 uint32_t jfi_real; 109 }; 110 111 void fixup_splcalls(void); /* splstubs.c */ 112 bool mips_fixup_exceptions(mips_fixup_callback_t); 113 bool mips_fixup_zero_relative(int32_t, uint32_t [2]); 114 void mips_fixup_stubs(uint32_t *, uint32_t *); 115 116 /* 117 * Define these stubs... 118 */ 119 void mips_cpu_switch_resume(struct lwp *); 120 void tlb_set_asid(uint32_t); 121 void tlb_invalidate_all(void); 122 void tlb_invalidate_globals(void); 123 void tlb_invalidate_asids(uint32_t, uint32_t); 124 void tlb_invalidate_addr(vaddr_t); 125 u_int tlb_record_asids(u_long *, uint32_t); 126 int tlb_update(vaddr_t, uint32_t); 127 void tlb_enter(size_t, vaddr_t, uint32_t); 128 void tlb_read_indexed(size_t, struct tlbmask *); 129 void tlb_write_indexed(size_t, const struct tlbmask *); 130 void wbflush(void); 131 132 #ifdef MIPS1 133 void mips1_tlb_invalidate_all(void); 134 135 uint32_t tx3900_cp0_config_read(void); 136 #endif 137 138 #if defined(MIPS3) || defined(MIPS4) 139 void mips3_tlb_invalidate_all(void); 140 void mips3_pagezero(void *dst); 141 #endif /* MIPS3 || MIPS4 */ 142 143 #ifdef MIPS32 144 void mips32_tlb_invalidate_all(void); 145 #endif 146 147 #ifdef MIPS64 148 void mips64_tlb_invalidate_all(void); 149 void mips64_pagezero(void *dst); 150 #endif 151 152 #if defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64) 153 uint32_t mips3_cp0_compare_read(void); 154 void mips3_cp0_compare_write(uint32_t); 155 156 uint32_t mips3_cp0_config_read(void); 157 void mips3_cp0_config_write(uint32_t); 158 #if defined(MIPS32) || defined(MIPS64) 159 uint32_t mipsNN_cp0_config1_read(void); 160 void mipsNN_cp0_config1_write(uint32_t); 161 uint32_t mipsNN_cp0_config2_read(void); 162 uint32_t mipsNN_cp0_config3_read(void); 163 #endif 164 165 uint32_t mips3_cp0_count_read(void); 166 void mips3_cp0_count_write(uint32_t); 167 168 uint32_t mips3_cp0_wired_read(void); 169 void mips3_cp0_wired_write(uint32_t); 170 void mips3_cp0_pg_mask_write(uint32_t); 171 172 #if defined(__GNUC__) && !defined(__mips_o32) 173 static inline uint64_t 174 mips3_ld(const volatile uint64_t *va) 175 { 176 uint64_t rv; 177 #if defined(__mips_o32) 178 uint32_t sr; 179 180 sr = mips_cp0_status_read(); 181 mips_cp0_status_write(sr & ~MIPS_SR_INT_IE); 182 183 __asm volatile( 184 ".set push \n\t" 185 ".set mips3 \n\t" 186 ".set noreorder \n\t" 187 ".set noat \n\t" 188 "ld %M0,0(%1) \n\t" 189 "dsll32 %L0,%M0,0 \n\t" 190 "dsra32 %M0,%M0,0 \n\t" /* high word */ 191 "dsra32 %L0,%L0,0 \n\t" /* low word */ 192 "ld %0,0(%1) \n\t" 193 ".set pop" 194 : "=d"(rv) 195 : "r"(va)); 196 197 mips_cp0_status_write(sr); 198 #elif defined(_LP64) 199 rv = *va; 200 #else 201 __asm volatile("ld %0,0(%1)" : "=d"(rv) : "r"(va)); 202 #endif 203 204 return rv; 205 } 206 static inline void 207 mips3_sd(volatile uint64_t *va, uint64_t v) 208 { 209 #if defined(__mips_o32) 210 uint32_t sr; 211 212 sr = mips_cp0_status_read(); 213 mips_cp0_status_write(sr & ~MIPS_SR_INT_IE); 214 215 __asm volatile( 216 ".set push \n\t" 217 ".set mips3 \n\t" 218 ".set noreorder \n\t" 219 ".set noat \n\t" 220 "dsll32 %M0,%M0,0 \n\t" 221 "dsll32 %L0,%L0,0 \n\t" 222 "dsrl32 %L0,%L0,0 \n\t" 223 "or %0,%L0,%M0 \n\t" 224 "sd %0,0(%1) \n\t" 225 ".set pop" 226 : "=d"(v) : "0"(v), "r"(va)); 227 228 mips_cp0_status_write(sr); 229 #elif defined(_LP64) 230 *va = v; 231 #else 232 __asm volatile("sd %0,0(%1)" :: "r"(v), "r"(va)); 233 #endif 234 } 235 #else 236 uint64_t mips3_ld(volatile uint64_t *va); 237 void mips3_sd(volatile uint64_t *, uint64_t); 238 #endif /* __GNUC__ */ 239 #endif /* MIPS3 || MIPS4 || MIPS32 || MIPS64 */ 240 241 #if defined(MIPS3) || defined(MIPS4) || defined(MIPS64) 242 static __inline uint32_t mips3_lw_a64(uint64_t addr) 243 __attribute__((__unused__)); 244 static __inline void mips3_sw_a64(uint64_t addr, uint32_t val) 245 __attribute__ ((__unused__)); 246 247 static __inline uint32_t 248 mips3_lw_a64(uint64_t addr) 249 { 250 uint32_t rv; 251 #if defined(__mips_o32) 252 uint32_t sr; 253 254 sr = mips_cp0_status_read(); 255 mips_cp0_status_write((sr & ~MIPS_SR_INT_IE) | MIPS3_SR_KX); 256 257 __asm volatile ( 258 ".set push \n\t" 259 ".set mips3 \n\t" 260 ".set noreorder \n\t" 261 ".set noat \n\t" 262 "dsll32 %M1,%M1,0 \n\t" 263 "dsll32 %L1,%L1,0 \n\t" 264 "dsrl32 %L1,%L1,0 \n\t" 265 "or %1,%M1,%L1 \n\t" 266 "lw %0, 0(%1) \n\t" 267 ".set pop" 268 : "=r"(rv), "=d"(addr) 269 : "1"(addr) 270 ); 271 272 mips_cp0_status_write(sr); 273 #elif defined(__mips_n32) 274 uint32_t sr = mips_cp0_status_read(); 275 mips_cp0_status_write((sr & ~MIPS_SR_INT_IE) | MIPS3_SR_KX); 276 __asm volatile("lw %0, 0(%1)" : "=r"(rv) : "d"(addr)); 277 mips_cp0_status_write(sr); 278 #elif defined(_LP64) 279 rv = *(const uint32_t *)addr; 280 #else 281 #error unknown ABI 282 #endif 283 return (rv); 284 } 285 286 static __inline void 287 mips3_sw_a64(uint64_t addr, uint32_t val) 288 { 289 #if defined(__mips_o32) 290 uint32_t sr; 291 292 sr = mips_cp0_status_read(); 293 mips_cp0_status_write((sr & ~MIPS_SR_INT_IE) | MIPS3_SR_KX); 294 295 __asm volatile ( 296 ".set push \n\t" 297 ".set mips3 \n\t" 298 ".set noreorder \n\t" 299 ".set noat \n\t" 300 "dsll32 %M0,%M0,0 \n\t" 301 "dsll32 %L0,%L0,0 \n\t" 302 "dsrl32 %L0,%L0,0 \n\t" 303 "or %0,%M0,%L0 \n\t" 304 "sw %1, 0(%0) \n\t" 305 ".set pop" 306 : "=d"(addr): "r"(val), "0"(addr) 307 ); 308 309 mips_cp0_status_write(sr); 310 #elif defined(__mips_n32) 311 uint32_t sr = mips_cp0_status_read(); 312 mips_cp0_status_write((sr & ~MIPS_SR_INT_IE) | MIPS3_SR_KX); 313 __asm volatile("sw %1, 0(%0)" :: "d"(addr), "r"(val)); 314 mips_cp0_status_write(sr); 315 #elif defined(_LP64) 316 *(uint32_t *)addr = val; 317 #else 318 #error unknown ABI 319 #endif 320 } 321 #endif /* MIPS3 || MIPS4 || MIPS64 */ 322 323 /* 324 * A vector with an entry for each mips-ISA-level dependent 325 * locore function, and macros which jump through it. 326 */ 327 typedef struct { 328 void (*ljv_cpu_switch_resume)(struct lwp *); 329 intptr_t ljv_lwp_trampoline; 330 intptr_t ljv_setfunc_trampoline; 331 void (*ljv_wbflush)(void); 332 void (*ljv_tlb_set_asid)(uint32_t pid); 333 void (*ljv_tlb_invalidate_asids)(uint32_t, uint32_t); 334 void (*ljv_tlb_invalidate_addr)(vaddr_t); 335 void (*ljv_tlb_invalidate_globals)(void); 336 void (*ljv_tlb_invalidate_all)(void); 337 u_int (*ljv_tlb_record_asids)(u_long *, uint32_t); 338 int (*ljv_tlb_update)(vaddr_t, uint32_t); 339 void (*ljv_tlb_enter)(size_t, vaddr_t, uint32_t); 340 void (*ljv_tlb_read_indexed)(size_t, struct tlbmask *); 341 void (*ljv_tlb_write_indexed)(size_t, const struct tlbmask *); 342 } mips_locore_jumpvec_t; 343 344 typedef struct { 345 u_int (*lav_atomic_cas_uint)(volatile u_int *, u_int, u_int); 346 u_long (*lav_atomic_cas_ulong)(volatile u_long *, u_long, u_long); 347 int (*lav_ucas_uint)(volatile u_int *, u_int, u_int, u_int *); 348 int (*lav_ucas_ulong)(volatile u_long *, u_long, u_long, u_long *); 349 void (*lav_mutex_enter)(kmutex_t *); 350 void (*lav_mutex_exit)(kmutex_t *); 351 void (*lav_mutex_spin_enter)(kmutex_t *); 352 void (*lav_mutex_spin_exit)(kmutex_t *); 353 } mips_locore_atomicvec_t; 354 355 void mips_set_wbflush(void (*)(void)); 356 void mips_wait_idle(void); 357 358 void stacktrace(void); 359 void logstacktrace(void); 360 361 struct cpu_info; 362 struct splsw; 363 364 struct locoresw { 365 void (*lsw_wbflush)(void); 366 void (*lsw_cpu_idle)(void); 367 int (*lsw_send_ipi)(struct cpu_info *, int); 368 void (*lsw_cpu_offline_md)(void); 369 void (*lsw_cpu_init)(struct cpu_info *); 370 int (*lsw_bus_error)(unsigned int); 371 }; 372 373 struct mips_vmfreelist { 374 paddr_t fl_start; 375 paddr_t fl_end; 376 int fl_freelist; 377 }; 378 379 /* 380 * The "active" locore-function vector, and 381 */ 382 extern const mips_locore_atomicvec_t mips_llsc_locore_atomicvec; 383 extern const mips_locore_atomicvec_t mips_ras_locore_atomicvec; 384 385 extern mips_locore_atomicvec_t mips_locore_atomicvec; 386 extern mips_locore_jumpvec_t mips_locore_jumpvec; 387 extern struct locoresw mips_locoresw; 388 389 struct splsw; 390 struct mips_vmfreelist; 391 struct phys_ram_seg; 392 393 void mips_vector_init(const struct splsw *, bool); 394 void mips_init_msgbuf(void); 395 void mips_init_lwp0_uarea(void); 396 void mips_page_physload(vaddr_t, vaddr_t, 397 const struct phys_ram_seg *, size_t, 398 const struct mips_vmfreelist *, size_t); 399 400 401 /* 402 * CPU identification, from PRID register. 403 */ 404 #define MIPS_PRID_REV(x) (((x) >> 0) & 0x00ff) 405 #define MIPS_PRID_IMPL(x) (((x) >> 8) & 0x00ff) 406 407 /* pre-MIPS32/64 */ 408 #define MIPS_PRID_RSVD(x) (((x) >> 16) & 0xffff) 409 #define MIPS_PRID_REV_MIN(x) ((MIPS_PRID_REV(x) >> 0) & 0x0f) 410 #define MIPS_PRID_REV_MAJ(x) ((MIPS_PRID_REV(x) >> 4) & 0x0f) 411 412 /* MIPS32/64 */ 413 #define MIPS_PRID_CID(x) (((x) >> 16) & 0x00ff) /* Company ID */ 414 #define MIPS_PRID_CID_PREHISTORIC 0x00 /* Not MIPS32/64 */ 415 #define MIPS_PRID_CID_MTI 0x01 /* MIPS Technologies, Inc. */ 416 #define MIPS_PRID_CID_BROADCOM 0x02 /* Broadcom */ 417 #define MIPS_PRID_CID_ALCHEMY 0x03 /* Alchemy Semiconductor */ 418 #define MIPS_PRID_CID_SIBYTE 0x04 /* SiByte */ 419 #define MIPS_PRID_CID_SANDCRAFT 0x05 /* SandCraft */ 420 #define MIPS_PRID_CID_PHILIPS 0x06 /* Philips */ 421 #define MIPS_PRID_CID_TOSHIBA 0x07 /* Toshiba */ 422 #define MIPS_PRID_CID_MICROSOFT 0x07 /* Microsoft also, sigh */ 423 #define MIPS_PRID_CID_LSI 0x08 /* LSI */ 424 /* 0x09 unannounced */ 425 /* 0x0a unannounced */ 426 #define MIPS_PRID_CID_LEXRA 0x0b /* Lexra */ 427 #define MIPS_PRID_CID_RMI 0x0c /* RMI / NetLogic */ 428 #define MIPS_PRID_COPTS(x) (((x) >> 24) & 0x00ff) /* Company Options */ 429 430 #ifdef _KERNEL 431 /* 432 * Global variables used to communicate CPU type, and parameters 433 * such as cache size, from locore to higher-level code (e.g., pmap). 434 */ 435 void mips_pagecopy(void *dst, void *src); 436 void mips_pagezero(void *dst); 437 438 #ifdef __HAVE_MIPS_MACHDEP_CACHE_CONFIG 439 void mips_machdep_cache_config(void); 440 #endif 441 442 /* 443 * trapframe argument passed to trap() 444 */ 445 446 #if 0 447 #define TF_AST 0 /* really zero */ 448 #define TF_V0 _R_V0 449 #define TF_V1 _R_V1 450 #define TF_A0 _R_A0 451 #define TF_A1 _R_A1 452 #define TF_A2 _R_A2 453 #define TF_A3 _R_A3 454 #define TF_T0 _R_T0 455 #define TF_T1 _R_T1 456 #define TF_T2 _R_T2 457 #define TF_T3 _R_T3 458 459 #if defined(__mips_n32) || defined(__mips_n64) 460 #define TF_A4 _R_A4 461 #define TF_A5 _R_A5 462 #define TF_A6 _R_A6 463 #define TF_A7 _R_A7 464 #else 465 #define TF_T4 _R_T4 466 #define TF_T5 _R_T5 467 #define TF_T6 _R_T6 468 #define TF_T7 _R_T7 469 #endif /* __mips_n32 || __mips_n64 */ 470 471 #define TF_TA0 _R_TA0 472 #define TF_TA1 _R_TA1 473 #define TF_TA2 _R_TA2 474 #define TF_TA3 _R_TA3 475 476 #define TF_T8 _R_T8 477 #define TF_T9 _R_T9 478 479 #define TF_RA _R_RA 480 #define TF_SR _R_SR 481 #define TF_MULLO _R_MULLO 482 #define TF_MULHI _R_MULLO 483 #define TF_EPC _R_PC /* may be changed by trap() call */ 484 485 #define TF_NREGS (sizeof(struct reg) / sizeof(mips_reg_t)) 486 #endif 487 488 struct trapframe { 489 struct reg tf_registers; 490 #define tf_regs tf_registers.r_regs 491 uint32_t tf_ppl; /* previous priority level */ 492 mips_reg_t tf_pad; /* for 8 byte aligned */ 493 }; 494 495 CTASSERT(sizeof(struct trapframe) % (4*sizeof(mips_reg_t)) == 0); 496 497 /* 498 * Stack frame for kernel traps. four args passed in registers. 499 * A trapframe is pointed to by the 5th arg, and a dummy sixth argument 500 * is used to avoid alignment problems 501 */ 502 503 struct kernframe { 504 #if defined(__mips_o32) || defined(__mips_o64) 505 register_t cf_args[4 + 1]; 506 #if defined(__mips_o32) 507 register_t cf_pad; /* (for 8 byte alignment) */ 508 #endif 509 #endif 510 #if defined(__mips_n32) || defined(__mips_n64) 511 register_t cf_pad[2]; /* for 16 byte alignment */ 512 #endif 513 register_t cf_sp; 514 register_t cf_ra; 515 struct trapframe cf_frame; 516 }; 517 518 CTASSERT(sizeof(struct kernframe) % (2*sizeof(mips_reg_t)) == 0); 519 520 /* 521 * PRocessor IDentity TABle 522 */ 523 524 struct pridtab { 525 int cpu_cid; 526 int cpu_pid; 527 int cpu_rev; /* -1 == wildcard */ 528 int cpu_copts; /* -1 == wildcard */ 529 int cpu_isa; /* -1 == probed (mips32/mips64) */ 530 int cpu_ntlb; /* -1 == unknown, 0 == probed */ 531 int cpu_flags; 532 u_int cpu_cp0flags; /* presence of some cp0 regs */ 533 u_int cpu_cidflags; /* company-specific flags */ 534 const char *cpu_name; 535 }; 536 537 /* 538 * bitfield defines for cpu_cp0flags 539 */ 540 #define MIPS_CP0FL_USE __BIT(0) /* use these flags */ 541 #define MIPS_CP0FL_ECC __BIT(1) 542 #define MIPS_CP0FL_CACHE_ERR __BIT(2) 543 #define MIPS_CP0FL_EIRR __BIT(3) 544 #define MIPS_CP0FL_EIMR __BIT(4) 545 #define MIPS_CP0FL_EBASE __BIT(5) 546 #define MIPS_CP0FL_CONFIG __BIT(6) 547 #define MIPS_CP0FL_CONFIG1 __BIT(7) 548 #define MIPS_CP0FL_CONFIG2 __BIT(8) 549 #define MIPS_CP0FL_CONFIG3 __BIT(9) 550 #define MIPS_CP0FL_CONFIG4 __BIT(10) 551 #define MIPS_CP0FL_CONFIG5 __BIT(11) 552 #define MIPS_CP0FL_CONFIG6 __BIT(12) 553 #define MIPS_CP0FL_CONFIG7 __BIT(13) 554 #define MIPS_CP0FL_USERLOCAL __BIT(14) 555 #define MIPS_CP0FL_HWRENA __BIT(15) 556 557 /* 558 * cpu_cidflags defines, by company 559 */ 560 /* 561 * RMI company-specific cpu_cidflags 562 */ 563 #define MIPS_CIDFL_RMI_TYPE __BITS(2,0) 564 # define CIDFL_RMI_TYPE_XLR 0 565 # define CIDFL_RMI_TYPE_XLS 1 566 # define CIDFL_RMI_TYPE_XLP 2 567 #define MIPS_CIDFL_RMI_THREADS_MASK __BITS(6,3) 568 # define MIPS_CIDFL_RMI_THREADS_SHIFT 3 569 #define MIPS_CIDFL_RMI_CORES_MASK __BITS(10,7) 570 # define MIPS_CIDFL_RMI_CORES_SHIFT 7 571 # define LOG2_1 0 572 # define LOG2_2 1 573 # define LOG2_4 2 574 # define LOG2_8 3 575 # define MIPS_CIDFL_RMI_CPUS(ncores, nthreads) \ 576 ((LOG2_ ## ncores << MIPS_CIDFL_RMI_CORES_SHIFT) \ 577 |(LOG2_ ## nthreads << MIPS_CIDFL_RMI_THREADS_SHIFT)) 578 # define MIPS_CIDFL_RMI_NTHREADS(cidfl) \ 579 (1 << (((cidfl) & MIPS_CIDFL_RMI_THREADS_MASK) \ 580 >> MIPS_CIDFL_RMI_THREADS_SHIFT)) 581 # define MIPS_CIDFL_RMI_NCORES(cidfl) \ 582 (1 << (((cidfl) & MIPS_CIDFL_RMI_CORES_MASK) \ 583 >> MIPS_CIDFL_RMI_CORES_SHIFT)) 584 #define MIPS_CIDFL_RMI_L2SZ_MASK __BITS(14,11) 585 # define MIPS_CIDFL_RMI_L2SZ_SHIFT 11 586 # define RMI_L2SZ_256KB 0 587 # define RMI_L2SZ_512KB 1 588 # define RMI_L2SZ_1MB 2 589 # define RMI_L2SZ_2MB 3 590 # define RMI_L2SZ_4MB 4 591 # define MIPS_CIDFL_RMI_L2(l2sz) \ 592 (RMI_L2SZ_ ## l2sz << MIPS_CIDFL_RMI_L2SZ_SHIFT) 593 # define MIPS_CIDFL_RMI_L2SZ(cidfl) \ 594 ((256*1024) << (((cidfl) & MIPS_CIDFL_RMI_L2SZ_MASK) \ 595 >> MIPS_CIDFL_RMI_L2SZ_SHIFT)) 596 597 #endif /* _KERNEL */ 598 #endif /* _MIPS_LOCORE_H */ 599
Indexes created Tue Sep 30 17:09:57 GMT 2025