locore.h revision 1.86
1 /* $NetBSD: locore.h,v 1.86 2011/04/06 05:43:11 matt Exp $ */ 2 3 /* 4 * This file should not be included by MI code!!! 5 */ 6 7 /* 8 * Copyright 1996 The Board of Trustees of The Leland Stanford 9 * Junior University. All Rights Reserved. 10 * 11 * Permission to use, copy, modify, and distribute this 12 * software and its documentation for any purpose and without 13 * fee is hereby granted, provided that the above copyright 14 * notice appear in all copies. Stanford University 15 * makes no representations about the suitability of this 16 * software for any purpose. It is provided "as is" without 17 * express or implied warranty. 18 */ 19 20 /* 21 * Jump table for MIPS CPU locore functions that are implemented 22 * differently on different generations, or instruction-level 23 * architecture (ISA) level, the Mips family. 24 * 25 * We currently provide support for MIPS I and MIPS III. 26 */ 27 28 #ifndef _MIPS_LOCORE_H 29 #define _MIPS_LOCORE_H 30 31 #ifndef _LKM 32 #include "opt_cputype.h" 33 #endif 34 35 #include <mips/mutex.h> 36 #include <mips/cpuregs.h> 37 #include <mips/reg.h> 38 39 struct tlbmask; 40 struct trapframe; 41 42 void trap(uint32_t, uint32_t, vaddr_t, vaddr_t, struct trapframe *); 43 void ast(void); 44 45 void mips_fpu_trap(vaddr_t, struct trapframe *); 46 void mips_fpu_intr(vaddr_t, struct trapframe *); 47 48 vaddr_t mips_emul_branch(struct trapframe *, vaddr_t, uint32_t, bool); 49 void mips_emul_inst(uint32_t, uint32_t, vaddr_t, struct trapframe *); 50 51 void mips_emul_fp(uint32_t, struct trapframe *, uint32_t); 52 void mips_emul_branchdelayslot(uint32_t, struct trapframe *, uint32_t); 53 54 void mips_emul_lwc0(uint32_t, struct trapframe *, uint32_t); 55 void mips_emul_swc0(uint32_t, struct trapframe *, uint32_t); 56 void mips_emul_special(uint32_t, struct trapframe *, uint32_t); 57 void mips_emul_special3(uint32_t, struct trapframe *, uint32_t); 58 59 void mips_emul_lwc1(uint32_t, struct trapframe *, uint32_t); 60 void mips_emul_swc1(uint32_t, struct trapframe *, uint32_t); 61 void mips_emul_ldc1(uint32_t, struct trapframe *, uint32_t); 62 void mips_emul_sdc1(uint32_t, struct trapframe *, uint32_t); 63 64 void mips_emul_lb(uint32_t, struct trapframe *, uint32_t); 65 void mips_emul_lbu(uint32_t, struct trapframe *, uint32_t); 66 void mips_emul_lh(uint32_t, struct trapframe *, uint32_t); 67 void mips_emul_lhu(uint32_t, struct trapframe *, uint32_t); 68 void mips_emul_lw(uint32_t, struct trapframe *, uint32_t); 69 void mips_emul_lwl(uint32_t, struct trapframe *, uint32_t); 70 void mips_emul_lwr(uint32_t, struct trapframe *, uint32_t); 71 #if defined(__mips_n32) || defined(__mips_n64) || defined(__mips_o64) 72 void mips_emul_lwu(uint32_t, struct trapframe *, uint32_t); 73 void mips_emul_ld(uint32_t, struct trapframe *, uint32_t); 74 void mips_emul_ldl(uint32_t, struct trapframe *, uint32_t); 75 void mips_emul_ldr(uint32_t, struct trapframe *, uint32_t); 76 #endif 77 void mips_emul_sb(uint32_t, struct trapframe *, uint32_t); 78 void mips_emul_sh(uint32_t, struct trapframe *, uint32_t); 79 void mips_emul_sw(uint32_t, struct trapframe *, uint32_t); 80 void mips_emul_swl(uint32_t, struct trapframe *, uint32_t); 81 void mips_emul_swr(uint32_t, struct trapframe *, uint32_t); 82 #if defined(__mips_n32) || defined(__mips_n64) || defined(__mips_o64) 83 void mips_emul_sd(uint32_t, struct trapframe *, uint32_t); 84 void mips_emul_sdl(uint32_t, struct trapframe *, uint32_t); 85 void mips_emul_sdr(uint32_t, struct trapframe *, uint32_t); 86 #endif 87 88 uint32_t mips_cp0_cause_read(void); 89 void mips_cp0_cause_write(uint32_t); 90 uint32_t mips_cp0_status_read(void); 91 void mips_cp0_status_write(uint32_t); 92 93 void softint_process(uint32_t); 94 void softint_fast_dispatch(struct lwp *, int); 95 96 /* 97 * Convert an address to an offset used in a MIPS jump instruction. The offset 98 * contains the low 28 bits (allowing a jump to anywhere within the same 256MB 99 * segment of address space) of the address but since mips instructions are 100 * always on a 4 byte boundary the low 2 bits are always zero so the 28 bits 101 * get shifted right by 2 bits leaving us with a 26 bit result. To make the 102 * offset, we shift left to clear the upper four bits and then right by 6. 103 */ 104 #define fixup_addr2offset(x) ((((uint32_t)(uintptr_t)(x)) << 4) >> 6) 105 typedef bool (*mips_fixup_callback_t)(int32_t, uint32_t [2]); 106 struct mips_jump_fixup_info { 107 uint32_t jfi_stub; 108 uint32_t jfi_real; 109 }; 110 111 void fixup_splcalls(void); /* splstubs.c */ 112 bool mips_fixup_exceptions(mips_fixup_callback_t); 113 bool mips_fixup_zero_relative(int32_t, uint32_t [2]); 114 void mips_fixup_stubs(uint32_t *, uint32_t *); 115 116 /* 117 * Define these stubs... 118 */ 119 void mips_cpu_switch_resume(struct lwp *); 120 void tlb_set_asid(uint32_t); 121 void tlb_invalidate_all(void); 122 void tlb_invalidate_globals(void); 123 void tlb_invalidate_asids(uint32_t, uint32_t); 124 void tlb_invalidate_addr(vaddr_t); 125 u_int tlb_record_asids(u_long *, uint32_t); 126 int tlb_update(vaddr_t, uint32_t); 127 void tlb_enter(size_t, vaddr_t, uint32_t); 128 void tlb_read_indexed(size_t, struct tlbmask *); 129 void tlb_write_indexed(size_t, const struct tlbmask *); 130 void wbflush(void); 131 132 #ifdef MIPS1 133 void mips1_tlb_invalidate_all(void); 134 135 uint32_t tx3900_cp0_config_read(void); 136 #endif 137 138 #if (MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0 139 uint32_t mips3_cp0_compare_read(void); 140 void mips3_cp0_compare_write(uint32_t); 141 142 uint32_t mips3_cp0_config_read(void); 143 void mips3_cp0_config_write(uint32_t); 144 145 #if (MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0 146 uint32_t mipsNN_cp0_config1_read(void); 147 void mipsNN_cp0_config1_write(uint32_t); 148 uint32_t mipsNN_cp0_config2_read(void); 149 uint32_t mipsNN_cp0_config3_read(void); 150 151 #if (MIPS32R2 + MIPS64R2) > 0 152 void mipsNN_cp0_hwrena_write(uint32_t); 153 void mipsNN_cp0_userlocal_write(void *); 154 #endif 155 #endif 156 157 uint32_t mips3_cp0_count_read(void); 158 void mips3_cp0_count_write(uint32_t); 159 160 uint32_t mips3_cp0_wired_read(void); 161 void mips3_cp0_wired_write(uint32_t); 162 void mips3_cp0_pg_mask_write(uint32_t); 163 164 #if defined(__GNUC__) && !defined(__mips_o32) 165 static inline uint64_t 166 mips3_ld(const volatile uint64_t *va) 167 { 168 uint64_t rv; 169 #if defined(__mips_o32) 170 uint32_t sr; 171 172 sr = mips_cp0_status_read(); 173 mips_cp0_status_write(sr & ~MIPS_SR_INT_IE); 174 175 __asm volatile( 176 ".set push \n\t" 177 ".set mips3 \n\t" 178 ".set noreorder \n\t" 179 ".set noat \n\t" 180 "ld %M0,0(%1) \n\t" 181 "dsll32 %L0,%M0,0 \n\t" 182 "dsra32 %M0,%M0,0 \n\t" /* high word */ 183 "dsra32 %L0,%L0,0 \n\t" /* low word */ 184 "ld %0,0(%1) \n\t" 185 ".set pop" 186 : "=d"(rv) 187 : "r"(va)); 188 189 mips_cp0_status_write(sr); 190 #elif defined(_LP64) 191 rv = *va; 192 #else 193 __asm volatile("ld %0,0(%1)" : "=d"(rv) : "r"(va)); 194 #endif 195 196 return rv; 197 } 198 static inline void 199 mips3_sd(volatile uint64_t *va, uint64_t v) 200 { 201 #if defined(__mips_o32) 202 uint32_t sr; 203 204 sr = mips_cp0_status_read(); 205 mips_cp0_status_write(sr & ~MIPS_SR_INT_IE); 206 207 __asm volatile( 208 ".set push \n\t" 209 ".set mips3 \n\t" 210 ".set noreorder \n\t" 211 ".set noat \n\t" 212 "dsll32 %M0,%M0,0 \n\t" 213 "dsll32 %L0,%L0,0 \n\t" 214 "dsrl32 %L0,%L0,0 \n\t" 215 "or %0,%L0,%M0 \n\t" 216 "sd %0,0(%1) \n\t" 217 ".set pop" 218 : "=d"(v) : "0"(v), "r"(va)); 219 220 mips_cp0_status_write(sr); 221 #elif defined(_LP64) 222 *va = v; 223 #else 224 __asm volatile("sd %0,0(%1)" :: "r"(v), "r"(va)); 225 #endif 226 } 227 #else 228 uint64_t mips3_ld(volatile uint64_t *va); 229 void mips3_sd(volatile uint64_t *, uint64_t); 230 #endif /* __GNUC__ */ 231 #endif /* (MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0 */ 232 233 #if (MIPS3 + MIPS4 + MIPS64 + MIPS64R2) > 0 234 static __inline uint32_t mips3_lw_a64(uint64_t addr) __unused; 235 static __inline void mips3_sw_a64(uint64_t addr, uint32_t val) __unused; 236 237 static __inline uint32_t 238 mips3_lw_a64(uint64_t addr) 239 { 240 uint32_t rv; 241 #if defined(__mips_o32) 242 uint32_t sr; 243 244 sr = mips_cp0_status_read(); 245 mips_cp0_status_write((sr & ~MIPS_SR_INT_IE) | MIPS3_SR_KX); 246 247 __asm volatile ( 248 ".set push \n\t" 249 ".set mips3 \n\t" 250 ".set noreorder \n\t" 251 ".set noat \n\t" 252 "dsll32 %M1,%M1,0 \n\t" 253 "dsll32 %L1,%L1,0 \n\t" 254 "dsrl32 %L1,%L1,0 \n\t" 255 "or %1,%M1,%L1 \n\t" 256 "lw %0, 0(%1) \n\t" 257 ".set pop" 258 : "=r"(rv), "=d"(addr) 259 : "1"(addr) 260 ); 261 262 mips_cp0_status_write(sr); 263 #elif defined(__mips_n32) 264 uint32_t sr = mips_cp0_status_read(); 265 mips_cp0_status_write((sr & ~MIPS_SR_INT_IE) | MIPS3_SR_KX); 266 __asm volatile("lw %0, 0(%1)" : "=r"(rv) : "d"(addr)); 267 mips_cp0_status_write(sr); 268 #elif defined(_LP64) 269 rv = *(const uint32_t *)addr; 270 #else 271 #error unknown ABI 272 #endif 273 return (rv); 274 } 275 276 static __inline void 277 mips3_sw_a64(uint64_t addr, uint32_t val) 278 { 279 #if defined(__mips_o32) 280 uint32_t sr; 281 282 sr = mips_cp0_status_read(); 283 mips_cp0_status_write((sr & ~MIPS_SR_INT_IE) | MIPS3_SR_KX); 284 285 __asm volatile ( 286 ".set push \n\t" 287 ".set mips3 \n\t" 288 ".set noreorder \n\t" 289 ".set noat \n\t" 290 "dsll32 %M0,%M0,0 \n\t" 291 "dsll32 %L0,%L0,0 \n\t" 292 "dsrl32 %L0,%L0,0 \n\t" 293 "or %0,%M0,%L0 \n\t" 294 "sw %1, 0(%0) \n\t" 295 ".set pop" 296 : "=d"(addr): "r"(val), "0"(addr) 297 ); 298 299 mips_cp0_status_write(sr); 300 #elif defined(__mips_n32) 301 uint32_t sr = mips_cp0_status_read(); 302 mips_cp0_status_write((sr & ~MIPS_SR_INT_IE) | MIPS3_SR_KX); 303 __asm volatile("sw %1, 0(%0)" :: "d"(addr), "r"(val)); 304 mips_cp0_status_write(sr); 305 #elif defined(_LP64) 306 *(uint32_t *)addr = val; 307 #else 308 #error unknown ABI 309 #endif 310 } 311 #endif /* (MIPS3 + MIPS4 + MIPS64 + MIPS64R2) > 0 */ 312 313 /* 314 * A vector with an entry for each mips-ISA-level dependent 315 * locore function, and macros which jump through it. 316 */ 317 typedef struct { 318 void (*ljv_cpu_switch_resume)(struct lwp *); 319 intptr_t ljv_lwp_trampoline; 320 intptr_t ljv_setfunc_trampoline; 321 void (*ljv_wbflush)(void); 322 void (*ljv_tlb_set_asid)(uint32_t pid); 323 void (*ljv_tlb_invalidate_asids)(uint32_t, uint32_t); 324 void (*ljv_tlb_invalidate_addr)(vaddr_t); 325 void (*ljv_tlb_invalidate_globals)(void); 326 void (*ljv_tlb_invalidate_all)(void); 327 u_int (*ljv_tlb_record_asids)(u_long *, uint32_t); 328 int (*ljv_tlb_update)(vaddr_t, uint32_t); 329 void (*ljv_tlb_enter)(size_t, vaddr_t, uint32_t); 330 void (*ljv_tlb_read_indexed)(size_t, struct tlbmask *); 331 void (*ljv_tlb_write_indexed)(size_t, const struct tlbmask *); 332 } mips_locore_jumpvec_t; 333 334 typedef struct { 335 u_int (*lav_atomic_cas_uint)(volatile u_int *, u_int, u_int); 336 u_long (*lav_atomic_cas_ulong)(volatile u_long *, u_long, u_long); 337 int (*lav_ucas_uint)(volatile u_int *, u_int, u_int, u_int *); 338 int (*lav_ucas_ulong)(volatile u_long *, u_long, u_long, u_long *); 339 void (*lav_mutex_enter)(kmutex_t *); 340 void (*lav_mutex_exit)(kmutex_t *); 341 void (*lav_mutex_spin_enter)(kmutex_t *); 342 void (*lav_mutex_spin_exit)(kmutex_t *); 343 } mips_locore_atomicvec_t; 344 345 void mips_set_wbflush(void (*)(void)); 346 void mips_wait_idle(void); 347 348 void stacktrace(void); 349 void logstacktrace(void); 350 351 struct cpu_info; 352 struct splsw; 353 354 struct locoresw { 355 void (*lsw_wbflush)(void); 356 void (*lsw_cpu_idle)(void); 357 int (*lsw_send_ipi)(struct cpu_info *, int); 358 void (*lsw_cpu_offline_md)(void); 359 void (*lsw_cpu_init)(struct cpu_info *); 360 int (*lsw_bus_error)(unsigned int); 361 }; 362 363 struct mips_vmfreelist { 364 paddr_t fl_start; 365 paddr_t fl_end; 366 int fl_freelist; 367 }; 368 369 /* 370 * The "active" locore-function vector, and 371 */ 372 extern const mips_locore_atomicvec_t mips_llsc_locore_atomicvec; 373 extern const mips_locore_atomicvec_t mips_ras_locore_atomicvec; 374 375 extern mips_locore_atomicvec_t mips_locore_atomicvec; 376 extern mips_locore_jumpvec_t mips_locore_jumpvec; 377 extern struct locoresw mips_locoresw; 378 379 struct splsw; 380 struct mips_vmfreelist; 381 struct phys_ram_seg; 382 383 void mips_vector_init(const struct splsw *, bool); 384 void mips_init_msgbuf(void); 385 void mips_init_lwp0_uarea(void); 386 void mips_page_physload(vaddr_t, vaddr_t, 387 const struct phys_ram_seg *, size_t, 388 const struct mips_vmfreelist *, size_t); 389 390 391 /* 392 * CPU identification, from PRID register. 393 */ 394 #define MIPS_PRID_REV(x) (((x) >> 0) & 0x00ff) 395 #define MIPS_PRID_IMPL(x) (((x) >> 8) & 0x00ff) 396 397 /* pre-MIPS32/64 */ 398 #define MIPS_PRID_RSVD(x) (((x) >> 16) & 0xffff) 399 #define MIPS_PRID_REV_MIN(x) ((MIPS_PRID_REV(x) >> 0) & 0x0f) 400 #define MIPS_PRID_REV_MAJ(x) ((MIPS_PRID_REV(x) >> 4) & 0x0f) 401 402 /* MIPS32/64 */ 403 #define MIPS_PRID_CID(x) (((x) >> 16) & 0x00ff) /* Company ID */ 404 #define MIPS_PRID_CID_PREHISTORIC 0x00 /* Not MIPS32/64 */ 405 #define MIPS_PRID_CID_MTI 0x01 /* MIPS Technologies, Inc. */ 406 #define MIPS_PRID_CID_BROADCOM 0x02 /* Broadcom */ 407 #define MIPS_PRID_CID_ALCHEMY 0x03 /* Alchemy Semiconductor */ 408 #define MIPS_PRID_CID_SIBYTE 0x04 /* SiByte */ 409 #define MIPS_PRID_CID_SANDCRAFT 0x05 /* SandCraft */ 410 #define MIPS_PRID_CID_PHILIPS 0x06 /* Philips */ 411 #define MIPS_PRID_CID_TOSHIBA 0x07 /* Toshiba */ 412 #define MIPS_PRID_CID_MICROSOFT 0x07 /* Microsoft also, sigh */ 413 #define MIPS_PRID_CID_LSI 0x08 /* LSI */ 414 /* 0x09 unannounced */ 415 /* 0x0a unannounced */ 416 #define MIPS_PRID_CID_LEXRA 0x0b /* Lexra */ 417 #define MIPS_PRID_CID_RMI 0x0c /* RMI / NetLogic */ 418 #define MIPS_PRID_COPTS(x) (((x) >> 24) & 0x00ff) /* Company Options */ 419 420 #ifdef _KERNEL 421 /* 422 * Global variables used to communicate CPU type, and parameters 423 * such as cache size, from locore to higher-level code (e.g., pmap). 424 */ 425 void mips_pagecopy(void *dst, void *src); 426 void mips_pagezero(void *dst); 427 428 #ifdef __HAVE_MIPS_MACHDEP_CACHE_CONFIG 429 void mips_machdep_cache_config(void); 430 #endif 431 432 /* 433 * trapframe argument passed to trap() 434 */ 435 436 #if 0 437 #define TF_AST 0 /* really zero */ 438 #define TF_V0 _R_V0 439 #define TF_V1 _R_V1 440 #define TF_A0 _R_A0 441 #define TF_A1 _R_A1 442 #define TF_A2 _R_A2 443 #define TF_A3 _R_A3 444 #define TF_T0 _R_T0 445 #define TF_T1 _R_T1 446 #define TF_T2 _R_T2 447 #define TF_T3 _R_T3 448 449 #if defined(__mips_n32) || defined(__mips_n64) 450 #define TF_A4 _R_A4 451 #define TF_A5 _R_A5 452 #define TF_A6 _R_A6 453 #define TF_A7 _R_A7 454 #else 455 #define TF_T4 _R_T4 456 #define TF_T5 _R_T5 457 #define TF_T6 _R_T6 458 #define TF_T7 _R_T7 459 #endif /* __mips_n32 || __mips_n64 */ 460 461 #define TF_TA0 _R_TA0 462 #define TF_TA1 _R_TA1 463 #define TF_TA2 _R_TA2 464 #define TF_TA3 _R_TA3 465 466 #define TF_T8 _R_T8 467 #define TF_T9 _R_T9 468 469 #define TF_RA _R_RA 470 #define TF_SR _R_SR 471 #define TF_MULLO _R_MULLO 472 #define TF_MULHI _R_MULLO 473 #define TF_EPC _R_PC /* may be changed by trap() call */ 474 475 #define TF_NREGS (sizeof(struct reg) / sizeof(mips_reg_t)) 476 #endif 477 478 struct trapframe { 479 struct reg tf_registers; 480 #define tf_regs tf_registers.r_regs 481 uint32_t tf_ppl; /* previous priority level */ 482 mips_reg_t tf_pad; /* for 8 byte aligned */ 483 }; 484 485 CTASSERT(sizeof(struct trapframe) % (4*sizeof(mips_reg_t)) == 0); 486 487 /* 488 * Stack frame for kernel traps. four args passed in registers. 489 * A trapframe is pointed to by the 5th arg, and a dummy sixth argument 490 * is used to avoid alignment problems 491 */ 492 493 struct kernframe { 494 #if defined(__mips_o32) || defined(__mips_o64) 495 register_t cf_args[4 + 1]; 496 #if defined(__mips_o32) 497 register_t cf_pad; /* (for 8 byte alignment) */ 498 #endif 499 #endif 500 #if defined(__mips_n32) || defined(__mips_n64) 501 register_t cf_pad[2]; /* for 16 byte alignment */ 502 #endif 503 register_t cf_sp; 504 register_t cf_ra; 505 struct trapframe cf_frame; 506 }; 507 508 CTASSERT(sizeof(struct kernframe) % (2*sizeof(mips_reg_t)) == 0); 509 510 /* 511 * PRocessor IDentity TABle 512 */ 513 514 struct pridtab { 515 int cpu_cid; 516 int cpu_pid; 517 int cpu_rev; /* -1 == wildcard */ 518 int cpu_copts; /* -1 == wildcard */ 519 int cpu_isa; /* -1 == probed (mips32/mips64) */ 520 int cpu_ntlb; /* -1 == unknown, 0 == probed */ 521 int cpu_flags; 522 u_int cpu_cp0flags; /* presence of some cp0 regs */ 523 u_int cpu_cidflags; /* company-specific flags */ 524 const char *cpu_name; 525 }; 526 527 /* 528 * bitfield defines for cpu_cp0flags 529 */ 530 #define MIPS_CP0FL_USE __BIT(0) /* use these flags */ 531 #define MIPS_CP0FL_ECC __BIT(1) 532 #define MIPS_CP0FL_CACHE_ERR __BIT(2) 533 #define MIPS_CP0FL_EIRR __BIT(3) 534 #define MIPS_CP0FL_EIMR __BIT(4) 535 #define MIPS_CP0FL_EBASE __BIT(5) 536 #define MIPS_CP0FL_CONFIG __BIT(6) 537 #define MIPS_CP0FL_CONFIG1 __BIT(7) 538 #define MIPS_CP0FL_CONFIG2 __BIT(8) 539 #define MIPS_CP0FL_CONFIG3 __BIT(9) 540 #define MIPS_CP0FL_CONFIG4 __BIT(10) 541 #define MIPS_CP0FL_CONFIG5 __BIT(11) 542 #define MIPS_CP0FL_CONFIG6 __BIT(12) 543 #define MIPS_CP0FL_CONFIG7 __BIT(13) 544 #define MIPS_CP0FL_USERLOCAL __BIT(14) 545 #define MIPS_CP0FL_HWRENA __BIT(15) 546 547 /* 548 * cpu_cidflags defines, by company 549 */ 550 /* 551 * RMI company-specific cpu_cidflags 552 */ 553 #define MIPS_CIDFL_RMI_TYPE __BITS(2,0) 554 # define CIDFL_RMI_TYPE_XLR 0 555 # define CIDFL_RMI_TYPE_XLS 1 556 # define CIDFL_RMI_TYPE_XLP 2 557 #define MIPS_CIDFL_RMI_THREADS_MASK __BITS(6,3) 558 # define MIPS_CIDFL_RMI_THREADS_SHIFT 3 559 #define MIPS_CIDFL_RMI_CORES_MASK __BITS(10,7) 560 # define MIPS_CIDFL_RMI_CORES_SHIFT 7 561 # define LOG2_1 0 562 # define LOG2_2 1 563 # define LOG2_4 2 564 # define LOG2_8 3 565 # define MIPS_CIDFL_RMI_CPUS(ncores, nthreads) \ 566 ((LOG2_ ## ncores << MIPS_CIDFL_RMI_CORES_SHIFT) \ 567 |(LOG2_ ## nthreads << MIPS_CIDFL_RMI_THREADS_SHIFT)) 568 # define MIPS_CIDFL_RMI_NTHREADS(cidfl) \ 569 (1 << (((cidfl) & MIPS_CIDFL_RMI_THREADS_MASK) \ 570 >> MIPS_CIDFL_RMI_THREADS_SHIFT)) 571 # define MIPS_CIDFL_RMI_NCORES(cidfl) \ 572 (1 << (((cidfl) & MIPS_CIDFL_RMI_CORES_MASK) \ 573 >> MIPS_CIDFL_RMI_CORES_SHIFT)) 574 #define MIPS_CIDFL_RMI_L2SZ_MASK __BITS(14,11) 575 # define MIPS_CIDFL_RMI_L2SZ_SHIFT 11 576 # define RMI_L2SZ_256KB 0 577 # define RMI_L2SZ_512KB 1 578 # define RMI_L2SZ_1MB 2 579 # define RMI_L2SZ_2MB 3 580 # define RMI_L2SZ_4MB 4 581 # define MIPS_CIDFL_RMI_L2(l2sz) \ 582 (RMI_L2SZ_ ## l2sz << MIPS_CIDFL_RMI_L2SZ_SHIFT) 583 # define MIPS_CIDFL_RMI_L2SZ(cidfl) \ 584 ((256*1024) << (((cidfl) & MIPS_CIDFL_RMI_L2SZ_MASK) \ 585 >> MIPS_CIDFL_RMI_L2SZ_SHIFT)) 586 587 #endif /* _KERNEL */ 588 #endif /* _MIPS_LOCORE_H */ 589
Indexes created Mon Sep 29 21:09:56 GMT 2025