locore.h revision 1.88
1 /* $NetBSD: locore.h,v 1.88 2011/04/14 05:08:22 cliff Exp $ */ 2 3 /* 4 * This file should not be included by MI code!!! 5 */ 6 7 /* 8 * Copyright 1996 The Board of Trustees of The Leland Stanford 9 * Junior University. All Rights Reserved. 10 * 11 * Permission to use, copy, modify, and distribute this 12 * software and its documentation for any purpose and without 13 * fee is hereby granted, provided that the above copyright 14 * notice appear in all copies. Stanford University 15 * makes no representations about the suitability of this 16 * software for any purpose. It is provided "as is" without 17 * express or implied warranty. 18 */ 19 20 /* 21 * Jump table for MIPS CPU locore functions that are implemented 22 * differently on different generations, or instruction-level 23 * architecture (ISA) level, the Mips family. 24 * 25 * We currently provide support for MIPS I and MIPS III. 26 */ 27 28 #ifndef _MIPS_LOCORE_H 29 #define _MIPS_LOCORE_H 30 31 #ifndef _LKM 32 #include "opt_cputype.h" 33 #endif 34 35 #include <mips/mutex.h> 36 #include <mips/cpuregs.h> 37 #include <mips/reg.h> 38 39 struct tlbmask; 40 struct trapframe; 41 42 void trap(uint32_t, uint32_t, vaddr_t, vaddr_t, struct trapframe *); 43 void ast(void); 44 45 void mips_fpu_trap(vaddr_t, struct trapframe *); 46 void mips_fpu_intr(vaddr_t, struct trapframe *); 47 48 vaddr_t mips_emul_branch(struct trapframe *, vaddr_t, uint32_t, bool); 49 void mips_emul_inst(uint32_t, uint32_t, vaddr_t, struct trapframe *); 50 51 void mips_emul_fp(uint32_t, struct trapframe *, uint32_t); 52 void mips_emul_branchdelayslot(uint32_t, struct trapframe *, uint32_t); 53 54 void mips_emul_lwc0(uint32_t, struct trapframe *, uint32_t); 55 void mips_emul_swc0(uint32_t, struct trapframe *, uint32_t); 56 void mips_emul_special(uint32_t, struct trapframe *, uint32_t); 57 void mips_emul_special3(uint32_t, struct trapframe *, uint32_t); 58 59 void mips_emul_lwc1(uint32_t, struct trapframe *, uint32_t); 60 void mips_emul_swc1(uint32_t, struct trapframe *, uint32_t); 61 void mips_emul_ldc1(uint32_t, struct trapframe *, uint32_t); 62 void mips_emul_sdc1(uint32_t, struct trapframe *, uint32_t); 63 64 void mips_emul_lb(uint32_t, struct trapframe *, uint32_t); 65 void mips_emul_lbu(uint32_t, struct trapframe *, uint32_t); 66 void mips_emul_lh(uint32_t, struct trapframe *, uint32_t); 67 void mips_emul_lhu(uint32_t, struct trapframe *, uint32_t); 68 void mips_emul_lw(uint32_t, struct trapframe *, uint32_t); 69 void mips_emul_lwl(uint32_t, struct trapframe *, uint32_t); 70 void mips_emul_lwr(uint32_t, struct trapframe *, uint32_t); 71 #if defined(__mips_n32) || defined(__mips_n64) || defined(__mips_o64) 72 void mips_emul_lwu(uint32_t, struct trapframe *, uint32_t); 73 void mips_emul_ld(uint32_t, struct trapframe *, uint32_t); 74 void mips_emul_ldl(uint32_t, struct trapframe *, uint32_t); 75 void mips_emul_ldr(uint32_t, struct trapframe *, uint32_t); 76 #endif 77 void mips_emul_sb(uint32_t, struct trapframe *, uint32_t); 78 void mips_emul_sh(uint32_t, struct trapframe *, uint32_t); 79 void mips_emul_sw(uint32_t, struct trapframe *, uint32_t); 80 void mips_emul_swl(uint32_t, struct trapframe *, uint32_t); 81 void mips_emul_swr(uint32_t, struct trapframe *, uint32_t); 82 #if defined(__mips_n32) || defined(__mips_n64) || defined(__mips_o64) 83 void mips_emul_sd(uint32_t, struct trapframe *, uint32_t); 84 void mips_emul_sdl(uint32_t, struct trapframe *, uint32_t); 85 void mips_emul_sdr(uint32_t, struct trapframe *, uint32_t); 86 #endif 87 88 uint32_t mips_cp0_cause_read(void); 89 void mips_cp0_cause_write(uint32_t); 90 uint32_t mips_cp0_status_read(void); 91 void mips_cp0_status_write(uint32_t); 92 93 void softint_process(uint32_t); 94 void softint_fast_dispatch(struct lwp *, int); 95 96 /* 97 * Convert an address to an offset used in a MIPS jump instruction. The offset 98 * contains the low 28 bits (allowing a jump to anywhere within the same 256MB 99 * segment of address space) of the address but since mips instructions are 100 * always on a 4 byte boundary the low 2 bits are always zero so the 28 bits 101 * get shifted right by 2 bits leaving us with a 26 bit result. To make the 102 * offset, we shift left to clear the upper four bits and then right by 6. 103 */ 104 #define fixup_addr2offset(x) ((((uint32_t)(uintptr_t)(x)) << 4) >> 6) 105 typedef bool (*mips_fixup_callback_t)(int32_t, uint32_t [2]); 106 struct mips_jump_fixup_info { 107 uint32_t jfi_stub; 108 uint32_t jfi_real; 109 }; 110 111 void fixup_splcalls(void); /* splstubs.c */ 112 bool mips_fixup_exceptions(mips_fixup_callback_t); 113 bool mips_fixup_zero_relative(int32_t, uint32_t [2]); 114 void mips_fixup_stubs(uint32_t *, uint32_t *); 115 116 /* 117 * Define these stubs... 118 */ 119 void mips_cpu_switch_resume(struct lwp *); 120 void tlb_set_asid(uint32_t); 121 void tlb_invalidate_all(void); 122 void tlb_invalidate_globals(void); 123 void tlb_invalidate_asids(uint32_t, uint32_t); 124 void tlb_invalidate_addr(vaddr_t); 125 u_int tlb_record_asids(u_long *, uint32_t); 126 int tlb_update(vaddr_t, uint32_t); 127 void tlb_enter(size_t, vaddr_t, uint32_t); 128 void tlb_read_indexed(size_t, struct tlbmask *); 129 void tlb_write_indexed(size_t, const struct tlbmask *); 130 void wbflush(void); 131 132 #ifdef MIPS1 133 void mips1_tlb_invalidate_all(void); 134 135 uint32_t tx3900_cp0_config_read(void); 136 #endif 137 138 #if (MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0 139 uint32_t mips3_cp0_compare_read(void); 140 void mips3_cp0_compare_write(uint32_t); 141 142 uint32_t mips3_cp0_config_read(void); 143 void mips3_cp0_config_write(uint32_t); 144 145 #if (MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0 146 uint32_t mipsNN_cp0_config1_read(void); 147 void mipsNN_cp0_config1_write(uint32_t); 148 uint32_t mipsNN_cp0_config2_read(void); 149 uint32_t mipsNN_cp0_config3_read(void); 150 151 uintptr_t mipsNN_cp0_watchlo_read(u_int); 152 void mipsNN_cp0_watchlo_write(u_int, uintptr_t); 153 uint32_t mipsNN_cp0_watchhi_read(u_int); 154 void mipsNN_cp0_watchhi_write(u_int, uint32_t); 155 156 #if (MIPS32R2 + MIPS64R2) > 0 157 void mipsNN_cp0_hwrena_write(uint32_t); 158 void mipsNN_cp0_userlocal_write(void *); 159 #endif 160 #endif 161 162 uint32_t mips3_cp0_count_read(void); 163 void mips3_cp0_count_write(uint32_t); 164 165 uint32_t mips3_cp0_wired_read(void); 166 void mips3_cp0_wired_write(uint32_t); 167 void mips3_cp0_pg_mask_write(uint32_t); 168 169 #if defined(__GNUC__) && !defined(__mips_o32) 170 static inline uint64_t 171 mips3_ld(const volatile uint64_t *va) 172 { 173 uint64_t rv; 174 #if defined(__mips_o32) 175 uint32_t sr; 176 177 sr = mips_cp0_status_read(); 178 mips_cp0_status_write(sr & ~MIPS_SR_INT_IE); 179 180 __asm volatile( 181 ".set push \n\t" 182 ".set mips3 \n\t" 183 ".set noreorder \n\t" 184 ".set noat \n\t" 185 "ld %M0,0(%1) \n\t" 186 "dsll32 %L0,%M0,0 \n\t" 187 "dsra32 %M0,%M0,0 \n\t" /* high word */ 188 "dsra32 %L0,%L0,0 \n\t" /* low word */ 189 "ld %0,0(%1) \n\t" 190 ".set pop" 191 : "=d"(rv) 192 : "r"(va)); 193 194 mips_cp0_status_write(sr); 195 #elif defined(_LP64) 196 rv = *va; 197 #else 198 __asm volatile("ld %0,0(%1)" : "=d"(rv) : "r"(va)); 199 #endif 200 201 return rv; 202 } 203 static inline void 204 mips3_sd(volatile uint64_t *va, uint64_t v) 205 { 206 #if defined(__mips_o32) 207 uint32_t sr; 208 209 sr = mips_cp0_status_read(); 210 mips_cp0_status_write(sr & ~MIPS_SR_INT_IE); 211 212 __asm volatile( 213 ".set push \n\t" 214 ".set mips3 \n\t" 215 ".set noreorder \n\t" 216 ".set noat \n\t" 217 "dsll32 %M0,%M0,0 \n\t" 218 "dsll32 %L0,%L0,0 \n\t" 219 "dsrl32 %L0,%L0,0 \n\t" 220 "or %0,%L0,%M0 \n\t" 221 "sd %0,0(%1) \n\t" 222 ".set pop" 223 : "=d"(v) : "0"(v), "r"(va)); 224 225 mips_cp0_status_write(sr); 226 #elif defined(_LP64) 227 *va = v; 228 #else 229 __asm volatile("sd %0,0(%1)" :: "r"(v), "r"(va)); 230 #endif 231 } 232 #else 233 uint64_t mips3_ld(volatile uint64_t *va); 234 void mips3_sd(volatile uint64_t *, uint64_t); 235 #endif /* __GNUC__ */ 236 #endif /* (MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0 */ 237 238 #if (MIPS3 + MIPS4 + MIPS64 + MIPS64R2) > 0 239 static __inline uint32_t mips3_lw_a64(uint64_t addr) __unused; 240 static __inline void mips3_sw_a64(uint64_t addr, uint32_t val) __unused; 241 242 static __inline uint32_t 243 mips3_lw_a64(uint64_t addr) 244 { 245 uint32_t rv; 246 #if defined(__mips_o32) 247 uint32_t sr; 248 249 sr = mips_cp0_status_read(); 250 mips_cp0_status_write((sr & ~MIPS_SR_INT_IE) | MIPS3_SR_KX); 251 252 __asm volatile ( 253 ".set push \n\t" 254 ".set mips3 \n\t" 255 ".set noreorder \n\t" 256 ".set noat \n\t" 257 "dsll32 %M1,%M1,0 \n\t" 258 "dsll32 %L1,%L1,0 \n\t" 259 "dsrl32 %L1,%L1,0 \n\t" 260 "or %1,%M1,%L1 \n\t" 261 "lw %0, 0(%1) \n\t" 262 ".set pop" 263 : "=r"(rv), "=d"(addr) 264 : "1"(addr) 265 ); 266 267 mips_cp0_status_write(sr); 268 #elif defined(__mips_n32) 269 uint32_t sr = mips_cp0_status_read(); 270 mips_cp0_status_write((sr & ~MIPS_SR_INT_IE) | MIPS3_SR_KX); 271 __asm volatile("lw %0, 0(%1)" : "=r"(rv) : "d"(addr)); 272 mips_cp0_status_write(sr); 273 #elif defined(_LP64) 274 rv = *(const uint32_t *)addr; 275 #else 276 #error unknown ABI 277 #endif 278 return (rv); 279 } 280 281 static __inline void 282 mips3_sw_a64(uint64_t addr, uint32_t val) 283 { 284 #if defined(__mips_o32) 285 uint32_t sr; 286 287 sr = mips_cp0_status_read(); 288 mips_cp0_status_write((sr & ~MIPS_SR_INT_IE) | MIPS3_SR_KX); 289 290 __asm volatile ( 291 ".set push \n\t" 292 ".set mips3 \n\t" 293 ".set noreorder \n\t" 294 ".set noat \n\t" 295 "dsll32 %M0,%M0,0 \n\t" 296 "dsll32 %L0,%L0,0 \n\t" 297 "dsrl32 %L0,%L0,0 \n\t" 298 "or %0,%M0,%L0 \n\t" 299 "sw %1, 0(%0) \n\t" 300 ".set pop" 301 : "=d"(addr): "r"(val), "0"(addr) 302 ); 303 304 mips_cp0_status_write(sr); 305 #elif defined(__mips_n32) 306 uint32_t sr = mips_cp0_status_read(); 307 mips_cp0_status_write((sr & ~MIPS_SR_INT_IE) | MIPS3_SR_KX); 308 __asm volatile("sw %1, 0(%0)" :: "d"(addr), "r"(val)); 309 mips_cp0_status_write(sr); 310 #elif defined(_LP64) 311 *(uint32_t *)addr = val; 312 #else 313 #error unknown ABI 314 #endif 315 } 316 #endif /* (MIPS3 + MIPS4 + MIPS64 + MIPS64R2) > 0 */ 317 318 /* 319 * A vector with an entry for each mips-ISA-level dependent 320 * locore function, and macros which jump through it. 321 */ 322 typedef struct { 323 void (*ljv_cpu_switch_resume)(struct lwp *); 324 intptr_t ljv_lwp_trampoline; 325 intptr_t ljv_setfunc_trampoline; 326 void (*ljv_wbflush)(void); 327 void (*ljv_tlb_set_asid)(uint32_t pid); 328 void (*ljv_tlb_invalidate_asids)(uint32_t, uint32_t); 329 void (*ljv_tlb_invalidate_addr)(vaddr_t); 330 void (*ljv_tlb_invalidate_globals)(void); 331 void (*ljv_tlb_invalidate_all)(void); 332 u_int (*ljv_tlb_record_asids)(u_long *, uint32_t); 333 int (*ljv_tlb_update)(vaddr_t, uint32_t); 334 void (*ljv_tlb_enter)(size_t, vaddr_t, uint32_t); 335 void (*ljv_tlb_read_indexed)(size_t, struct tlbmask *); 336 void (*ljv_tlb_write_indexed)(size_t, const struct tlbmask *); 337 } mips_locore_jumpvec_t; 338 339 typedef struct { 340 u_int (*lav_atomic_cas_uint)(volatile u_int *, u_int, u_int); 341 u_long (*lav_atomic_cas_ulong)(volatile u_long *, u_long, u_long); 342 int (*lav_ucas_uint)(volatile u_int *, u_int, u_int, u_int *); 343 int (*lav_ucas_ulong)(volatile u_long *, u_long, u_long, u_long *); 344 void (*lav_mutex_enter)(kmutex_t *); 345 void (*lav_mutex_exit)(kmutex_t *); 346 void (*lav_mutex_spin_enter)(kmutex_t *); 347 void (*lav_mutex_spin_exit)(kmutex_t *); 348 } mips_locore_atomicvec_t; 349 350 void mips_set_wbflush(void (*)(void)); 351 void mips_wait_idle(void); 352 353 void stacktrace(void); 354 void logstacktrace(void); 355 356 struct cpu_info; 357 struct splsw; 358 359 struct locoresw { 360 void (*lsw_wbflush)(void); 361 void (*lsw_cpu_idle)(void); 362 int (*lsw_send_ipi)(struct cpu_info *, int); 363 void (*lsw_cpu_offline_md)(void); 364 void (*lsw_cpu_init)(struct cpu_info *); 365 void (*lsw_cpu_run)(struct cpu_info *); 366 int (*lsw_bus_error)(unsigned int); 367 }; 368 369 struct mips_vmfreelist { 370 paddr_t fl_start; 371 paddr_t fl_end; 372 int fl_freelist; 373 }; 374 375 /* 376 * The "active" locore-function vector, and 377 */ 378 extern const mips_locore_atomicvec_t mips_llsc_locore_atomicvec; 379 extern const mips_locore_atomicvec_t mips_ras_locore_atomicvec; 380 381 extern mips_locore_atomicvec_t mips_locore_atomicvec; 382 extern mips_locore_jumpvec_t mips_locore_jumpvec; 383 extern struct locoresw mips_locoresw; 384 385 struct splsw; 386 struct mips_vmfreelist; 387 struct phys_ram_seg; 388 389 void mips_vector_init(const struct splsw *, bool); 390 void mips_init_msgbuf(void); 391 void mips_init_lwp0_uarea(void); 392 void mips_page_physload(vaddr_t, vaddr_t, 393 const struct phys_ram_seg *, size_t, 394 const struct mips_vmfreelist *, size_t); 395 396 397 /* 398 * CPU identification, from PRID register. 399 */ 400 #define MIPS_PRID_REV(x) (((x) >> 0) & 0x00ff) 401 #define MIPS_PRID_IMPL(x) (((x) >> 8) & 0x00ff) 402 403 /* pre-MIPS32/64 */ 404 #define MIPS_PRID_RSVD(x) (((x) >> 16) & 0xffff) 405 #define MIPS_PRID_REV_MIN(x) ((MIPS_PRID_REV(x) >> 0) & 0x0f) 406 #define MIPS_PRID_REV_MAJ(x) ((MIPS_PRID_REV(x) >> 4) & 0x0f) 407 408 /* MIPS32/64 */ 409 #define MIPS_PRID_CID(x) (((x) >> 16) & 0x00ff) /* Company ID */ 410 #define MIPS_PRID_CID_PREHISTORIC 0x00 /* Not MIPS32/64 */ 411 #define MIPS_PRID_CID_MTI 0x01 /* MIPS Technologies, Inc. */ 412 #define MIPS_PRID_CID_BROADCOM 0x02 /* Broadcom */ 413 #define MIPS_PRID_CID_ALCHEMY 0x03 /* Alchemy Semiconductor */ 414 #define MIPS_PRID_CID_SIBYTE 0x04 /* SiByte */ 415 #define MIPS_PRID_CID_SANDCRAFT 0x05 /* SandCraft */ 416 #define MIPS_PRID_CID_PHILIPS 0x06 /* Philips */ 417 #define MIPS_PRID_CID_TOSHIBA 0x07 /* Toshiba */ 418 #define MIPS_PRID_CID_MICROSOFT 0x07 /* Microsoft also, sigh */ 419 #define MIPS_PRID_CID_LSI 0x08 /* LSI */ 420 /* 0x09 unannounced */ 421 /* 0x0a unannounced */ 422 #define MIPS_PRID_CID_LEXRA 0x0b /* Lexra */ 423 #define MIPS_PRID_CID_RMI 0x0c /* RMI / NetLogic */ 424 #define MIPS_PRID_COPTS(x) (((x) >> 24) & 0x00ff) /* Company Options */ 425 426 #ifdef _KERNEL 427 /* 428 * Global variables used to communicate CPU type, and parameters 429 * such as cache size, from locore to higher-level code (e.g., pmap). 430 */ 431 void mips_pagecopy(void *dst, void *src); 432 void mips_pagezero(void *dst); 433 434 #ifdef __HAVE_MIPS_MACHDEP_CACHE_CONFIG 435 void mips_machdep_cache_config(void); 436 #endif 437 438 /* 439 * trapframe argument passed to trap() 440 */ 441 442 #if 0 443 #define TF_AST 0 /* really zero */ 444 #define TF_V0 _R_V0 445 #define TF_V1 _R_V1 446 #define TF_A0 _R_A0 447 #define TF_A1 _R_A1 448 #define TF_A2 _R_A2 449 #define TF_A3 _R_A3 450 #define TF_T0 _R_T0 451 #define TF_T1 _R_T1 452 #define TF_T2 _R_T2 453 #define TF_T3 _R_T3 454 455 #if defined(__mips_n32) || defined(__mips_n64) 456 #define TF_A4 _R_A4 457 #define TF_A5 _R_A5 458 #define TF_A6 _R_A6 459 #define TF_A7 _R_A7 460 #else 461 #define TF_T4 _R_T4 462 #define TF_T5 _R_T5 463 #define TF_T6 _R_T6 464 #define TF_T7 _R_T7 465 #endif /* __mips_n32 || __mips_n64 */ 466 467 #define TF_TA0 _R_TA0 468 #define TF_TA1 _R_TA1 469 #define TF_TA2 _R_TA2 470 #define TF_TA3 _R_TA3 471 472 #define TF_T8 _R_T8 473 #define TF_T9 _R_T9 474 475 #define TF_RA _R_RA 476 #define TF_SR _R_SR 477 #define TF_MULLO _R_MULLO 478 #define TF_MULHI _R_MULLO 479 #define TF_EPC _R_PC /* may be changed by trap() call */ 480 481 #define TF_NREGS (sizeof(struct reg) / sizeof(mips_reg_t)) 482 #endif 483 484 struct trapframe { 485 struct reg tf_registers; 486 #define tf_regs tf_registers.r_regs 487 uint32_t tf_ppl; /* previous priority level */ 488 mips_reg_t tf_pad; /* for 8 byte aligned */ 489 }; 490 491 CTASSERT(sizeof(struct trapframe) % (4*sizeof(mips_reg_t)) == 0); 492 493 /* 494 * Stack frame for kernel traps. four args passed in registers. 495 * A trapframe is pointed to by the 5th arg, and a dummy sixth argument 496 * is used to avoid alignment problems 497 */ 498 499 struct kernframe { 500 #if defined(__mips_o32) || defined(__mips_o64) 501 register_t cf_args[4 + 1]; 502 #if defined(__mips_o32) 503 register_t cf_pad; /* (for 8 byte alignment) */ 504 #endif 505 #endif 506 #if defined(__mips_n32) || defined(__mips_n64) 507 register_t cf_pad[2]; /* for 16 byte alignment */ 508 #endif 509 register_t cf_sp; 510 register_t cf_ra; 511 struct trapframe cf_frame; 512 }; 513 514 CTASSERT(sizeof(struct kernframe) % (2*sizeof(mips_reg_t)) == 0); 515 516 /* 517 * PRocessor IDentity TABle 518 */ 519 520 struct pridtab { 521 int cpu_cid; 522 int cpu_pid; 523 int cpu_rev; /* -1 == wildcard */ 524 int cpu_copts; /* -1 == wildcard */ 525 int cpu_isa; /* -1 == probed (mips32/mips64) */ 526 int cpu_ntlb; /* -1 == unknown, 0 == probed */ 527 int cpu_flags; 528 u_int cpu_cp0flags; /* presence of some cp0 regs */ 529 u_int cpu_cidflags; /* company-specific flags */ 530 const char *cpu_name; 531 }; 532 533 /* 534 * bitfield defines for cpu_cp0flags 535 */ 536 #define MIPS_CP0FL_USE __BIT(0) /* use these flags */ 537 #define MIPS_CP0FL_ECC __BIT(1) 538 #define MIPS_CP0FL_CACHE_ERR __BIT(2) 539 #define MIPS_CP0FL_EIRR __BIT(3) 540 #define MIPS_CP0FL_EIMR __BIT(4) 541 #define MIPS_CP0FL_EBASE __BIT(5) 542 #define MIPS_CP0FL_CONFIG __BIT(6) 543 #define MIPS_CP0FL_CONFIG1 __BIT(7) 544 #define MIPS_CP0FL_CONFIG2 __BIT(8) 545 #define MIPS_CP0FL_CONFIG3 __BIT(9) 546 #define MIPS_CP0FL_CONFIG4 __BIT(10) 547 #define MIPS_CP0FL_CONFIG5 __BIT(11) 548 #define MIPS_CP0FL_CONFIG6 __BIT(12) 549 #define MIPS_CP0FL_CONFIG7 __BIT(13) 550 #define MIPS_CP0FL_USERLOCAL __BIT(14) 551 #define MIPS_CP0FL_HWRENA __BIT(15) 552 553 /* 554 * cpu_cidflags defines, by company 555 */ 556 /* 557 * RMI company-specific cpu_cidflags 558 */ 559 #define MIPS_CIDFL_RMI_TYPE __BITS(2,0) 560 # define CIDFL_RMI_TYPE_XLR 0 561 # define CIDFL_RMI_TYPE_XLS 1 562 # define CIDFL_RMI_TYPE_XLP 2 563 #define MIPS_CIDFL_RMI_THREADS_MASK __BITS(6,3) 564 # define MIPS_CIDFL_RMI_THREADS_SHIFT 3 565 #define MIPS_CIDFL_RMI_CORES_MASK __BITS(10,7) 566 # define MIPS_CIDFL_RMI_CORES_SHIFT 7 567 # define LOG2_1 0 568 # define LOG2_2 1 569 # define LOG2_4 2 570 # define LOG2_8 3 571 # define MIPS_CIDFL_RMI_CPUS(ncores, nthreads) \ 572 ((LOG2_ ## ncores << MIPS_CIDFL_RMI_CORES_SHIFT) \ 573 |(LOG2_ ## nthreads << MIPS_CIDFL_RMI_THREADS_SHIFT)) 574 # define MIPS_CIDFL_RMI_NTHREADS(cidfl) \ 575 (1 << (((cidfl) & MIPS_CIDFL_RMI_THREADS_MASK) \ 576 >> MIPS_CIDFL_RMI_THREADS_SHIFT)) 577 # define MIPS_CIDFL_RMI_NCORES(cidfl) \ 578 (1 << (((cidfl) & MIPS_CIDFL_RMI_CORES_MASK) \ 579 >> MIPS_CIDFL_RMI_CORES_SHIFT)) 580 #define MIPS_CIDFL_RMI_L2SZ_MASK __BITS(14,11) 581 # define MIPS_CIDFL_RMI_L2SZ_SHIFT 11 582 # define RMI_L2SZ_256KB 0 583 # define RMI_L2SZ_512KB 1 584 # define RMI_L2SZ_1MB 2 585 # define RMI_L2SZ_2MB 3 586 # define RMI_L2SZ_4MB 4 587 # define MIPS_CIDFL_RMI_L2(l2sz) \ 588 (RMI_L2SZ_ ## l2sz << MIPS_CIDFL_RMI_L2SZ_SHIFT) 589 # define MIPS_CIDFL_RMI_L2SZ(cidfl) \ 590 ((256*1024) << (((cidfl) & MIPS_CIDFL_RMI_L2SZ_MASK) \ 591 >> MIPS_CIDFL_RMI_L2SZ_SHIFT)) 592 593 #endif /* _KERNEL */ 594 #endif /* _MIPS_LOCORE_H */ 595
Indexes created Tue Sep 30 06:09:59 GMT 2025