locore.h revision 1.9
1 /* $NetBSD: locore.h,v 1.9 1997/06/19 06:31:14 mhitch Exp $ */ 2 3 /* 4 * Copyright 1996 The Board of Trustees of The Leland Stanford 5 * Junior University. All Rights Reserved. 6 * 7 * Permission to use, copy, modify, and distribute this 8 * software and its documentation for any purpose and without 9 * fee is hereby granted, provided that the above copyright 10 * notice appear in all copies. Stanford University 11 * makes no representations about the suitability of this 12 * software for any purpose. It is provided "as is" without 13 * express or implied warranty. 14 */ 15 16 /* 17 * Jump table for MIPS cpu locore functions that are implemented 18 * differently on different generations, or instruction-level 19 * archtecture (ISA) level, the Mips family. 20 * The following functions must be provided for each mips ISA level: 21 * 22 * 23 * MachConfigCache 24 * MachFlushCache 25 * MachFlushDCache 26 * MachFlushICache 27 * MachForceCacheUpdate 28 * MachSetPID 29 * MachTLBFlush 30 * MachTLBFlushAddr __P() 31 * MachTLBUpdate (u_int, (pt_entry_t?) u_int); 32 * MachTLBWriteIndexed 33 * wbflush 34 * proc_trampoline() 35 * switch_exit() 36 * cpu_switch_resume() 37 * 38 * We currently provide support for: 39 * 40 * r2000 and r3000 (mips ISA-I) 41 * r4000 and r4400 in 32-bit mode (mips ISA-III?) 42 */ 43 44 #ifndef _MIPS_LOCORE_H 45 #define _MIPS_LOCORE_H 46 47 /* 48 * locore service routine for exeception vectors. Used outside locore 49 * only to print them by name in stack tracebacks 50 */ 51 52 extern void mips1_ConfigCache __P((void)); 53 extern void mips1_FlushCache __P((void)); 54 extern void mips1_FlushDCache __P((vm_offset_t addr, vm_offset_t len)); 55 extern void mips1_FlushICache __P((vm_offset_t addr, vm_offset_t len)); 56 extern void mips1_ForceCacheUpdate __P((void)); 57 extern void mips1_SetPID __P((int pid)); 58 extern void mips1_TLBFlush __P((void)); 59 extern void mips1_TLBFlushAddr __P( /* XXX Really pte highpart ? */ 60 (vm_offset_t addr)); 61 extern int mips1_TLBUpdate __P((u_int, /*pt_entry_t*/ u_int)); 62 extern void mips1_TLBWriteIndexed __P((u_int index, u_int high, 63 u_int low)); 64 extern void mips1_wbflush __P((void)); 65 extern void mips1_proc_trampoline __P((void)); 66 extern void mips1_switch_exit __P((struct proc *)); 67 extern void mips1_cpu_switch_resume __P((void)); 68 69 extern void mips3_ConfigCache __P((void)); 70 extern void mips3_FlushCache __P((void)); 71 extern void mips3_FlushDCache __P((vm_offset_t addr, vm_offset_t len)); 72 extern void mips3_FlushICache __P((vm_offset_t addr, vm_offset_t len)); 73 extern void mips3_ForceCacheUpdate __P((void)); 74 extern void mips3_HitFlushDCache __P((vm_offset_t, int)); 75 extern void mips3_SetPID __P((int pid)); 76 extern void mips3_TLBFlush __P((void)); 77 extern void mips3_TLBFlushAddr __P( /* XXX Really pte highpart ? */ 78 (vm_offset_t addr)); 79 extern int mips3_TLBUpdate __P((u_int, /*pt_entry_t*/ u_int)); 80 extern void mips3_TLBWriteIndexedVPS __P((u_int index, void *tlb)); 81 extern void mips3_TLBWriteIndexed __P((u_int index, u_int high, 82 u_int lo0, u_int lo1)); 83 extern void mips3_wbflush __P((void)); 84 extern void mips3_proc_trampoline __P((void)); 85 extern void mips3_switch_exit __P((struct proc *)); 86 extern void mips3_cpu_switch_resume __P((void)); 87 88 extern void MachHitFlushDCache __P((caddr_t, int)); 89 extern void mips3_SetWIRED __P((int)); 90 91 92 /* 93 * A vector with an entry for each mips-ISA-level dependent 94 * locore function, and macros which jump through it. 95 * XXX the macro names are chosen to be compatible with the old 96 * Sprite coding-convention names used in 4.4bsd/pmax. 97 */ 98 typedef struct { 99 void (*configCache) __P((void)); 100 void (*flushCache) __P((void)); 101 void (*flushDCache) __P((vm_offset_t addr, vm_offset_t len)); 102 void (*flushICache) __P((vm_offset_t addr, vm_offset_t len)); 103 void (*forceCacheUpdate) __P((void)); 104 void (*setTLBpid) __P((int pid)); 105 void (*tlbFlush) __P((void)); 106 void (*tlbFlushAddr) __P((vm_offset_t)); /* XXX Really pte highpart ? */ 107 int (*tlbUpdate) __P((u_int highreg, u_int lowreg)); 108 #ifdef MIPS3 109 void (*tlbWriteIndexed) __P((u_int, u_int, u_int, u_int)); 110 #else 111 void (*tlbWriteIndexed) __P((u_int, u_int, u_int)); 112 #endif 113 void (*wbflush) __P((void)); 114 void (*proc_trampoline) __P((void)); 115 void (*mips_switch_exit) __P((struct proc *)); 116 void (*cpu_switch_resume) __P((void)); 117 } mips_locore_jumpvec_t; 118 119 120 /* 121 * The "active" locore-fuction vector, and 122 123 */ 124 extern mips_locore_jumpvec_t mips_locore_jumpvec; 125 extern mips_locore_jumpvec_t r2000_locore_vec; 126 extern mips_locore_jumpvec_t r4000_locore_vec; 127 128 #define MachConfigCache (*(mips_locore_jumpvec.configCache)) 129 #define MachFlushCache (*(mips_locore_jumpvec.flushCache)) 130 #define MachFlushDCache (*(mips_locore_jumpvec.flushDCache)) 131 #define MachFlushICache (*(mips_locore_jumpvec.flushICache)) 132 #define MachForceCacheUpdate (*(mips_locore_jumpvec.forceCacheUpdate)) 133 #define MachSetPID (*(mips_locore_jumpvec.setTLBpid)) 134 #define MachTLBFlush (*(mips_locore_jumpvec.tlbFlush)) 135 #define MachTLBFlushAddr (*(mips_locore_jumpvec.tlbFlushAddr)) 136 #define MachTLBUpdate (*(mips_locore_jumpvec.tlbUpdate)) 137 #define MachTLBWriteIndexed (*(mips_locore_jumpvec.tlbWriteIndexed)) 138 #define wbflush (*(mips_locore_jumpvec.wbflush)) 139 #define proc_trampoline (mips_locore_jumpvec.proc_trampoline) 140 #define switch_exit (*(mips_locore_jumpvec.mips_switch_exit)) 141 /* cpu_switch_resume not called directly */ 142 143 144 /* 145 * CPU identification, from PRID register. 146 */ 147 union cpuprid { 148 int cpuprid; 149 struct { 150 #if BYTE_ORDER == BIG_ENDIAN 151 u_int pad1:16; /* reserved */ 152 u_int cp_imp:8; /* implementation identifier */ 153 u_int cp_majrev:4; /* major revision identifier */ 154 u_int cp_minrev:4; /* minor revision identifier */ 155 #else 156 u_int cp_minrev:4; /* minor revision identifier */ 157 u_int cp_majrev:4; /* major revision identifier */ 158 u_int cp_imp:8; /* implementation identifier */ 159 u_int pad1:16; /* reserved */ 160 #endif 161 } cpu; 162 }; 163 164 165 #ifdef _KERNEL 166 167 /* 168 * Global variables used to communicate CPU type, and parameters 169 * such as cache size, from locore to higher-level code (e.g., pmap). 170 */ 171 extern union cpuprid cpu_id; 172 extern union cpuprid fpu_id; 173 extern int cpu_arch; 174 extern u_int mips_L1DataCacheSize; 175 extern u_int mips_L1InstCacheSize; 176 extern u_int mips_L1DataCacheLSize; 177 extern u_int mips_L1InstCacheLSize; 178 extern u_int mips_L2CacheSize; 179 extern u_int mips_L2CacheLSize; 180 extern u_int mips_CacheAliasMask; 181 extern struct intr_tab intr_tab[]; 182 #endif 183 184 #endif /* _MIPS_LOCORE_H */ 185
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