locore.h revision 1.98
1 /* $NetBSD: locore.h,v 1.98 2015/06/01 22:55:13 matt Exp $ */ 2 3 /* 4 * This file should not be included by MI code!!! 5 */ 6 7 /* 8 * Copyright 1996 The Board of Trustees of The Leland Stanford 9 * Junior University. All Rights Reserved. 10 * 11 * Permission to use, copy, modify, and distribute this 12 * software and its documentation for any purpose and without 13 * fee is hereby granted, provided that the above copyright 14 * notice appear in all copies. Stanford University 15 * makes no representations about the suitability of this 16 * software for any purpose. It is provided "as is" without 17 * express or implied warranty. 18 */ 19 20 /* 21 * Jump table for MIPS CPU locore functions that are implemented 22 * differently on different generations, or instruction-level 23 * architecture (ISA) level, the Mips family. 24 * 25 * We currently provide support for MIPS I and MIPS III. 26 */ 27 28 #ifndef _MIPS_LOCORE_H 29 #define _MIPS_LOCORE_H 30 31 #if !defined(_LKM) && defined(_KERNEL_OPT) 32 #include "opt_cputype.h" 33 #endif 34 35 #include <mips/mutex.h> 36 #include <mips/cpuregs.h> 37 #include <mips/reg.h> 38 39 struct tlbmask; 40 struct trapframe; 41 42 void trap(uint32_t, uint32_t, vaddr_t, vaddr_t, struct trapframe *); 43 void ast(void); 44 45 void mips_fpu_trap(vaddr_t, struct trapframe *); 46 void mips_fpu_intr(vaddr_t, struct trapframe *); 47 48 vaddr_t mips_emul_branch(struct trapframe *, vaddr_t, uint32_t, bool); 49 void mips_emul_inst(uint32_t, uint32_t, vaddr_t, struct trapframe *); 50 51 void mips_emul_fp(uint32_t, struct trapframe *, uint32_t); 52 void mips_emul_branchdelayslot(uint32_t, struct trapframe *, uint32_t); 53 54 void mips_emul_lwc0(uint32_t, struct trapframe *, uint32_t); 55 void mips_emul_swc0(uint32_t, struct trapframe *, uint32_t); 56 void mips_emul_special(uint32_t, struct trapframe *, uint32_t); 57 void mips_emul_special3(uint32_t, struct trapframe *, uint32_t); 58 59 void mips_emul_lwc1(uint32_t, struct trapframe *, uint32_t); 60 void mips_emul_swc1(uint32_t, struct trapframe *, uint32_t); 61 void mips_emul_ldc1(uint32_t, struct trapframe *, uint32_t); 62 void mips_emul_sdc1(uint32_t, struct trapframe *, uint32_t); 63 64 void mips_emul_lb(uint32_t, struct trapframe *, uint32_t); 65 void mips_emul_lbu(uint32_t, struct trapframe *, uint32_t); 66 void mips_emul_lh(uint32_t, struct trapframe *, uint32_t); 67 void mips_emul_lhu(uint32_t, struct trapframe *, uint32_t); 68 void mips_emul_lw(uint32_t, struct trapframe *, uint32_t); 69 void mips_emul_lwl(uint32_t, struct trapframe *, uint32_t); 70 void mips_emul_lwr(uint32_t, struct trapframe *, uint32_t); 71 #if defined(__mips_n32) || defined(__mips_n64) || defined(__mips_o64) 72 void mips_emul_lwu(uint32_t, struct trapframe *, uint32_t); 73 void mips_emul_ld(uint32_t, struct trapframe *, uint32_t); 74 void mips_emul_ldl(uint32_t, struct trapframe *, uint32_t); 75 void mips_emul_ldr(uint32_t, struct trapframe *, uint32_t); 76 #endif 77 void mips_emul_sb(uint32_t, struct trapframe *, uint32_t); 78 void mips_emul_sh(uint32_t, struct trapframe *, uint32_t); 79 void mips_emul_sw(uint32_t, struct trapframe *, uint32_t); 80 void mips_emul_swl(uint32_t, struct trapframe *, uint32_t); 81 void mips_emul_swr(uint32_t, struct trapframe *, uint32_t); 82 #if defined(__mips_n32) || defined(__mips_n64) || defined(__mips_o64) 83 void mips_emul_sd(uint32_t, struct trapframe *, uint32_t); 84 void mips_emul_sdl(uint32_t, struct trapframe *, uint32_t); 85 void mips_emul_sdr(uint32_t, struct trapframe *, uint32_t); 86 #endif 87 88 uint32_t mips_cp0_cause_read(void); 89 void mips_cp0_cause_write(uint32_t); 90 uint32_t mips_cp0_status_read(void); 91 void mips_cp0_status_write(uint32_t); 92 93 void softint_process(uint32_t); 94 void softint_fast_dispatch(struct lwp *, int); 95 96 /* 97 * Convert an address to an offset used in a MIPS jump instruction. The offset 98 * contains the low 28 bits (allowing a jump to anywhere within the same 256MB 99 * segment of address space) of the address but since mips instructions are 100 * always on a 4 byte boundary the low 2 bits are always zero so the 28 bits 101 * get shifted right by 2 bits leaving us with a 26 bit result. To make the 102 * offset, we shift left to clear the upper four bits and then right by 6. 103 */ 104 #define fixup_addr2offset(x) ((((uint32_t)(uintptr_t)(x)) << 4) >> 6) 105 typedef bool (*mips_fixup_callback_t)(int32_t, uint32_t [2], void *); 106 struct mips_jump_fixup_info { 107 uint32_t jfi_stub; 108 uint32_t jfi_real; 109 }; 110 111 void fixup_splcalls(void); /* splstubs.c */ 112 bool mips_fixup_exceptions(mips_fixup_callback_t, void *); 113 bool mips_fixup_zero_relative(int32_t, uint32_t [2]); 114 intptr_t 115 mips_fixup_addr(const uint32_t *); 116 void mips_fixup_stubs(uint32_t *, uint32_t *); 117 118 /* 119 * Define these stubs... 120 */ 121 void mips_cpu_switch_resume(struct lwp *); 122 void tlb_set_asid(uint32_t); 123 void tlb_invalidate_all(void); 124 void tlb_invalidate_globals(void); 125 void tlb_invalidate_asids(uint32_t, uint32_t); 126 void tlb_invalidate_addr(vaddr_t); 127 u_int tlb_record_asids(u_long *, uint32_t); 128 int tlb_update(vaddr_t, uint32_t); 129 void tlb_enter(size_t, vaddr_t, uint32_t); 130 void tlb_read_indexed(size_t, struct tlbmask *); 131 void tlb_write_indexed(size_t, const struct tlbmask *); 132 void wbflush(void); 133 134 #ifdef MIPS1 135 void mips1_tlb_invalidate_all(void); 136 137 uint32_t tx3900_cp0_config_read(void); 138 #endif 139 140 #if (MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0 141 uint32_t mips3_cp0_compare_read(void); 142 void mips3_cp0_compare_write(uint32_t); 143 144 uint32_t mips3_cp0_config_read(void); 145 void mips3_cp0_config_write(uint32_t); 146 147 #if (MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0 148 uint32_t mipsNN_cp0_config1_read(void); 149 void mipsNN_cp0_config1_write(uint32_t); 150 uint32_t mipsNN_cp0_config2_read(void); 151 uint32_t mipsNN_cp0_config3_read(void); 152 153 intptr_t mipsNN_cp0_watchlo_read(u_int); 154 void mipsNN_cp0_watchlo_write(u_int, intptr_t); 155 uint32_t mipsNN_cp0_watchhi_read(u_int); 156 void mipsNN_cp0_watchhi_write(u_int, uint32_t); 157 158 int32_t mipsNN_cp0_ebase_read(void); 159 void mipsNN_cp0_ebase_write(int32_t); 160 161 #if (MIPS32R2 + MIPS64R2) > 0 162 void mipsNN_cp0_hwrena_write(uint32_t); 163 void mipsNN_cp0_userlocal_write(void *); 164 #endif 165 #endif 166 167 uint32_t mips3_cp0_count_read(void); 168 void mips3_cp0_count_write(uint32_t); 169 170 uint32_t mips3_cp0_wired_read(void); 171 void mips3_cp0_wired_write(uint32_t); 172 void mips3_cp0_pg_mask_write(uint32_t); 173 174 #if defined(__GNUC__) && !defined(__mips_o32) 175 static inline uint64_t 176 mips3_ld(const volatile uint64_t *va) 177 { 178 uint64_t rv; 179 #if defined(__mips_o32) 180 uint32_t sr; 181 182 sr = mips_cp0_status_read(); 183 mips_cp0_status_write(sr & ~MIPS_SR_INT_IE); 184 185 __asm volatile( 186 ".set push \n\t" 187 ".set mips3 \n\t" 188 ".set noreorder \n\t" 189 ".set noat \n\t" 190 "ld %M0,0(%1) \n\t" 191 "dsll32 %L0,%M0,0 \n\t" 192 "dsra32 %M0,%M0,0 \n\t" /* high word */ 193 "dsra32 %L0,%L0,0 \n\t" /* low word */ 194 "ld %0,0(%1) \n\t" 195 ".set pop" 196 : "=d"(rv) 197 : "r"(va)); 198 199 mips_cp0_status_write(sr); 200 #elif defined(_LP64) 201 rv = *va; 202 #else 203 __asm volatile("ld %0,0(%1)" : "=d"(rv) : "r"(va)); 204 #endif 205 206 return rv; 207 } 208 static inline void 209 mips3_sd(volatile uint64_t *va, uint64_t v) 210 { 211 #if defined(__mips_o32) 212 uint32_t sr; 213 214 sr = mips_cp0_status_read(); 215 mips_cp0_status_write(sr & ~MIPS_SR_INT_IE); 216 217 __asm volatile( 218 ".set push \n\t" 219 ".set mips3 \n\t" 220 ".set noreorder \n\t" 221 ".set noat \n\t" 222 "dsll32 %M0,%M0,0 \n\t" 223 "dsll32 %L0,%L0,0 \n\t" 224 "dsrl32 %L0,%L0,0 \n\t" 225 "or %0,%L0,%M0 \n\t" 226 "sd %0,0(%1) \n\t" 227 ".set pop" 228 : "=d"(v) : "0"(v), "r"(va)); 229 230 mips_cp0_status_write(sr); 231 #elif defined(_LP64) 232 *va = v; 233 #else 234 __asm volatile("sd %0,0(%1)" :: "r"(v), "r"(va)); 235 #endif 236 } 237 #else 238 uint64_t mips3_ld(volatile uint64_t *va); 239 void mips3_sd(volatile uint64_t *, uint64_t); 240 #endif /* __GNUC__ */ 241 #endif /* (MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0 */ 242 243 #if (MIPS3 + MIPS4 + MIPS64 + MIPS64R2) > 0 244 static __inline uint32_t mips3_lw_a64(uint64_t addr) __unused; 245 static __inline void mips3_sw_a64(uint64_t addr, uint32_t val) __unused; 246 247 static __inline uint32_t 248 mips3_lw_a64(uint64_t addr) 249 { 250 uint32_t rv; 251 #if defined(__mips_o32) 252 uint32_t sr; 253 254 sr = mips_cp0_status_read(); 255 mips_cp0_status_write((sr & ~MIPS_SR_INT_IE) | MIPS3_SR_KX); 256 257 __asm volatile ( 258 ".set push \n\t" 259 ".set mips3 \n\t" 260 ".set noreorder \n\t" 261 ".set noat \n\t" 262 "dsll32 %M1,%M1,0 \n\t" 263 "dsll32 %L1,%L1,0 \n\t" 264 "dsrl32 %L1,%L1,0 \n\t" 265 "or %1,%M1,%L1 \n\t" 266 "lw %0, 0(%1) \n\t" 267 ".set pop" 268 : "=r"(rv), "=d"(addr) 269 : "1"(addr) 270 ); 271 272 mips_cp0_status_write(sr); 273 #elif defined(__mips_n32) 274 uint32_t sr = mips_cp0_status_read(); 275 mips_cp0_status_write((sr & ~MIPS_SR_INT_IE) | MIPS3_SR_KX); 276 __asm volatile("lw %0, 0(%1)" : "=r"(rv) : "d"(addr)); 277 mips_cp0_status_write(sr); 278 #elif defined(_LP64) 279 rv = *(const uint32_t *)addr; 280 #else 281 #error unknown ABI 282 #endif 283 return (rv); 284 } 285 286 static __inline void 287 mips3_sw_a64(uint64_t addr, uint32_t val) 288 { 289 #if defined(__mips_o32) 290 uint32_t sr; 291 292 sr = mips_cp0_status_read(); 293 mips_cp0_status_write((sr & ~MIPS_SR_INT_IE) | MIPS3_SR_KX); 294 295 __asm volatile ( 296 ".set push \n\t" 297 ".set mips3 \n\t" 298 ".set noreorder \n\t" 299 ".set noat \n\t" 300 "dsll32 %M0,%M0,0 \n\t" 301 "dsll32 %L0,%L0,0 \n\t" 302 "dsrl32 %L0,%L0,0 \n\t" 303 "or %0,%M0,%L0 \n\t" 304 "sw %1, 0(%0) \n\t" 305 ".set pop" 306 : "=d"(addr): "r"(val), "0"(addr) 307 ); 308 309 mips_cp0_status_write(sr); 310 #elif defined(__mips_n32) 311 uint32_t sr = mips_cp0_status_read(); 312 mips_cp0_status_write((sr & ~MIPS_SR_INT_IE) | MIPS3_SR_KX); 313 __asm volatile("sw %1, 0(%0)" :: "d"(addr), "r"(val)); 314 mips_cp0_status_write(sr); 315 #elif defined(_LP64) 316 *(uint32_t *)addr = val; 317 #else 318 #error unknown ABI 319 #endif 320 } 321 #endif /* (MIPS3 + MIPS4 + MIPS64 + MIPS64R2) > 0 */ 322 323 #if (MIPS64 + MIPS64R2) > 0 && !defined(__mips_o32) 324 /* 64-bits address space accessor for n32, n64 ABI */ 325 326 static __inline uint64_t mips64_ld_a64(uint64_t addr) __unused; 327 static __inline void mips64_sd_a64(uint64_t addr, uint64_t val) __unused; 328 329 static __inline uint64_t 330 mips64_ld_a64(uint64_t addr) 331 { 332 uint64_t rv; 333 #if defined(__mips_n32) 334 __asm volatile("ld %0, 0(%1)" : "=r"(rv) : "d"(addr)); 335 #elif defined(_LP64) 336 rv = *(volatile uint64_t *)addr; 337 #else 338 #error unknown ABI 339 #endif 340 return (rv); 341 } 342 343 static __inline void 344 mips64_sd_a64(uint64_t addr, uint64_t val) 345 { 346 #if defined(__mips_n32) 347 __asm volatile("sd %1, 0(%0)" :: "d"(addr), "r"(val)); 348 #elif defined(_LP64) 349 *(volatile uint64_t *)addr = val; 350 #else 351 #error unknown ABI 352 #endif 353 } 354 #endif /* (MIPS64 + MIPS64R2) > 0 */ 355 356 /* 357 * A vector with an entry for each mips-ISA-level dependent 358 * locore function, and macros which jump through it. 359 */ 360 typedef struct { 361 void (*ljv_cpu_switch_resume)(struct lwp *); 362 intptr_t ljv_lwp_trampoline; 363 void (*ljv_wbflush)(void); 364 void (*ljv_tlb_set_asid)(uint32_t pid); 365 void (*ljv_tlb_invalidate_asids)(uint32_t, uint32_t); 366 void (*ljv_tlb_invalidate_addr)(vaddr_t); 367 void (*ljv_tlb_invalidate_globals)(void); 368 void (*ljv_tlb_invalidate_all)(void); 369 u_int (*ljv_tlb_record_asids)(u_long *, uint32_t); 370 int (*ljv_tlb_update)(vaddr_t, uint32_t); 371 void (*ljv_tlb_enter)(size_t, vaddr_t, uint32_t); 372 void (*ljv_tlb_read_indexed)(size_t, struct tlbmask *); 373 void (*ljv_tlb_write_indexed)(size_t, const struct tlbmask *); 374 } mips_locore_jumpvec_t; 375 376 typedef struct { 377 u_int (*lav_atomic_cas_uint)(volatile u_int *, u_int, u_int); 378 u_long (*lav_atomic_cas_ulong)(volatile u_long *, u_long, u_long); 379 int (*lav_ucas_uint)(volatile u_int *, u_int, u_int, u_int *); 380 int (*lav_ucas_ulong)(volatile u_long *, u_long, u_long, u_long *); 381 void (*lav_mutex_enter)(kmutex_t *); 382 void (*lav_mutex_exit)(kmutex_t *); 383 void (*lav_mutex_spin_enter)(kmutex_t *); 384 void (*lav_mutex_spin_exit)(kmutex_t *); 385 } mips_locore_atomicvec_t; 386 387 void mips_set_wbflush(void (*)(void)); 388 void mips_wait_idle(void); 389 390 void stacktrace(void); 391 void logstacktrace(void); 392 393 struct cpu_info; 394 struct splsw; 395 396 struct locoresw { 397 void (*lsw_wbflush)(void); 398 void (*lsw_cpu_idle)(void); 399 int (*lsw_send_ipi)(struct cpu_info *, int); 400 void (*lsw_cpu_offline_md)(void); 401 void (*lsw_cpu_init)(struct cpu_info *); 402 void (*lsw_cpu_run)(struct cpu_info *); 403 int (*lsw_bus_error)(unsigned int); 404 }; 405 406 struct mips_vmfreelist { 407 paddr_t fl_start; 408 paddr_t fl_end; 409 int fl_freelist; 410 }; 411 412 /* 413 * The "active" locore-function vector, and 414 */ 415 extern const mips_locore_atomicvec_t mips_llsc_locore_atomicvec; 416 417 extern mips_locore_atomicvec_t mips_locore_atomicvec; 418 extern mips_locore_jumpvec_t mips_locore_jumpvec; 419 extern struct locoresw mips_locoresw; 420 421 struct splsw; 422 struct mips_vmfreelist; 423 struct phys_ram_seg; 424 425 void mips64r2_vector_init(const struct splsw *); 426 void mips_vector_init(const struct splsw *, bool); 427 void mips_init_msgbuf(void); 428 void mips_init_lwp0_uarea(void); 429 void mips_page_physload(vaddr_t, vaddr_t, 430 const struct phys_ram_seg *, size_t, 431 const struct mips_vmfreelist *, size_t); 432 433 434 /* 435 * CPU identification, from PRID register. 436 */ 437 #define MIPS_PRID_REV(x) (((x) >> 0) & 0x00ff) 438 #define MIPS_PRID_IMPL(x) (((x) >> 8) & 0x00ff) 439 440 /* pre-MIPS32/64 */ 441 #define MIPS_PRID_RSVD(x) (((x) >> 16) & 0xffff) 442 #define MIPS_PRID_REV_MIN(x) ((MIPS_PRID_REV(x) >> 0) & 0x0f) 443 #define MIPS_PRID_REV_MAJ(x) ((MIPS_PRID_REV(x) >> 4) & 0x0f) 444 445 /* MIPS32/64 */ 446 #define MIPS_PRID_CID(x) (((x) >> 16) & 0x00ff) /* Company ID */ 447 #define MIPS_PRID_CID_PREHISTORIC 0x00 /* Not MIPS32/64 */ 448 #define MIPS_PRID_CID_MTI 0x01 /* MIPS Technologies, Inc. */ 449 #define MIPS_PRID_CID_BROADCOM 0x02 /* Broadcom */ 450 #define MIPS_PRID_CID_ALCHEMY 0x03 /* Alchemy Semiconductor */ 451 #define MIPS_PRID_CID_SIBYTE 0x04 /* SiByte */ 452 #define MIPS_PRID_CID_SANDCRAFT 0x05 /* SandCraft */ 453 #define MIPS_PRID_CID_PHILIPS 0x06 /* Philips */ 454 #define MIPS_PRID_CID_TOSHIBA 0x07 /* Toshiba */ 455 #define MIPS_PRID_CID_MICROSOFT 0x07 /* Microsoft also, sigh */ 456 #define MIPS_PRID_CID_LSI 0x08 /* LSI */ 457 /* 0x09 unannounced */ 458 /* 0x0a unannounced */ 459 #define MIPS_PRID_CID_LEXRA 0x0b /* Lexra */ 460 #define MIPS_PRID_CID_RMI 0x0c /* RMI / NetLogic */ 461 #define MIPS_PRID_CID_CAVIUM 0x0d /* Cavium */ 462 #define MIPS_PRID_CID_INGENIC 0xe1 463 #define MIPS_PRID_COPTS(x) (((x) >> 24) & 0x00ff) /* Company Options */ 464 465 #ifdef _KERNEL 466 /* 467 * Global variables used to communicate CPU type, and parameters 468 * such as cache size, from locore to higher-level code (e.g., pmap). 469 */ 470 void mips_pagecopy(void *dst, void *src); 471 void mips_pagezero(void *dst); 472 473 #ifdef __HAVE_MIPS_MACHDEP_CACHE_CONFIG 474 void mips_machdep_cache_config(void); 475 #endif 476 477 /* 478 * trapframe argument passed to trap() 479 */ 480 481 #if 0 482 #define TF_AST 0 /* really zero */ 483 #define TF_V0 _R_V0 484 #define TF_V1 _R_V1 485 #define TF_A0 _R_A0 486 #define TF_A1 _R_A1 487 #define TF_A2 _R_A2 488 #define TF_A3 _R_A3 489 #define TF_T0 _R_T0 490 #define TF_T1 _R_T1 491 #define TF_T2 _R_T2 492 #define TF_T3 _R_T3 493 494 #if defined(__mips_n32) || defined(__mips_n64) 495 #define TF_A4 _R_A4 496 #define TF_A5 _R_A5 497 #define TF_A6 _R_A6 498 #define TF_A7 _R_A7 499 #else 500 #define TF_T4 _R_T4 501 #define TF_T5 _R_T5 502 #define TF_T6 _R_T6 503 #define TF_T7 _R_T7 504 #endif /* __mips_n32 || __mips_n64 */ 505 506 #define TF_TA0 _R_TA0 507 #define TF_TA1 _R_TA1 508 #define TF_TA2 _R_TA2 509 #define TF_TA3 _R_TA3 510 511 #define TF_T8 _R_T8 512 #define TF_T9 _R_T9 513 514 #define TF_RA _R_RA 515 #define TF_SR _R_SR 516 #define TF_MULLO _R_MULLO 517 #define TF_MULHI _R_MULLO 518 #define TF_EPC _R_PC /* may be changed by trap() call */ 519 520 #define TF_NREGS (sizeof(struct reg) / sizeof(mips_reg_t)) 521 #endif 522 523 struct trapframe { 524 struct reg tf_registers; 525 #define tf_regs tf_registers.r_regs 526 uint32_t tf_ppl; /* previous priority level */ 527 mips_reg_t tf_pad; /* for 8 byte aligned */ 528 }; 529 530 CTASSERT(sizeof(struct trapframe) % (4*sizeof(mips_reg_t)) == 0); 531 532 /* 533 * Stack frame for kernel traps. four args passed in registers. 534 * A trapframe is pointed to by the 5th arg, and a dummy sixth argument 535 * is used to avoid alignment problems 536 */ 537 538 struct kernframe { 539 #if defined(__mips_o32) || defined(__mips_o64) 540 register_t cf_args[4 + 1]; 541 #if defined(__mips_o32) 542 register_t cf_pad; /* (for 8 byte alignment) */ 543 #endif 544 #endif 545 #if defined(__mips_n32) || defined(__mips_n64) 546 register_t cf_pad[2]; /* for 16 byte alignment */ 547 #endif 548 register_t cf_sp; 549 register_t cf_ra; 550 struct trapframe cf_frame; 551 }; 552 553 CTASSERT(sizeof(struct kernframe) % (2*sizeof(mips_reg_t)) == 0); 554 555 /* 556 * PRocessor IDentity TABle 557 */ 558 559 struct pridtab { 560 int cpu_cid; 561 int cpu_pid; 562 int cpu_rev; /* -1 == wildcard */ 563 int cpu_copts; /* -1 == wildcard */ 564 int cpu_isa; /* -1 == probed (mips32/mips64) */ 565 int cpu_ntlb; /* -1 == unknown, 0 == probed */ 566 int cpu_flags; 567 u_int cpu_cp0flags; /* presence of some cp0 regs */ 568 u_int cpu_cidflags; /* company-specific flags */ 569 const char *cpu_name; 570 }; 571 572 /* 573 * bitfield defines for cpu_cp0flags 574 */ 575 #define MIPS_CP0FL_USE __BIT(0) /* use these flags */ 576 #define MIPS_CP0FL_ECC __BIT(1) 577 #define MIPS_CP0FL_CACHE_ERR __BIT(2) 578 #define MIPS_CP0FL_EIRR __BIT(3) 579 #define MIPS_CP0FL_EIMR __BIT(4) 580 #define MIPS_CP0FL_EBASE __BIT(5) 581 #define MIPS_CP0FL_CONFIG __BIT(6) 582 #define MIPS_CP0FL_CONFIG1 __BIT(7) 583 #define MIPS_CP0FL_CONFIG2 __BIT(8) 584 #define MIPS_CP0FL_CONFIG3 __BIT(9) 585 #define MIPS_CP0FL_CONFIG4 __BIT(10) 586 #define MIPS_CP0FL_CONFIG5 __BIT(11) 587 #define MIPS_CP0FL_CONFIG6 __BIT(12) 588 #define MIPS_CP0FL_CONFIG7 __BIT(13) 589 #define MIPS_CP0FL_USERLOCAL __BIT(14) 590 #define MIPS_CP0FL_HWRENA __BIT(15) 591 592 /* 593 * cpu_cidflags defines, by company 594 */ 595 /* 596 * RMI company-specific cpu_cidflags 597 */ 598 #define MIPS_CIDFL_RMI_TYPE __BITS(2,0) 599 # define CIDFL_RMI_TYPE_XLR 0 600 # define CIDFL_RMI_TYPE_XLS 1 601 # define CIDFL_RMI_TYPE_XLP 2 602 #define MIPS_CIDFL_RMI_THREADS_MASK __BITS(6,3) 603 # define MIPS_CIDFL_RMI_THREADS_SHIFT 3 604 #define MIPS_CIDFL_RMI_CORES_MASK __BITS(10,7) 605 # define MIPS_CIDFL_RMI_CORES_SHIFT 7 606 # define LOG2_1 0 607 # define LOG2_2 1 608 # define LOG2_4 2 609 # define LOG2_8 3 610 # define MIPS_CIDFL_RMI_CPUS(ncores, nthreads) \ 611 ((LOG2_ ## ncores << MIPS_CIDFL_RMI_CORES_SHIFT) \ 612 |(LOG2_ ## nthreads << MIPS_CIDFL_RMI_THREADS_SHIFT)) 613 # define MIPS_CIDFL_RMI_NTHREADS(cidfl) \ 614 (1 << (((cidfl) & MIPS_CIDFL_RMI_THREADS_MASK) \ 615 >> MIPS_CIDFL_RMI_THREADS_SHIFT)) 616 # define MIPS_CIDFL_RMI_NCORES(cidfl) \ 617 (1 << (((cidfl) & MIPS_CIDFL_RMI_CORES_MASK) \ 618 >> MIPS_CIDFL_RMI_CORES_SHIFT)) 619 #define MIPS_CIDFL_RMI_L2SZ_MASK __BITS(14,11) 620 # define MIPS_CIDFL_RMI_L2SZ_SHIFT 11 621 # define RMI_L2SZ_256KB 0 622 # define RMI_L2SZ_512KB 1 623 # define RMI_L2SZ_1MB 2 624 # define RMI_L2SZ_2MB 3 625 # define RMI_L2SZ_4MB 4 626 # define MIPS_CIDFL_RMI_L2(l2sz) \ 627 (RMI_L2SZ_ ## l2sz << MIPS_CIDFL_RMI_L2SZ_SHIFT) 628 # define MIPS_CIDFL_RMI_L2SZ(cidfl) \ 629 ((256*1024) << (((cidfl) & MIPS_CIDFL_RMI_L2SZ_MASK) \ 630 >> MIPS_CIDFL_RMI_L2SZ_SHIFT)) 631 632 #endif /* _KERNEL */ 633 #endif /* _MIPS_LOCORE_H */ 634
Indexes created Tue Sep 30 11:09:46 GMT 2025