mips1_pte.h revision 1.18
1 /* $NetBSD: mips1_pte.h,v 1.18 2011/02/08 20:20:19 rmind Exp $ */ 2 3 /* 4 * Copyright (c) 1988 University of Utah. 5 * Copyright (c) 1992, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * the Systems Programming Group of the University of Utah Computer 10 * Science Department and Ralph Campbell. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: Utah Hdr: pte.h 1.11 89/09/03 37 * 38 * @(#)pte.h 8.1 (Berkeley) 6/10/93 39 */ 40 41 /* 42 * R2000 hardware page table entry 43 */ 44 45 #ifndef _LOCORE 46 struct mips1_pte { 47 #if BYTE_ORDER == BIG_ENDIAN 48 unsigned int pg_pfnum:20, /* HW: core page frame number or 0 */ 49 pg_n:1, /* HW: non-cacheable bit */ 50 pg_m:1, /* HW: dirty bit */ 51 pg_v:1, /* HW: valid bit */ 52 pg_g:1, /* HW: ignore pid bit */ 53 :4, 54 pg_swapm:1, /* SW: page must be forced to swap */ 55 pg_fod:1, /* SW: is fill on demand (=0) */ 56 pg_prot:2; /* SW: access control */ 57 #endif 58 #if BYTE_ORDER == LITTLE_ENDIAN 59 unsigned int pg_prot:2, /* SW: access control */ 60 pg_fod:1, /* SW: is fill on demand (=0) */ 61 pg_swapm:1, /* SW: page must be forced to swap */ 62 :4, 63 pg_g:1, /* HW: ignore pid bit */ 64 pg_v:1, /* HW: valid bit */ 65 pg_m:1, /* HW: dirty bit */ 66 pg_n:1, /* HW: non-cacheable bit */ 67 pg_pfnum:20; /* HW: core page frame number or 0 */ 68 #endif 69 }; 70 #endif /* _LOCORE */ 71 72 #define MIPS1_PG_PROT 0x00000003 73 #define MIPS1_PG_RW 0x00000000 74 #define MIPS1_PG_RO 0x00000001 75 #define MIPS1_PG_WIRED 0x00000002 76 #define MIPS1_PG_G 0x00000100 77 #define MIPS1_PG_V 0x00000200 78 #define MIPS1_PG_NV 0x00000000 79 #define MIPS1_PG_D 0x00000400 80 #define MIPS1_PG_N 0x00000800 81 #define MIPS1_PG_FRAME 0xfffff000 82 #define MIPS1_PG_SHIFT 12 83 #define MIPS1_PG_PFNUM(x) (((x) & MIPS1_PG_FRAME) >> MIPS1_PG_SHIFT) 84 85 #define MIPS1_PG_ROPAGE MIPS1_PG_V 86 #define MIPS1_PG_RWPAGE MIPS1_PG_D 87 #define MIPS1_PG_CWPAGE 0 88 #define MIPS1_PG_RWNCPAGE (MIPS1_PG_D | MIPS1_PG_N) 89 #define MIPS1_PG_CWNCPAGE MIPS1_PG_N 90 #define MIPS1_PG_IOPAGE (MIPS1_PG_D | MIPS1_PG_N) 91 92 #define mips1_tlbpfn_to_paddr(x) ((x) & MIPS1_PG_FRAME) 93 #define mips1_paddr_to_tlbpfn(x) (x) 94 95 #define MIPS1_PTE_TO_PADDR(pte) ((unsigned)(pte) & MIPS1_PG_FRAME) 96 #define MIPS1_PAGE_IS_RDONLY(pte,va) ((int)(pte) & MIPS1_PG_RO) 97
Indexes created Wed Sep 24 15:09:51 GMT 2025