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      1 /*	$NetBSD: cache_r4k.c,v 1.14 2016/07/11 23:06:54 matt Exp $	*/
      2 
      3 /*
      4  * Copyright 2001 Wasabi Systems, Inc.
      5  * All rights reserved.
      6  *
      7  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
      8  *
      9  * Redistribution and use in source and binary forms, with or without
     10  * modification, are permitted provided that the following conditions
     11  * are met:
     12  * 1. Redistributions of source code must retain the above copyright
     13  *    notice, this list of conditions and the following disclaimer.
     14  * 2. Redistributions in binary form must reproduce the above copyright
     15  *    notice, this list of conditions and the following disclaimer in the
     16  *    documentation and/or other materials provided with the distribution.
     17  * 3. All advertising materials mentioning features or use of this software
     18  *    must display the following acknowledgement:
     19  *	This product includes software developed for the NetBSD Project by
     20  *	Wasabi Systems, Inc.
     21  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
     22  *    or promote products derived from this software without specific prior
     23  *    written permission.
     24  *
     25  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
     26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
     29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     35  * POSSIBILITY OF SUCH DAMAGE.
     36  */
     37 
     38 #include <sys/cdefs.h>
     39 __KERNEL_RCSID(0, "$NetBSD: cache_r4k.c,v 1.14 2016/07/11 23:06:54 matt Exp $");
     40 
     41 #include <sys/param.h>
     42 
     43 #include <mips/cpuregs.h>
     44 #include <mips/cache.h>
     45 #include <mips/cache_r4k.h>
     46 
     47 /*
     48  * Cache operations for R4000/R4400-style caches:
     49  *
     50  *	- Direct-mapped
     51  *	- Write-back
     52  *	- Virtually indexed, physically tagged
     53  *
     54  * XXX Does not handle split secondary caches.
     55  */
     56 
     57 void
     58 r4k_icache_sync_all_generic(void)
     59 {
     60 	mips_dcache_wbinv_all();
     61 
     62 	mips_intern_icache_sync_range_index(MIPS_PHYS_TO_KSEG0(0),
     63 	    mips_cache_info.mci_picache_size);
     64 }
     65 
     66 void
     67 r4k_icache_sync_range_generic(register_t va, vsize_t size)
     68 {
     69 	mips_dcache_wb_range(va, size);
     70 
     71 	mips_intern_icache_sync_range_index(va, size);
     72 }
     73 
     74 void
     75 r4k_icache_sync_range_index_generic(vaddr_t va, vsize_t size)
     76 {
     77 	mips_dcache_wbinv_range_index(va, size);
     78 
     79 	/*
     80 	 * Since we're doing Index ops, we expect to not be able
     81 	 * to access the address we've been given.  So, get the
     82 	 * bits that determine the cache index, and make a KSEG0
     83 	 * address out of them.
     84 	 */
     85 	va = MIPS_PHYS_TO_KSEG0(va & mips_cache_info.mci_picache_way_mask);
     86 	size &= mips_cache_info.mci_picache_way_mask;
     87 
     88 	mips_intern_icache_sync_range_index(va, size);
     89 }
     90 
     91 void
     92 r4k_pdcache_wbinv_all_generic(void)
     93 {
     94 	mips_intern_pdcache_wbinv_range_index(MIPS_PHYS_TO_KSEG0(0),
     95 	     mips_cache_info.mci_pdcache_size);
     96 }
     97 
     98 void
     99 r4k_sdcache_wbinv_all_generic(void)
    100 {
    101 	mips_intern_sdcache_wbinv_range_index(MIPS_PHYS_TO_KSEG0(0),
    102 	     mips_cache_info.mci_sdcache_size);
    103 }
    104