1 /* $NetBSD: ralink_i2c.c,v 1.9 2025/09/15 13:23:02 thorpej Exp $ */ 2 /*- 3 * Copyright (c) 2011 CradlePoint Technology, Inc. 4 * All rights reserved. 5 * 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY CRADLEPOINT TECHNOLOGY, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* ra_i2c.c - Ralink i2c 3052 driver */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: ralink_i2c.c,v 1.9 2025/09/15 13:23:02 thorpej Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/errno.h> 38 #include <sys/kernel.h> 39 #include <sys/proc.h> 40 #include <sys/systm.h> 41 42 #include <dev/i2c/i2cvar.h> 43 44 #include <mips/ralink/ralink_var.h> 45 #include <mips/ralink/ralink_reg.h> 46 47 #if 0 48 /* 49 * Defined for the Ralink 3050, w/320MHz CPU: milage may vary. 50 * Set the I2C clock to 100K bps (low speed) transfer rate. 51 * Value is based upon the forms defined in the Ralink reference document 52 * for RT3050, page 53. JCL. 53 */ 54 #define CLKDIV_VALUE 533 55 #endif 56 57 /* 58 * Slow the I2C bus clock to 12.5 KHz to work around the misbehavior 59 * of the TI part. 60 */ 61 #define CLKDIV_VALUE 4264 62 63 #define i2c_busy_loop (clkdiv*30) 64 #define max_ee_busy_loop (clkdiv*25) 65 66 67 typedef struct ra_i2c_softc { 68 device_t sc_dev; 69 struct i2c_controller sc_i2c; 70 bus_space_tag_t sc_memt; 71 bus_space_handle_t sc_i2c_memh; 72 bus_space_handle_t sc_sy_memh; 73 } ra_i2c_softc_t; 74 75 76 static int ra_i2c_match(device_t, cfdata_t, void *); 77 static void ra_i2c_attach(device_t, device_t, void *); 78 79 /* RT3052 I2C functions */ 80 static int i2c_write(ra_i2c_softc_t *, u_long, const u_char *, u_long); 81 static int i2c_read(ra_i2c_softc_t *, u_long, u_char *, u_long); 82 #ifdef NOTYET 83 static void i2c_write_stop(ra_i2c_softc_t *, u_long, u_char *); 84 static void i2c_read_stop(ra_i2c_softc_t *, u_long, u_char *); 85 #endif 86 87 /* i2c driver functions */ 88 int ra_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t, 89 void *, size_t, int); 90 void ra_i2c_reset(ra_i2c_softc_t *); 91 92 CFATTACH_DECL_NEW(ri2c, sizeof(struct ra_i2c_softc), 93 ra_i2c_match, ra_i2c_attach, NULL, NULL); 94 95 unsigned int clkdiv = CLKDIV_VALUE; 96 97 static inline void 98 ra_i2c_busy_wait(ra_i2c_softc_t *sc) 99 { 100 for (int i=0; i < i2c_busy_loop; i++) { 101 uint32_t r; 102 r = bus_space_read_4(sc->sc_memt, sc->sc_i2c_memh, 103 RA_I2C_STATUS); 104 if ((r & I2C_STATUS_BUSY) == 0) 105 break; 106 } 107 } 108 109 int 110 ra_i2c_match(device_t parent, cfdata_t cf, void *aux) 111 { 112 return 1; 113 } 114 115 116 void 117 ra_i2c_attach(device_t parent, device_t self, void *aux) 118 { 119 ra_i2c_softc_t * const sc = device_private(self); 120 const struct mainbus_attach_args *ma = aux; 121 uint32_t r; 122 int error; 123 124 aprint_naive(": Ralink I2C controller\n"); 125 aprint_normal(": Ralink I2C controller\n"); 126 127 /* save out bus space tag */ 128 sc->sc_memt = ma->ma_memt; 129 130 /* Map Sysctl registers */ 131 if ((error = bus_space_map(ma->ma_memt, RA_SYSCTL_BASE, 0x10000, 132 0, &sc->sc_sy_memh)) != 0) { 133 aprint_error_dev(self, "unable to map Sysctl registers, " 134 "error=%d\n", error); 135 return; 136 } 137 138 /* map the I2C registers */ 139 if ((error = bus_space_map(sc->sc_memt, RA_I2C_BASE, 0x100, 140 0, &sc->sc_i2c_memh)) != 0) { 141 aprint_error_dev(self, "unable to map registers, " 142 "error=%d\n", error); 143 bus_space_unmap(ma->ma_memt, sc->sc_sy_memh, 0x10000); 144 return; 145 } 146 147 /* Enable I2C block */ 148 r = bus_space_read_4(sc->sc_memt, sc->sc_sy_memh, 149 RA_SYSCTL_GPIOMODE); 150 r &= ~GPIOMODE_I2C; 151 bus_space_write_4(sc->sc_memt, sc->sc_sy_memh, 152 RA_SYSCTL_GPIOMODE, r); 153 154 iic_tag_init(&sc->sc_i2c); 155 sc->sc_i2c.ic_cookie = sc; 156 sc->sc_i2c.ic_exec = ra_i2c_exec; 157 158 iicbus_attach(self, &sc->sc_i2c); 159 } 160 161 162 163 /* 164 * I2C API 165 */ 166 167 int 168 ra_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *cmdbuf, 169 size_t cmdlen, void *buf, size_t len, int flags) 170 { 171 ra_i2c_softc_t * const sc = cookie; 172 173 /* 174 * Make sure we only pass a seven-bit device address, 175 * as per I2C standard. 176 */ 177 KASSERT(addr <= 127); 178 if (addr > 127) 179 return -1; 180 181 bus_space_write_4(sc->sc_memt, sc->sc_i2c_memh, RA_I2C_DEVADDR, 182 addr); 183 184 ra_i2c_reset(sc); 185 186 /* 187 * Process the requested operation. 188 * There are four I2C operations of interest: 189 * - Write 190 * - Write with stop 191 * - Read 192 * - Read with stop 193 * Because the I2C block on the Ralink part generates stop markers 194 * at approprite places, based upon the byte count, the read and write 195 * with stop operations will rarely be needed. They are included here 196 * as placeholders, but haven't been implemented or tested. 197 */ 198 switch(op) { 199 case I2C_OP_WRITE: 200 return i2c_write(sc, addr, cmdbuf, cmdlen); 201 break; 202 case I2C_OP_READ: 203 return i2c_read(sc, addr, buf, len); 204 break; 205 #ifdef NOTYET 206 case I2C_OP_WRITE_WITH_STOP: 207 i2c_write_stop(sc, addr, buf); 208 break; 209 case I2C_OP_READ_WITH_STOP: 210 i2c_read_stop(sc, addr, buf); 211 break; 212 #endif 213 default: 214 return -1; /* Illegal operation, error return. */ 215 } 216 217 return 0; 218 } 219 220 static int 221 i2c_write(ra_i2c_softc_t *sc, u_long addr, const u_char *data, 222 u_long nbytes) 223 { 224 uint32_t r; 225 int i, j; 226 227 bus_space_write_4(sc->sc_memt, sc->sc_i2c_memh, RA_I2C_DEVADDR, 228 addr); 229 bus_space_write_4(sc->sc_memt, sc->sc_i2c_memh, RA_I2C_BYTECNT, 230 nbytes - 1); 231 bus_space_write_4(sc->sc_memt, sc->sc_i2c_memh, RA_I2C_STARTXFR, 232 I2C_OP_WRITE); 233 234 for (i=0; i < nbytes; i++) { 235 for (j=0; j < max_ee_busy_loop; j++) { 236 r = bus_space_read_4(sc->sc_memt, sc->sc_i2c_memh, 237 RA_I2C_STATUS); 238 if ((r & I2C_STATUS_SDOEMPTY) != 0) { 239 bus_space_write_4(sc->sc_memt, sc->sc_i2c_memh, 240 RA_I2C_DATAOUT, data[i]); 241 break; 242 } 243 } 244 #if 0 245 if ((r & I2C_STATUS_ACKERR) != 0) { 246 aprint_error_dev(sc->sc_dev, "ACK error in %s\n", 247 __func__); 248 return EAGAIN; 249 } 250 #endif 251 if (j == max_ee_busy_loop) { 252 aprint_error_dev(sc->sc_dev, "timeout error in %s\n", 253 __func__); 254 return EAGAIN; 255 } 256 } 257 258 ra_i2c_busy_wait(sc); 259 260 return 0; 261 } 262 263 264 static int 265 i2c_read(ra_i2c_softc_t *sc, u_long addr, u_char *data, u_long nbytes) 266 { 267 bus_space_write_4(sc->sc_memt, sc->sc_i2c_memh, RA_I2C_DEVADDR, 268 addr); 269 bus_space_write_4(sc->sc_memt, sc->sc_i2c_memh, RA_I2C_BYTECNT, 270 nbytes - 1); 271 bus_space_write_4(sc->sc_memt, sc->sc_i2c_memh, RA_I2C_STARTXFR, 272 I2C_OP_READ); 273 274 for (u_int i = 0; i < nbytes; i++) { 275 u_long j; 276 uint32_t r; 277 278 for (j=0; j < max_ee_busy_loop; j++) { 279 r = bus_space_read_4(sc->sc_memt, sc->sc_i2c_memh, 280 RA_I2C_STATUS); 281 if ((r & I2C_STATUS_DATARDY) != 0) { 282 data[i] = bus_space_read_4( 283 sc->sc_memt, sc->sc_i2c_memh, 284 RA_I2C_DATAIN); 285 break; 286 } 287 } 288 #if 0 289 if ((r & I2C_STATUS_ACKERR) != 0) { 290 aprint_error_dev(sc->sc_dev, "ACK error in %s\n", 291 __func__); 292 return EAGAIN; 293 } 294 #endif 295 if (j == max_ee_busy_loop) { 296 aprint_error_dev(sc->sc_dev, "timeout error in %s\n", 297 __func__); 298 return EAGAIN; 299 } 300 } 301 302 ra_i2c_busy_wait(sc); 303 304 return 0; 305 306 } 307 308 309 #ifdef NOTYET 310 static void 311 i2c_write_stop(ra_i2c_softc_t *sc, u_long address, u_char *data) 312 { 313 /* unimplemented */ 314 } 315 316 static void 317 i2c_read_stop(ra_i2c_softc_t *sc, u_long address, u_char *data) 318 { 319 /* unimplemented */ 320 } 321 #endif 322 323 void 324 ra_i2c_reset(ra_i2c_softc_t *sc) 325 { 326 uint32_t r; 327 328 /* reset i2c block */ 329 r = bus_space_read_4(sc->sc_memt, sc->sc_sy_memh, RA_SYSCTL_RST); 330 bus_space_write_4(sc->sc_memt, sc->sc_sy_memh, RA_SYSCTL_RST, 331 r | RST_I2C); 332 bus_space_write_4(sc->sc_memt, sc->sc_sy_memh, RA_SYSCTL_RST, r); 333 334 r = I2C_CONFIG_ADDRLEN(I2C_CONFIG_ADDRLEN_8) | 335 I2C_CONFIG_DEVADLEN(I2C_CONFIG_DEVADLEN_7) | 336 I2C_CONFIG_ADDRDIS; 337 bus_space_write_4(sc->sc_memt, sc->sc_i2c_memh, RA_I2C_CONFIG, r); 338 339 /* 340 * Set the I2C clock divider. Appears to be set to 200,000, 341 * which is strange, as I2C is 100K/400K/3.?M bps. 342 */ 343 bus_space_write_4(sc->sc_memt, sc->sc_i2c_memh, RA_I2C_CLKDIV, 344 clkdiv); 345 } 346
Indexes created Sat Sep 20 22:09:52 GMT 2025