rmixl_fmn.c revision 1.1.2.5
1 /* $NetBSD: rmixl_fmn.c,v 1.1.2.5 2011/02/05 06:11:16 cliff Exp $ */ 2 /*- 3 * Copyright (c) 2010 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Cliff Neighbors. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include "opt_ddb.h" 32 33 #include <sys/cdefs.h> 34 #include <sys/param.h> 35 #include <sys/cpu.h> 36 #include <mips/cpuregs.h> 37 #include <mips/rmi/rmixlreg.h> 38 #include <mips/rmi/rmixlvar.h> 39 #include <mips/rmi/rmixl_intr.h> 40 #include <mips/rmi/rmixl_fmnvar.h> 41 42 #ifdef FMN_DEBUG 43 # define DPRINTF(x) do { printf x ; } while(0) 44 #else 45 # define DPRINTF(x) 46 #endif 47 48 #ifdef DIAGNOSTIC 49 # define DIAG_PRF(x) do { printf x ; } while(0) 50 #else 51 # define DIAG_PRF(x) 52 #endif 53 54 55 56 /* 57 * index CPU-dependent table by (global) bucket ID to obtain logical Station ID 58 * see Table 12.1 in the XLS PRM 59 */ 60 /* use this table for XLS6xx, XLS4xx */ 61 static const int station_xls_4xx[] = { 62 [0 ... 7] = RMIXLS_FMN_STID_CORE0, 63 [8 ... 15] = RMIXLS_FMN_STID_CORE1, 64 [16 ... 23] = RMIXLS_FMN_STID_CORE2, 65 [24 ... 31] = RMIXLS_FMN_STID_CORE3, 66 [32 ... 63] = RMIXLS_FMN_STID_RESERVED, 67 [64 ... 71] = RMIXLS_FMN_STID_PCIE, 68 [72 ... 79] = RMIXLS_FMN_STID_RESERVED, 69 [80 ... 87] = RMIXLS_FMN_STID_GMAC_Q1, 70 [88 ... 95] = RMIXLS_FMN_STID_RESERVED, 71 [96 ... 103] = RMIXLS_FMN_STID_GMAC_Q0, 72 [104 ... 107] = RMIXLS_FMN_STID_DMA, 73 [108 ... 109] = RMIXLS_FMN_STID_CDE, 74 [110 ... 119] = RMIXLS_FMN_STID_RESERVED, 75 [120 ... 127] = RMIXLS_FMN_STID_SAE, 76 }; 77 78 /* use this table for XLS408Lite, XLS404Lite */ 79 static const int station_xls_4xx_lite[] = { 80 [0 ... 7] = RMIXLS_FMN_STID_CORE0, 81 [8 ... 15] = RMIXLS_FMN_STID_CORE1, 82 [16 ... 23] = RMIXLS_FMN_STID_CORE2, 83 [24 ... 31] = RMIXLS_FMN_STID_CORE3, 84 [32 ... 79] = RMIXLS_FMN_STID_RESERVED, 85 [80 ... 87] = RMIXLS_FMN_STID_GMAC_Q1, 86 [88 ... 95] = RMIXLS_FMN_STID_RESERVED, 87 [96 ... 103] = RMIXLS_FMN_STID_GMAC_Q0, 88 [104 ... 107] = RMIXLS_FMN_STID_DMA, 89 [108 ... 109] = RMIXLS_FMN_STID_CDE, 90 [110 ... 115] = RMIXLS_FMN_STID_RESERVED, 91 [116 ... 119] = RMIXLS_FMN_STID_PCIE, 92 [120 ... 127] = RMIXLS_FMN_STID_SAE, 93 }; 94 95 /* use this table for XLS2xx */ 96 static const int station_xls_2xx[] = { 97 [0 ... 7] = RMIXLS_FMN_STID_CORE0, 98 [8 ... 15] = RMIXLS_FMN_STID_CORE1, 99 [16 ... 23] = RMIXLS_FMN_STID_CORE2, 100 [24 ... 31] = RMIXLS_FMN_STID_CORE3, 101 [32 ... 63] = RMIXLS_FMN_STID_RESERVED, 102 [64 ... 71] = RMIXLS_FMN_STID_PCIE, 103 [72 ... 95] = RMIXLS_FMN_STID_RESERVED, 104 [96 ... 103] = RMIXLS_FMN_STID_GMAC_Q0, 105 [104 ... 107] = RMIXLS_FMN_STID_DMA, 106 [108 ... 119] = RMIXLS_FMN_STID_RESERVED, 107 [120 ... 127] = RMIXLS_FMN_STID_SAE, 108 }; 109 110 /* use this table for XLS1xx */ 111 static const int station_xls_1xx[] = { 112 [0 ... 7] = RMIXLS_FMN_STID_CORE0, 113 [8 ... 15] = RMIXLS_FMN_STID_CORE1, 114 [16 ... 23] = RMIXLS_FMN_STID_CORE2, 115 [24 ... 31] = RMIXLS_FMN_STID_CORE3, 116 [32 ... 63] = RMIXLS_FMN_STID_RESERVED, 117 [64 ... 71] = RMIXLS_FMN_STID_PCIE, 118 [72 ... 95] = RMIXLS_FMN_STID_RESERVED, 119 [96 ... 101] = RMIXLS_FMN_STID_GMAC_Q0, 120 [102 ... 103] = RMIXLS_FMN_STID_RESERVED, 121 [104 ... 107] = RMIXLS_FMN_STID_DMA, 122 [108 ... 119] = RMIXLS_FMN_STID_RESERVED, 123 [120 ... 127] = RMIXLS_FMN_STID_SAE, 124 }; 125 126 /* use this table for XLRxxx */ 127 static const int station_xlr_xxx[] = { 128 [0 ... 7] = RMIXLR_FMN_STID_CORE0, 129 [8 ... 15] = RMIXLR_FMN_STID_CORE1, 130 [16 ... 23] = RMIXLR_FMN_STID_CORE2, 131 [24 ... 31] = RMIXLR_FMN_STID_CORE3, 132 [32 ... 39] = RMIXLR_FMN_STID_CORE4, 133 [40 ... 47] = RMIXLR_FMN_STID_CORE5, 134 [48 ... 55] = RMIXLR_FMN_STID_CORE6, 135 [56 ... 63] = RMIXLR_FMN_STID_CORE7, 136 [64 ... 79] = RMIXLR_FMN_STID_TXRX_0, 137 [80 ... 95] = RMIXLR_FMN_STID_TXRX_1, 138 [96 ... 103] = RMIXLR_FMN_STID_RGMII, 139 [104 ... 107] = RMIXLR_FMN_STID_DMA, 140 [108 ... 111] = RMIXLR_FMN_STID_RESERVED, 141 [112 ... 113] = RMIXLR_FMN_STID_FREE_0, 142 [114 ... 115] = RMIXLR_FMN_STID_FREE_0, 143 [116 ... 119] = RMIXLR_FMN_STID_RESERVED, 144 [120 ... 127] = RMIXLR_FMN_STID_SAE, 145 }; 146 147 typedef struct fmn_station_info { 148 const char *si_name; 149 const u_int si_buckets_max; 150 const u_int si_stid_first; 151 const u_int si_stid_last; 152 const u_int si_bucket_size_dflt; 153 const u_int si_credits_min; 154 const u_int si_regbase; 155 } fmn_station_info_t; 156 157 /* use this table for XLS6xx, XLS4xx */ 158 static const fmn_station_info_t station_info_xls_4xx[RMIXLS_FMN_NSTID] = { 159 [RMIXLS_FMN_STID_CORE0] = { "core0", 8, 0, 7, 32, 4, 0 }, 160 [RMIXLS_FMN_STID_CORE1] = { "core1", 8, 8, 15, 32, 4, 0 }, 161 [RMIXLS_FMN_STID_CORE2] = { "core2", 8, 16, 23, 32, 4, 0 }, 162 [RMIXLS_FMN_STID_CORE3] = { "core3", 8, 24, 31, 32, 4, 0 }, 163 [RMIXLS_FMN_STID_GMAC_Q0] = { "gmac_q0", 3, 80, 87, 32, 0, RMIXL_IO_DEV_GMAC_0 }, 164 [RMIXLS_FMN_STID_GMAC_Q1] = { "gmac_q1", 3, 96, 103, 32, 0, RMIXL_IO_DEV_GMAC_4 }, 165 [RMIXLS_FMN_STID_DMA] = { "dma", 4, 104, 107, 64, 0, RMIXL_IO_DEV_DMA }, 166 [RMIXLS_FMN_STID_CDE] = { "cde", 4, 108, 109, 128, 0, RMIXL_IO_DEV_CDE }, 167 [RMIXLS_FMN_STID_PCIE] = { "pcie", 8, 64, 71, 32, 0, RMIXL_IO_DEV_PCIE_BE }, 168 [RMIXLS_FMN_STID_SAE] = { "sae", 2, 120, 121, 128, 0, RMIXL_IO_DEV_SAE }, 169 }; 170 171 /* use this table for XLS4xxLite */ 172 static const fmn_station_info_t station_info_xls_4xx_lite[RMIXLS_FMN_NSTID] = { 173 [RMIXLS_FMN_STID_CORE0] = { "core0", 8, 0, 7, 32, 4, 0 }, 174 [RMIXLS_FMN_STID_CORE1] = { "core1", 8, 8, 15, 32, 4, 0 }, 175 [RMIXLS_FMN_STID_CORE2] = { "core2", 8, 16, 23, 32, 4, 0 }, 176 [RMIXLS_FMN_STID_CORE3] = { "core3", 8, 24, 31, 32, 4, 0 }, 177 [RMIXLS_FMN_STID_GMAC_Q0] = { "gmac_q0", 3, 80, 87, 32, 0, RMIXL_IO_DEV_GMAC_0 }, 178 [RMIXLS_FMN_STID_GMAC_Q1] = { "gmac_q1", 3, 96, 103, 32, 0, RMIXL_IO_DEV_GMAC_4 }, 179 [RMIXLS_FMN_STID_DMA] = { "dma", 4, 104, 107, 64, 0, RMIXL_IO_DEV_DMA }, 180 [RMIXLS_FMN_STID_CDE] = { "cde", 4, 108, 109, 128, 0, RMIXL_IO_DEV_CDE }, 181 [RMIXLS_FMN_STID_PCIE] = { "pcie", 4, 116, 119, 64, 0, RMIXL_IO_DEV_PCIE_BE }, 182 [RMIXLS_FMN_STID_SAE] = { "sae", 2, 120, 121, 128, 0, RMIXL_IO_DEV_SAE }, 183 }; 184 185 /* use this table for XLS2xx */ 186 static const fmn_station_info_t station_info_xls_2xx[RMIXLS_FMN_NSTID] = { 187 [RMIXLS_FMN_STID_CORE0] = { "core0", 8, 0, 7, 32, 4, 0 }, 188 [RMIXLS_FMN_STID_CORE1] = { "core1", 8, 8, 15, 32, 4, 0 }, 189 [RMIXLS_FMN_STID_CORE2] = { "core2", 8, 16, 23, 32, 4, 0 }, 190 [RMIXLS_FMN_STID_CORE3] = { "core3", 8, 24, 31, 32, 4, 0 }, 191 [RMIXLS_FMN_STID_GMAC_Q0] = { "gmac_q0", 3, 96, 103, 32, 0, RMIXL_IO_DEV_GMAC_0 }, 192 [RMIXLS_FMN_STID_DMA] = { "dma", 4, 104, 107, 64, 0, RMIXL_IO_DEV_DMA }, 193 [RMIXLS_FMN_STID_PCIE] = { "pcie", 8, 64, 71, 32, 0, RMIXL_IO_DEV_PCIE_BE }, 194 [RMIXLS_FMN_STID_SAE] = { "sae", 2, 120, 121, 128, 0, RMIXL_IO_DEV_SAE }, 195 }; 196 197 /* use this table for XLS1xx */ 198 static const fmn_station_info_t station_info_xls_1xx[RMIXLS_FMN_NSTID] = { 199 [RMIXLS_FMN_STID_CORE0] = { "core0", 8, 0, 7, 32, 4, 0 }, 200 [RMIXLS_FMN_STID_CORE1] = { "core1", 8, 8, 15, 32, 4, 0 }, 201 [RMIXLS_FMN_STID_CORE2] = { "core2", 8, 16, 23, 32, 4, 0 }, 202 [RMIXLS_FMN_STID_CORE3] = { "core3", 8, 24, 31, 32, 4, 0 }, 203 [RMIXLS_FMN_STID_GMAC_Q0] = { "gmac_q0", 3, 96, 101, 32, 0, RMIXL_IO_DEV_GMAC_0 }, 204 [RMIXLS_FMN_STID_DMA] = { "dma", 4, 104, 107, 64, 0, RMIXL_IO_DEV_PCIE_BE }, 205 [RMIXLS_FMN_STID_PCIE] = { "pcie", 4, 64, 67, 32, 0, RMIXL_IO_DEV_PCIE_BE }, 206 [RMIXLS_FMN_STID_SAE] = { "sae", 2, 120, 121, 128, 0, RMIXL_IO_DEV_SAE }, 207 }; 208 209 /* 210 * use this table for XLRxxx 211 * caution: 212 * - the XGMII/SPI4 stations si_regbase are 'special' 213 * - the RGMII station si_regbase is 'special' 214 */ 215 static const fmn_station_info_t station_info_xlr_xxx[RMIXLR_FMN_NSTID] = { 216 [RMIXLR_FMN_STID_CORE0] = { "core0", 8, 0, 7, 32, 4, 0 }, 217 [RMIXLR_FMN_STID_CORE1] = { "core1", 8, 8, 15, 32, 4, 0 }, 218 [RMIXLR_FMN_STID_CORE2] = { "core2", 8, 16, 23, 32, 4, 0 }, 219 [RMIXLR_FMN_STID_CORE3] = { "core3", 8, 24, 31, 32, 4, 0 }, 220 [RMIXLR_FMN_STID_CORE4] = { "core4", 8, 32, 39, 32, 4, 0 }, 221 [RMIXLR_FMN_STID_CORE5] = { "core5", 8, 40, 47, 32, 4, 0 }, 222 [RMIXLR_FMN_STID_CORE6] = { "core6", 8, 48, 55, 32, 4, 0 }, 223 [RMIXLR_FMN_STID_CORE7] = { "core7", 8, 56, 63, 32, 4, 0 }, 224 [RMIXLR_FMN_STID_TXRX_0] = { "txrx0", 1, 64, 79, 16, 0, RMIXL_IO_DEV_XGMAC_A }, 225 [RMIXLR_FMN_STID_TXRX_1] = { "txrx1", 1, 80, 95, 16, 0, RMIXL_IO_DEV_XGMAC_B }, 226 [RMIXLR_FMN_STID_RGMII] = { "rgmii", 8, 96, 103, 32, 0, RMIXL_IO_DEV_GMAC_A }, 227 [RMIXLR_FMN_STID_DMA] = { "dma", 4, 104, 107, 64, 0, RMIXL_IO_DEV_DMA }, 228 [RMIXLR_FMN_STID_FREE_0] = { "free0", 2, 112, 113, 128, 0, RMIXL_IO_DEV_XGMAC_A }, 229 [RMIXLR_FMN_STID_FREE_1] = { "free1", 2, 114, 115, 128, 0, RMIXL_IO_DEV_XGMAC_B }, 230 [RMIXLR_FMN_STID_SAE] = { "sae", 5, 120, 124, 32, 0, RMIXL_IO_DEV_SAE }, 231 }; 232 233 234 typedef struct fmn_intrhand { 235 int (*ih_func)(void *, rmixl_fmn_rxmsg_t *); 236 void *ih_arg; 237 struct evcnt ih_count; 238 } fmn_intrhand_t; 239 240 /* 241 * per-core FMN structure 242 */ 243 typedef struct fmn { 244 kmutex_t *fmn_lock; 245 u_int fmn_core; 246 u_int fmn_thread; 247 u_int fmn_nstid; 248 const int *fmn_stidtab; 249 const fmn_station_info_t *fmn_stinfo; 250 void *fmn_ih; 251 fmn_intrhand_t fmn_intrhand[RMIXL_FMN_NSTID]; 252 } fmn_t; 253 254 static fmn_t fmn_store[1 << 10]; /* index by cpuid) *//* XXX assumes 1 node */ 255 #define NFMN (sizeof(fmn_store) / sizeof(fmn_store[0])) 256 257 static fmn_t * 258 fmn_lookup(cpuid_t cpuid) 259 { 260 KASSERT(cpuid < (cpuid_t)NFMN); 261 return &fmn_store[cpuid]; 262 } 263 264 static void rmixl_fmn_init_core_xlr(fmn_t *); 265 static void rmixl_fmn_init_core_xls(fmn_t *); 266 static void rmixl_fmn_config_noncore(fmn_t *); 267 static void rmixl_fmn_config_core(fmn_t *); 268 #ifdef NOTYET 269 static int rmixl_fmn_intr_dispatch(void *); 270 #endif /* NOTYET */ 271 static int rmixl_fmn_msg_recv_subr(u_int, rmixl_fmn_rxmsg_t *); 272 273 #ifdef FMN_DEBUG 274 void rmixl_fmn_cp2_dump(void); 275 void rmixl_fmn_cc_dump(void); 276 #endif 277 278 /* 279 * macros used because mtc2, mfc2, dmtc2, dmfc2 instructions 280 * must use literal values for rd and sel operands 281 * so let the compiler sort it out 282 */ 283 284 /* 285 * write v to all 8 SELs for given RD 286 */ 287 #define FMN_CP2_4SEL_READ(rd, sel, vp) \ 288 do { \ 289 uint32_t *rp = vp; \ 290 RMIXL_MFC2(rd, sel, rp[0]); \ 291 RMIXL_MFC2(rd, sel+1, rp[1]); \ 292 RMIXL_MFC2(rd, sel+2, rp[2]); \ 293 RMIXL_MFC2(rd, sel+3, rp[3]); \ 294 } while (0) 295 296 /* 297 * write v to all 8 SELs for given RD 298 */ 299 #define FMN_CP2_4SEL_WRITE(rd, sel, v) \ 300 do { \ 301 RMIXL_MTC2(rd, sel, v); \ 302 RMIXL_MTC2(rd, sel+1, v); \ 303 RMIXL_MTC2(rd, sel+2, v); \ 304 RMIXL_MTC2(rd, sel+3, v); \ 305 } while (0) 306 307 #define FMN_CP2_8SEL_WRITE(rd, v) \ 308 do { \ 309 RMIXL_MTC2(rd, 0, v); \ 310 RMIXL_MTC2(rd, 1, v); \ 311 RMIXL_MTC2(rd, 2, v); \ 312 RMIXL_MTC2(rd, 3, v); \ 313 RMIXL_MTC2(rd, 4, v); \ 314 RMIXL_MTC2(rd, 5, v); \ 315 RMIXL_MTC2(rd, 6, v); \ 316 RMIXL_MTC2(rd, 7, v); \ 317 } while (0) 318 319 320 #define FMN_CP2_SEL_CASE_READ(rd, sel, v) \ 321 case sel: \ 322 RMIXL_MFC2(rd, sel, v); \ 323 break 324 #define FMN_CP2_SEL_CASE_WRITE(rd, sel, v) \ 325 case sel: \ 326 RMIXL_MTC2(rd, sel, v); \ 327 break 328 /* 329 * read/write a single arbitrary sel for the given rd 330 */ 331 #define FMN_CP2_SEL_SWITCH_RW(rw, rd, sel, val) \ 332 do { \ 333 switch (sel) { \ 334 FMN_CP2_SEL_CASE_ ## rw(rd, 0, val); \ 335 FMN_CP2_SEL_CASE_ ## rw(rd, 1, val); \ 336 FMN_CP2_SEL_CASE_ ## rw(rd, 2, val); \ 337 FMN_CP2_SEL_CASE_ ## rw(rd, 3, val); \ 338 FMN_CP2_SEL_CASE_ ## rw(rd, 4, val); \ 339 FMN_CP2_SEL_CASE_ ## rw(rd, 5, val); \ 340 FMN_CP2_SEL_CASE_ ## rw(rd, 6, val); \ 341 FMN_CP2_SEL_CASE_ ## rw(rd, 7, val); \ 342 default: \ 343 panic("%s:%d: bad sel %d\n", \ 344 __func__, __LINE__, sel); \ 345 } \ 346 } while (0) 347 348 #define FMN_CP2_RD_CASE_RW(rw, rd, sel, val) \ 349 case rd: \ 350 FMN_CP2_SEL_SWITCH_RW(rw, rd, sel, val); \ 351 break 352 /* 353 * read/write a single arbitrary Credit Counter at (rd, sel) 354 * eg: 355 * FMN_CP2_RD_SWITCH_RW(READ, 16, 2, val) 356 * FMN_CP2_RD_SWITCH_RW(WRITE, 18, 0, val) 357 */ 358 #define FMN_CP2_RD_SWITCH_RW(rw, rd, sel, val) \ 359 do { \ 360 switch(rd) { \ 361 FMN_CP2_RD_CASE_RW(rw, 0, sel, val); \ 362 FMN_CP2_RD_CASE_RW(rw, 1, sel, val); \ 363 FMN_CP2_RD_CASE_RW(rw, 2, sel, val); \ 364 FMN_CP2_RD_CASE_RW(rw, 3, sel, val); \ 365 FMN_CP2_RD_CASE_RW(rw, 4, sel, val); \ 366 FMN_CP2_RD_CASE_RW(rw, 5, sel, val); \ 367 FMN_CP2_RD_CASE_RW(rw, 6, sel, val); \ 368 FMN_CP2_RD_CASE_RW(rw, 7, sel, val); \ 369 FMN_CP2_RD_CASE_RW(rw, 8, sel, val); \ 370 FMN_CP2_RD_CASE_RW(rw, 9, sel, val); \ 371 FMN_CP2_RD_CASE_RW(rw, 10, sel, val); \ 372 FMN_CP2_RD_CASE_RW(rw, 11, sel, val); \ 373 FMN_CP2_RD_CASE_RW(rw, 12, sel, val); \ 374 FMN_CP2_RD_CASE_RW(rw, 13, sel, val); \ 375 FMN_CP2_RD_CASE_RW(rw, 14, sel, val); \ 376 FMN_CP2_RD_CASE_RW(rw, 15, sel, val); \ 377 FMN_CP2_RD_CASE_RW(rw, 16, sel, val); \ 378 FMN_CP2_RD_CASE_RW(rw, 17, sel, val); \ 379 FMN_CP2_RD_CASE_RW(rw, 18, sel, val); \ 380 FMN_CP2_RD_CASE_RW(rw, 19, sel, val); \ 381 FMN_CP2_RD_CASE_RW(rw, 20, sel, val); \ 382 FMN_CP2_RD_CASE_RW(rw, 21, sel, val); \ 383 FMN_CP2_RD_CASE_RW(rw, 22, sel, val); \ 384 FMN_CP2_RD_CASE_RW(rw, 23, sel, val); \ 385 FMN_CP2_RD_CASE_RW(rw, 24, sel, val); \ 386 FMN_CP2_RD_CASE_RW(rw, 25, sel, val); \ 387 FMN_CP2_RD_CASE_RW(rw, 26, sel, val); \ 388 FMN_CP2_RD_CASE_RW(rw, 27, sel, val); \ 389 FMN_CP2_RD_CASE_RW(rw, 28, sel, val); \ 390 FMN_CP2_RD_CASE_RW(rw, 29, sel, val); \ 391 FMN_CP2_RD_CASE_RW(rw, 30, sel, val); \ 392 FMN_CP2_RD_CASE_RW(rw, 31, sel, val); \ 393 default: \ 394 panic("%s:%d: bad regno %d\n", \ 395 __func__, __LINE__, rd); \ 396 } \ 397 } while (0) 398 399 400 void 401 rmixl_fmn_init(void) 402 { 403 int cpu; 404 fmn_t *fmnp; 405 static bool once=false; 406 407 KASSERT(cpu_number() == 0); 408 fmnp = fmn_lookup(cpu_number()); 409 410 if (once == true) 411 panic("%s: call only once!", __func__); 412 once = true; 413 414 for (cpu=0; cpu < NFMN; cpu++) { 415 fmnp[cpu].fmn_core = RMIXL_CPU_CORE(cpu); 416 fmnp[cpu].fmn_thread = RMIXL_CPU_THREAD(cpu); 417 } 418 419 rmixl_fmn_init_core(); /* for initial boot cpu (#0) */ 420 rmixl_fmn_config_noncore(fmnp); /* boot cpu initializes noncore */ 421 } 422 423 /* 424 * link to TX station ID table for RMI XLR type chip 425 */ 426 static void 427 rmixl_fmn_init_core_xlr(fmn_t *fmnp) 428 { 429 fmnp->fmn_nstid = RMIXLR_FMN_NSTID; 430 fmnp->fmn_stidtab = station_xlr_xxx; 431 fmnp->fmn_stinfo = station_info_xlr_xxx; 432 } 433 434 /* 435 * link to TX station ID table for RMI XLS type chip 436 */ 437 static void 438 rmixl_fmn_init_core_xls(fmn_t *fmnp) 439 { 440 const fmn_station_info_t *info = NULL; 441 const int *tab = NULL; 442 443 switch (MIPS_PRID_IMPL(mips_options.mips_cpu_id)) { 444 case MIPS_XLS104: 445 case MIPS_XLS108: 446 tab = station_xls_1xx; 447 info = station_info_xls_1xx; 448 break; 449 case MIPS_XLS204: 450 case MIPS_XLS208: 451 tab = station_xls_2xx; 452 info = station_info_xls_2xx; 453 break; 454 case MIPS_XLS404: 455 case MIPS_XLS408: 456 case MIPS_XLS416: 457 case MIPS_XLS608: 458 case MIPS_XLS616: 459 tab = station_xls_4xx; 460 info = station_info_xls_4xx; 461 break; 462 case MIPS_XLS404LITE: 463 case MIPS_XLS408LITE: 464 tab = station_xls_4xx_lite; 465 info = station_info_xls_4xx_lite; 466 break; 467 default: 468 panic("%s: unknown PRID IMPL %#x\n", __func__, 469 MIPS_PRID_IMPL(mips_options.mips_cpu_id)); 470 } 471 472 fmnp->fmn_nstid = RMIXLS_FMN_NSTID; 473 fmnp->fmn_stidtab = tab; 474 fmnp->fmn_stinfo = info; 475 } 476 477 void 478 rmixl_fmn_init_core(void) 479 { 480 fmn_t *fmnp; 481 kmutex_t *lk; 482 483 fmnp = fmn_lookup(cpu_number()); 484 KASSERT(fmnp != NULL); 485 KASSERT(fmnp->fmn_core == RMIXL_CPU_CORE(cpu_number())); 486 KASSERT(fmnp->fmn_thread == RMIXL_CPU_THREAD(cpu_number())); 487 488 lk = mutex_obj_alloc(MUTEX_DEFAULT, RMIXL_FMN_INTR_IPL); 489 if (lk == NULL) 490 panic("%s: mutex_obj_alloc failed", __func__); 491 fmnp->fmn_lock = lk; 492 493 mutex_enter(fmnp->fmn_lock); 494 495 /* 496 * do chip-dependent per-core FMN initialization 497 */ 498 switch(cpu_rmixl_chip_type(mips_options.mips_cpu)) { 499 case CIDFL_RMI_TYPE_XLR: 500 rmixl_fmn_init_core_xlr(fmnp); 501 break; 502 case CIDFL_RMI_TYPE_XLS: 503 rmixl_fmn_init_core_xls(fmnp); 504 break; 505 case CIDFL_RMI_TYPE_XLP: 506 panic("%s: RMI XLP not yet supported", __func__); 507 default: 508 panic("%s: RMI chip type %#x unknown", __func__, 509 cpu_rmixl_chip_type(mips_options.mips_cpu)); 510 } 511 512 /* 513 * thread #0 for each core owns 'global' CP2 regs 514 */ 515 if (fmnp->fmn_thread == 0) 516 rmixl_fmn_config_core(fmnp); 517 518 mutex_exit(fmnp->fmn_lock); 519 } 520 521 /* 522 * rmixl_fmn_config_noncore 523 * 524 * initialize bucket sizes and (minimum) credits for non-core stations to ZERO 525 * configured through memory write operations instead of CP2 526 */ 527 static void 528 rmixl_fmn_config_noncore(fmn_t *fmnp) 529 { 530 for (u_int sid=0; sid < fmnp->fmn_nstid; sid++) { 531 u_int regoff = fmnp->fmn_stinfo[sid].si_regbase; 532 if (regoff != 0) { 533 u_int buckets_max = fmnp->fmn_stinfo[sid].si_buckets_max; 534 regoff += RMIXL_FMN_BS_FIRST; 535 for (u_int bucket=0; bucket < buckets_max; bucket++) { 536 RMIXL_IOREG_WRITE(regoff, 0); 537 regoff += sizeof(uint32_t); 538 } 539 } 540 } 541 } 542 543 /* 544 * rmixl_fmn_config_core 545 * 546 * - assumes fmn_mutex is owned 547 * - configure FMN 548 * - initialize bucket sizes and (minimum) credits for a core 549 */ 550 static void 551 rmixl_fmn_config_core(fmn_t *fmnp) 552 { 553 const fmn_station_info_t *info = fmnp->fmn_stinfo; 554 uint32_t sts1; 555 uint32_t cfg; 556 uint32_t cp0_status; 557 558 KASSERT(mutex_owned(fmnp->fmn_lock) != 0); 559 KASSERT(fmnp->fmn_thread == 0); 560 cp0_status = rmixl_cp2_enable(); 561 562 /* check/clear any pre-existing status1 error(s) */ 563 RMIXL_MFC2(RMIXL_COP_2_MSG_STS, 1, sts1); 564 if ((sts1 & RMIXL_MSG_STS1_ERRS) != 0) 565 RMIXL_MTC2(RMIXL_COP_2_MSG_STS, 1, sts1); 566 567 /* set up MsgConfig reg */ 568 cfg = ((1 << RMIXL_MSG_CFG0_WMSHIFT) /* watermark */ 569 | (RMIXL_INTRVEC_FMN << RMIXL_MSG_CFG0_IV_SHIFT) /* irq */ 570 | (1 << RMIXL_MSG_CFG0_ITM_SHIFT) /* thread mask */ 571 | RMIXL_MSG_CFG0_WIE /* watermark intr enb */ 572 | RMIXL_MSG_CFG0_EIE); /* rx not empty intr enb */ 573 RMIXL_DMTC2(RMIXL_COP_2_MSG_CFG, 0, cfg); 574 575 /* disable trace mode, credit overrun intr, messaging errors intr */ 576 RMIXL_DMTC2(RMIXL_COP_2_MSG_CFG, 0, 0); 577 578 /* XXX using 4 buckets per core */ 579 KASSERT(4 <= info->si_buckets_max); 580 581 /* 582 * initialize default sizes for core buckets 583 * zero sizes for unused buckets 584 */ 585 KASSERT(info->si_buckets_max == 8); 586 uint32_t sz = info->si_bucket_size_dflt; 587 KASSERT((sz & ~RMIXL_MSG_BSZ_SIZE) == 0); 588 RMIXL_MTC2(RMIXL_COP_2_MSG_BSZ, 0, sz); 589 RMIXL_MTC2(RMIXL_COP_2_MSG_BSZ, 1, sz); 590 RMIXL_MTC2(RMIXL_COP_2_MSG_BSZ, 2, sz); 591 RMIXL_MTC2(RMIXL_COP_2_MSG_BSZ, 3, sz); 592 RMIXL_MTC2(RMIXL_COP_2_MSG_BSZ, 4, 0); 593 RMIXL_MTC2(RMIXL_COP_2_MSG_BSZ, 5, 0); 594 RMIXL_MTC2(RMIXL_COP_2_MSG_BSZ, 6, 0); 595 RMIXL_MTC2(RMIXL_COP_2_MSG_BSZ, 7, 0); 596 597 /* 598 * configure minimum credits for each core, 4 buckets 599 * zero all unused credit counters for this core 600 */ 601 uint32_t cr = info->si_credits_min; 602 603 FMN_CP2_4SEL_WRITE(RMIXL_COP_2_CREDITS, 0, cr); 604 FMN_CP2_4SEL_WRITE(RMIXL_COP_2_CREDITS, 4, 0); 605 FMN_CP2_4SEL_WRITE(RMIXL_COP_2_CREDITS+1, 0, cr); 606 FMN_CP2_4SEL_WRITE(RMIXL_COP_2_CREDITS+1, 4, 0); 607 FMN_CP2_4SEL_WRITE(RMIXL_COP_2_CREDITS+2, 0, cr); 608 FMN_CP2_4SEL_WRITE(RMIXL_COP_2_CREDITS+2, 4, 0); 609 FMN_CP2_4SEL_WRITE(RMIXL_COP_2_CREDITS+3, 0, cr); 610 FMN_CP2_4SEL_WRITE(RMIXL_COP_2_CREDITS+3, 4, 0); 611 612 FMN_CP2_8SEL_WRITE(RMIXL_COP_2_CREDITS+4, 0); 613 FMN_CP2_8SEL_WRITE(RMIXL_COP_2_CREDITS+5, 0); 614 FMN_CP2_8SEL_WRITE(RMIXL_COP_2_CREDITS+6, 0); 615 FMN_CP2_8SEL_WRITE(RMIXL_COP_2_CREDITS+7, 0); 616 FMN_CP2_8SEL_WRITE(RMIXL_COP_2_CREDITS+8, 0); 617 FMN_CP2_8SEL_WRITE(RMIXL_COP_2_CREDITS+9, 0); 618 FMN_CP2_8SEL_WRITE(RMIXL_COP_2_CREDITS+10, 0); 619 FMN_CP2_8SEL_WRITE(RMIXL_COP_2_CREDITS+11, 0); 620 FMN_CP2_8SEL_WRITE(RMIXL_COP_2_CREDITS+12, 0); 621 FMN_CP2_8SEL_WRITE(RMIXL_COP_2_CREDITS+13, 0); 622 FMN_CP2_8SEL_WRITE(RMIXL_COP_2_CREDITS+14, 0); 623 FMN_CP2_8SEL_WRITE(RMIXL_COP_2_CREDITS+15, 0); 624 625 RMIXL_MFC2(RMIXL_COP_2_MSG_STS, 1, sts1); 626 KASSERT((sts1 & RMIXL_MSG_STS1_ERRS) == 0); 627 628 rmixl_cp2_restore(cp0_status); 629 } 630 631 void 632 rmixl_fmn_init_cpu_intr(void) 633 { 634 fmn_t *fmnp; 635 636 fmnp = fmn_lookup(cpu_number()); 637 mutex_enter(fmnp->fmn_lock); 638 639 for (int i=0; i < fmnp->fmn_nstid; i++) 640 evcnt_attach_dynamic(&fmnp->fmn_intrhand[i].ih_count, 641 EVCNT_TYPE_INTR, NULL, "rmixl_fmn", fmnp->fmn_stinfo[i].si_name); 642 643 #ifdef NOTYET 644 /* 645 * establish dispatcher for FMN interrupt 646 */ 647 extern kmutex_t rmixl_intr_lock; 648 void *ih; 649 650 mutex_enter(&rmixl_intr_lock); 651 ih = rmixl_vec_establish(RMIXL_INTRVEC_FMN, -1, RMIXL_FMN_INTR_IPL, 652 rmixl_fmn_intr_dispatch, fmnp, "fmn"); 653 if (ih == NULL) 654 panic("%s: rmixl_vec_establish failed", __func__); 655 mutex_exit(&rmixl_intr_lock); 656 fmnp->fmn_ih = ih; 657 #endif 658 659 mutex_exit(fmnp->fmn_lock); 660 } 661 662 void * 663 rmixl_fmn_intr_establish(int txstid, int (*func)(void *, rmixl_fmn_rxmsg_t *), void *arg) 664 { 665 fmn_t *fmnp; 666 fmn_intrhand_t *ih; 667 668 fmnp = fmn_lookup(cpu_number()); 669 670 mutex_enter(fmnp->fmn_lock); 671 672 ih = &fmnp->fmn_intrhand[txstid]; 673 674 if (ih->ih_func != NULL) { 675 #ifdef DEBUG 676 panic("%s: intrhand[%d] busy", __func__, txstid); 677 #endif 678 ih = NULL; 679 } else { 680 ih->ih_func = func; 681 ih->ih_arg = arg; 682 } 683 684 mutex_exit(fmnp->fmn_lock); 685 686 return ih; 687 } 688 689 void 690 rmixl_fmn_intr_disestablish(void *cookie) 691 { 692 fmn_t *fmnp; 693 fmn_intrhand_t *ih = cookie; 694 695 fmnp = fmn_lookup(cpu_number()); 696 mutex_enter(fmnp->fmn_lock); 697 698 if (ih->ih_func != NULL) { 699 ih->ih_func = NULL; 700 ih->ih_arg = NULL; 701 } 702 #ifdef DEBUG 703 else { 704 panic("%s: intrhand[%ld] not in use", 705 __func__, ih - &fmnp->fmn_intrhand[0]); 706 } 707 #endif 708 709 mutex_exit(fmnp->fmn_lock); 710 } 711 712 void 713 rmixl_fmn_intr_poll(u_int bucket, rmixl_fmn_rxmsg_t *rxmsg) 714 { 715 uint32_t bit = 1 << bucket; 716 uint32_t cp0_status; 717 718 KASSERT(bucket < 8); 719 720 cp0_status = rmixl_cp2_enable(); 721 722 for(;;) { 723 rmixl_fmn_msgwait(bit); 724 if (rmixl_fmn_msg_recv(bucket, rxmsg) == 0) 725 break; 726 DELAY(10); /* XXX */ 727 } 728 729 rmixl_cp2_restore(cp0_status); 730 } 731 732 #ifdef NOTYET 733 static int 734 rmixl_fmn_intr_dispatch(void *arg) 735 { 736 fmn_t *fmnp = arg; 737 uint32_t msg_status; 738 uint32_t cp0_status; 739 uint32_t rfbne; 740 int txstid; 741 int rv = 0; 742 743 mutex_enter(fmnp->fmn_lock); 744 cp0_status = rmixl_cp2_enable(); 745 746 RMIXL_MFC2(RMIXL_COP_2_MSG_STS, 0, msg_status); 747 rfbne = (~msg_status) >> RMIXL_MSG_STS0_RFBE_SHIFT; 748 749 if (rfbne != 0) { 750 DPRINTF(("%s: rfbne %#x\n", __func__, rfbne)); 751 for (u_int bucket=0; bucket < 8; bucket++) { 752 rmixl_fmn_rxmsg_t rxmsg; 753 fmn_intrhand_t *ih; 754 755 if ((rfbne & (1 << bucket)) == 0) 756 continue; 757 if (rmixl_fmn_msg_recv_subr(bucket, &rxmsg) != 0) 758 continue; 759 rv = 1; 760 txstid = fmnp->fmn_stidtab[rxmsg.rxsid]; 761 ih = &fmnp->fmn_intrhand[txstid]; 762 if (ih->ih_func != NULL) 763 if ((ih->ih_func)(ih->ih_arg, &rxmsg) != 0) 764 ih->ih_count.ev_count++; 765 } 766 767 } 768 rmixl_cp2_restore(cp0_status); 769 mutex_exit(fmnp->fmn_lock); 770 771 return rv; 772 } 773 #endif /* NOTYET */ 774 775 int 776 rmixl_fmn_msg_send(u_int size, u_int code, u_int dest_id, rmixl_fmn_msg_t *msg) 777 { 778 fmn_t *fmnp; 779 uint32_t cp0_status; 780 uint32_t msg_status; 781 uint32_t msg_status1; 782 uint32_t desc; 783 int rv = 0; 784 785 KASSERT((size >= 1) && size <= 4); 786 KASSERT(code <= 0xff); 787 KASSERT(dest_id <= 0xff); 788 789 fmnp = fmn_lookup(cpu_number()); 790 mutex_enter(fmnp->fmn_lock); 791 cp0_status = rmixl_cp2_enable(); 792 793 switch(size) { 794 case 1: 795 RMIXL_DMTC2(RMIXL_COP_2_TXBUF, 0, msg->data[0]); 796 break; 797 case 2: 798 RMIXL_DMTC2(RMIXL_COP_2_TXBUF, 0, msg->data[0]); 799 RMIXL_DMTC2(RMIXL_COP_2_TXBUF, 1, msg->data[1]); 800 break; 801 case 3: 802 RMIXL_DMTC2(RMIXL_COP_2_TXBUF, 0, msg->data[0]); 803 RMIXL_DMTC2(RMIXL_COP_2_TXBUF, 1, msg->data[1]); 804 RMIXL_DMTC2(RMIXL_COP_2_TXBUF, 2, msg->data[2]); 805 break; 806 case 4: 807 RMIXL_DMTC2(RMIXL_COP_2_TXBUF, 0, msg->data[0]); 808 RMIXL_DMTC2(RMIXL_COP_2_TXBUF, 1, msg->data[1]); 809 RMIXL_DMTC2(RMIXL_COP_2_TXBUF, 2, msg->data[2]); 810 RMIXL_DMTC2(RMIXL_COP_2_TXBUF, 3, msg->data[3]); 811 break; 812 default: 813 DIAG_PRF(("%s: bad size %d", __func__, size)); 814 rv = -1; 815 goto out; 816 } 817 818 for (int try=16; try--; ) { 819 RMIXL_MFC2(RMIXL_COP_2_MSG_STS, 0, msg_status); 820 if ((msg_status & (RMIXL_MSG_STS0_LPF|RMIXL_MSG_STS0_SPF|RMIXL_MSG_STS0_SMP)) == 0) 821 goto send; 822 DELAY(10); /* XXX ??? */ 823 } 824 DIAG_PRF(("%s: cpu=%ld, msg %p, dst_id=%d, sts=%#x: can't send\n", 825 __func__, cpu_number(), msg, dest_id, msg_status)); 826 rv = -1; 827 goto out; 828 send: 829 desc = RMIXL_MSGSND_DESC(size, code, dest_id); 830 DPRINTF(("%s: cpu %ld, desc %#x\n", __func__, cpu_number(), desc)); 831 for (int try=16; try--; ) { 832 rmixl_msgsnd(desc); 833 RMIXL_MFC2(RMIXL_COP_2_MSG_STS, 0, msg_status); 834 RMIXL_MFC2(RMIXL_COP_2_MSG_STS, 1, msg_status1); 835 if (((msg_status & RMIXL_MSG_STS0_SCF) == 0) 836 && ((msg_status1 & RMIXL_MSG_STS1_ERRS) == 0)) 837 goto out; 838 #if 0 839 #ifdef DEBUG 840 if ((msg_status & RMIXL_MSG_STS0_SCF) != 0) { 841 uint32_t r; 842 u_int regno = RMIXL_COP_2_CREDITS+fmnp->fmn_core; 843 u_int sel = fmnp->fmn_thread; 844 printf("%s: CC[%d,%d]=", __func__, regno, sel); 845 FMN_CP2_RD_SWITCH_RW(READ, regno, sel, r); 846 printf("%s: CC[%d,%d]=%d\n", __func__, regno, sel, r); 847 } 848 #endif /* DEBUG */ 849 #endif /* 0 */ 850 /* clear status1 error(s) */ 851 if ((msg_status1 & RMIXL_MSG_STS1_ERRS) != 0) { 852 RMIXL_MFC2(RMIXL_COP_2_MSG_STS, 1, msg_status1); 853 RMIXL_MTC2(RMIXL_COP_2_MSG_STS, 1, msg_status1); 854 } 855 DIAG_PRF(("%s: src=%ld, dst=%d, sts=%#x, %#x: send error, try %d\n", 856 __func__, cpu_number(), dest_id, msg_status, msg_status1, try)); 857 DELAY(10); 858 } 859 rv = -1; 860 out: 861 rmixl_cp2_restore(cp0_status); 862 mutex_exit(fmnp->fmn_lock); 863 864 return rv; 865 } 866 867 /* 868 * rmixl_fmn_msg_recv 869 * 870 * - grab fmn_lock and call rmixl_fmn_msg_recv_subr to do the real work 871 * - assume cp2 access is already enabled 872 */ 873 int 874 rmixl_fmn_msg_recv(u_int bucket, rmixl_fmn_rxmsg_t *rxmsg) 875 { 876 fmn_t *fmnp; 877 int rv; 878 879 fmnp = fmn_lookup(cpu_number()); 880 mutex_enter(fmnp->fmn_lock); 881 rv = rmixl_fmn_msg_recv_subr(bucket, rxmsg); 882 mutex_exit(fmnp->fmn_lock); 883 884 return rv; 885 } 886 887 /* 888 * rmixl_fmn_msg_recv_subr 889 * 890 * - assume fmn_lock is owned 891 * - assume cp2 access is already enabled 892 */ 893 static int 894 rmixl_fmn_msg_recv_subr(u_int bucket, rmixl_fmn_rxmsg_t *rxmsg) 895 { 896 fmn_t *fmnp; 897 uint32_t msg_status; 898 int rv; 899 900 fmnp = fmn_lookup(cpu_number()); 901 KASSERT(mutex_owned(fmnp->fmn_lock) != 0); 902 903 for (int try=16; try--; ) { 904 RMIXL_MFC2(RMIXL_COP_2_MSG_STS, 0, msg_status); 905 if ((msg_status & (RMIXL_MSG_STS0_LPF)) == 0) 906 goto recv; 907 } 908 DIAG_PRF(("%s: cpu=%ld, bucket=%d, sts=%#x: Load Pending Fail\n", 909 __func__, cpu_number(), bucket, msg_status)); 910 rv = -1; 911 goto out; 912 recv: 913 rmixl_msgld(bucket); 914 RMIXL_MFC2(RMIXL_COP_2_MSG_STS, 0, msg_status); 915 DPRINTF(("%s: cpu=%ld, bucket=%d, sts=%#x\n", 916 __func__, cpu_number(), bucket, msg_status)); 917 rv = msg_status & (RMIXL_MSG_STS0_LEF|RMIXL_MSG_STS0_LPF); 918 if (rv == 0) { 919 rxmsg->rxsid = (msg_status & RMIXL_MSG_STS0_RMSID) 920 >> RMIXL_MSG_STS0_RMSID_SHIFT; 921 rxmsg->code = (msg_status & RMIXL_MSG_STS0_RMSC) 922 >> RMIXL_MSG_STS0_RMSC_SHIFT; 923 rxmsg->size = ((msg_status & RMIXL_MSG_STS0_RMS) 924 >> RMIXL_MSG_STS0_RMS_SHIFT) + 1; 925 switch(rxmsg->size) { 926 case 1: 927 RMIXL_DMFC2(RMIXL_COP_2_RXBUF, 0, rxmsg->msg.data[0]); 928 break; 929 case 2: 930 RMIXL_DMFC2(RMIXL_COP_2_RXBUF, 0, rxmsg->msg.data[0]); 931 RMIXL_DMFC2(RMIXL_COP_2_RXBUF, 1, rxmsg->msg.data[1]); 932 break; 933 case 3: 934 RMIXL_DMFC2(RMIXL_COP_2_RXBUF, 0, rxmsg->msg.data[0]); 935 RMIXL_DMFC2(RMIXL_COP_2_RXBUF, 1, rxmsg->msg.data[1]); 936 RMIXL_DMFC2(RMIXL_COP_2_RXBUF, 2, rxmsg->msg.data[2]); 937 break; 938 case 4: 939 RMIXL_DMFC2(RMIXL_COP_2_RXBUF, 0, rxmsg->msg.data[0]); 940 RMIXL_DMFC2(RMIXL_COP_2_RXBUF, 1, rxmsg->msg.data[1]); 941 RMIXL_DMFC2(RMIXL_COP_2_RXBUF, 2, rxmsg->msg.data[2]); 942 RMIXL_DMFC2(RMIXL_COP_2_RXBUF, 3, rxmsg->msg.data[3]); 943 break; 944 default: 945 /* "impossible" due to bitfield width */ 946 panic("%s: bad size %d", __func__, rxmsg->size); 947 } 948 } 949 out: 950 951 return rv; 952 } 953 954 #ifdef FMN_DEBUG 955 void 956 rmixl_fmn_cp2_dump(void) 957 { 958 uint32_t cp0_status; 959 960 cp0_status = rmixl_cp2_enable(); 961 962 CPU2_PRINT_8(RMIXL_COP_2_TXBUF, 0); 963 CPU2_PRINT_8(RMIXL_COP_2_TXBUF, 1); 964 CPU2_PRINT_8(RMIXL_COP_2_TXBUF, 2); 965 CPU2_PRINT_8(RMIXL_COP_2_TXBUF, 3); 966 967 CPU2_PRINT_8(RMIXL_COP_2_RXBUF, 0); 968 CPU2_PRINT_8(RMIXL_COP_2_RXBUF, 1); 969 CPU2_PRINT_8(RMIXL_COP_2_RXBUF, 2); 970 CPU2_PRINT_8(RMIXL_COP_2_RXBUF, 3); 971 972 CPU2_PRINT_4(RMIXL_COP_2_MSG_STS, 0); 973 CPU2_PRINT_4(RMIXL_COP_2_MSG_STS, 1); 974 975 CPU2_PRINT_4(RMIXL_COP_2_MSG_CFG, 0); 976 CPU2_PRINT_4(RMIXL_COP_2_MSG_CFG, 1); 977 978 CPU2_PRINT_4(RMIXL_COP_2_MSG_BSZ, 0); 979 CPU2_PRINT_4(RMIXL_COP_2_MSG_BSZ, 1); 980 CPU2_PRINT_4(RMIXL_COP_2_MSG_BSZ, 2); 981 CPU2_PRINT_4(RMIXL_COP_2_MSG_BSZ, 3); 982 CPU2_PRINT_4(RMIXL_COP_2_MSG_BSZ, 4); 983 CPU2_PRINT_4(RMIXL_COP_2_MSG_BSZ, 5); 984 CPU2_PRINT_4(RMIXL_COP_2_MSG_BSZ, 6); 985 CPU2_PRINT_4(RMIXL_COP_2_MSG_BSZ, 7); 986 987 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 0, 0); 988 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 0, 1); 989 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 0, 2); 990 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 0, 3); 991 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 0, 4); 992 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 0, 5); 993 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 0, 6); 994 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 0, 7); 995 996 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 1, 0); 997 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 1, 1); 998 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 1, 2); 999 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 1, 3); 1000 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 1, 4); 1001 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 1, 5); 1002 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 1, 6); 1003 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 1, 7); 1004 1005 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 2, 0); 1006 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 2, 1); 1007 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 2, 2); 1008 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 2, 3); 1009 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 2, 4); 1010 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 2, 5); 1011 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 2, 6); 1012 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 2, 7); 1013 1014 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 3, 0); 1015 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 3, 1); 1016 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 3, 2); 1017 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 3, 3); 1018 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 3, 4); 1019 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 3, 5); 1020 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 3, 6); 1021 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 3, 7); 1022 1023 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 4, 0); 1024 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 4, 1); 1025 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 4, 2); 1026 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 4, 3); 1027 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 4, 4); 1028 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 4, 5); 1029 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 4, 6); 1030 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 4, 7); 1031 1032 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 5, 0); 1033 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 5, 1); 1034 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 5, 2); 1035 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 5, 3); 1036 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 5, 4); 1037 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 5, 5); 1038 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 5, 6); 1039 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 5, 7); 1040 1041 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 6, 0); 1042 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 6, 1); 1043 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 6, 2); 1044 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 6, 3); 1045 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 6, 4); 1046 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 6, 5); 1047 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 6, 6); 1048 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 6, 7); 1049 1050 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 7, 0); 1051 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 7, 1); 1052 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 7, 2); 1053 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 7, 3); 1054 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 7, 4); 1055 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 7, 5); 1056 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 7, 6); 1057 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 7, 7); 1058 1059 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 8, 0); 1060 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 8, 1); 1061 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 8, 2); 1062 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 8, 3); 1063 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 8, 4); 1064 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 8, 5); 1065 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 8, 6); 1066 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 8, 7); 1067 1068 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 9, 0); 1069 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 9, 1); 1070 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 9, 2); 1071 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 9, 3); 1072 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 9, 4); 1073 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 9, 5); 1074 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 9, 6); 1075 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 9, 7); 1076 1077 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 10, 0); 1078 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 10, 1); 1079 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 10, 2); 1080 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 10, 3); 1081 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 10, 4); 1082 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 10, 5); 1083 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 10, 6); 1084 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 10, 7); 1085 1086 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 11, 0); 1087 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 11, 1); 1088 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 11, 2); 1089 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 11, 3); 1090 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 11, 4); 1091 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 11, 5); 1092 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 11, 6); 1093 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 11, 7); 1094 1095 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 12, 0); 1096 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 12, 1); 1097 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 12, 2); 1098 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 12, 3); 1099 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 12, 4); 1100 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 12, 5); 1101 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 12, 6); 1102 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 12, 7); 1103 1104 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 13, 0); 1105 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 13, 1); 1106 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 13, 2); 1107 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 13, 3); 1108 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 13, 4); 1109 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 13, 5); 1110 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 13, 6); 1111 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 13, 7); 1112 1113 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 14, 0); 1114 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 14, 1); 1115 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 14, 2); 1116 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 14, 3); 1117 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 14, 4); 1118 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 14, 5); 1119 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 14, 6); 1120 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 14, 7); 1121 1122 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 15, 0); 1123 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 15, 1); 1124 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 15, 2); 1125 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 15, 3); 1126 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 15, 4); 1127 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 15, 5); 1128 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 15, 6); 1129 CPU2_PRINT_4(RMIXL_COP_2_CREDITS + 15, 7); 1130 1131 rmixl_cp2_restore(cp0_status); 1132 } 1133 1134 1135 void 1136 rmixl_fmn_cc_dump(void) 1137 { 1138 uint32_t cc[4][8]; 1139 1140 FMN_CP2_4SEL_READ(RMIXL_COP_2_CREDITS, 0, &cc[0][0]); 1141 FMN_CP2_4SEL_READ(RMIXL_COP_2_CREDITS, 4, &cc[0][4]); 1142 FMN_CP2_4SEL_READ(RMIXL_COP_2_CREDITS+1, 0, &cc[1][0]); 1143 FMN_CP2_4SEL_READ(RMIXL_COP_2_CREDITS+1, 4, &cc[1][4]); 1144 FMN_CP2_4SEL_READ(RMIXL_COP_2_CREDITS+2, 0, &cc[2][0]); 1145 FMN_CP2_4SEL_READ(RMIXL_COP_2_CREDITS+2, 4, &cc[2][4]); 1146 FMN_CP2_4SEL_READ(RMIXL_COP_2_CREDITS+3, 0, &cc[3][0]); 1147 FMN_CP2_4SEL_READ(RMIXL_COP_2_CREDITS+3, 4, &cc[3][4]); 1148 1149 printf("%s: cpu %ld\n", __func__, cpu_number()); 1150 for (int i=0; i < 4; i++) { 1151 for (int j=0; j < 8; j++) 1152 printf(" %#x,", cc[i][j]); 1153 printf("\n"); 1154 } 1155 } 1156 1157 #endif /* FMN_DEBUG */ 1158
Indexes created Wed Oct 29 09:09:48 GMT 2025