rmixl_intr.c revision 1.1.2.15
1 /* $NetBSD: rmixl_intr.c,v 1.1.2.15 2010/03/21 21:25:30 cliff Exp $ */ 2 3 /*- 4 * Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or 8 * without modification, are permitted provided that the following 9 * conditions are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above 13 * copyright notice, this list of conditions and the following 14 * disclaimer in the documentation and/or other materials provided 15 * with the distribution. 16 * 3. The names of the authors may not be used to endorse or promote 17 * products derived from this software without specific prior 18 * written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY 21 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 23 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, 25 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 27 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 29 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 30 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 31 * OF SUCH DAMAGE. 32 */ 33 /*- 34 * Copyright (c) 2001 The NetBSD Foundation, Inc. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to The NetBSD Foundation 38 * by Jason R. Thorpe. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 49 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 50 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 51 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 52 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 53 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 54 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 55 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 56 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 57 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 58 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 59 * POSSIBILITY OF SUCH DAMAGE. 60 */ 61 62 /* 63 * Platform-specific interrupt support for the RMI XLP, XLR, XLS 64 */ 65 66 #include <sys/cdefs.h> 67 __KERNEL_RCSID(0, "$NetBSD: rmixl_intr.c,v 1.1.2.15 2010/03/21 21:25:30 cliff Exp $"); 68 69 #include "opt_ddb.h" 70 #define __INTR_PRIVATE 71 72 #include <sys/param.h> 73 #include <sys/queue.h> 74 #include <sys/malloc.h> 75 #include <sys/systm.h> 76 #include <sys/device.h> 77 #include <sys/kernel.h> 78 #include <sys/atomic.h> 79 #include <sys/cpu.h> 80 81 #include <machine/bus.h> 82 #include <machine/intr.h> 83 84 #include <mips/cpu.h> 85 #include <mips/locore.h> 86 87 #include <mips/rmi/rmixlreg.h> 88 #include <mips/rmi/rmixlvar.h> 89 90 #include <mips/rmi/rmixl_cpuvar.h> 91 #include <mips/rmi/rmixl_intr.h> 92 93 #include <dev/pci/pcireg.h> 94 #include <dev/pci/pcivar.h> 95 96 // #define IOINTR_DEBUG 1 97 #ifdef IOINTR_DEBUG 98 int iointr_debug = IOINTR_DEBUG; 99 # define DPRINTF(x) do { if (iointr_debug) printf x ; } while(0) 100 #else 101 # define DPRINTF(x) 102 #endif 103 104 #define RMIXL_PICREG_READ(off) \ 105 RMIXL_IOREG_READ(RMIXL_IO_DEV_PIC + (off)) 106 #define RMIXL_PICREG_WRITE(off, val) \ 107 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PIC + (off), (val)) 108 109 /* 110 * do not clear these when acking EIRR 111 * (otherwise they get lost) 112 */ 113 #define RMIXL_EIRR_PRESERVE_MASK \ 114 ((MIPS_INT_MASK_5|MIPS_SOFT_INT_MASK) >> 8) 115 116 /* 117 * IRT assignments depends on the RMI chip family 118 * (XLS1xx vs. XLS2xx vs. XLS3xx vs. XLS6xx) 119 * use the right irq (and display string table) for the CPU that's running. 120 */ 121 122 /* 123 * rmixl_irtnames_xls1xx 124 * - use for XLS1xx, XLS2xx, XLS4xx-Lite 125 */ 126 static const char * const rmixl_irtnames_xls1xx[NIRTS] = { 127 "int 0 (watchdog)", /* 0 */ 128 "int 1 (timer0)", /* 1 */ 129 "int 2 (timer1)", /* 2 */ 130 "int 3 (timer2)", /* 3 */ 131 "int 4 (timer3)", /* 4 */ 132 "int 5 (timer4)", /* 5 */ 133 "int 6 (timer5)", /* 6 */ 134 "int 7 (timer6)", /* 7 */ 135 "int 8 (timer7)", /* 8 */ 136 "int 9 (uart0)", /* 9 */ 137 "int 10 (uart1)", /* 10 */ 138 "int 11 (i2c0)", /* 11 */ 139 "int 12 (i2c1)", /* 12 */ 140 "int 13 (pcmcia)", /* 13 */ 141 "int 14 (gpio_a)", /* 14 */ 142 "int 15 (irq15)", /* 15 */ 143 "int 16 (bridge_tb)", /* 16 */ 144 "int 17 (gmac0)", /* 17 */ 145 "int 18 (gmac1)", /* 18 */ 146 "int 19 (gmac2)", /* 19 */ 147 "int 20 (gmac3)", /* 20 */ 148 "int 21 (irq21)", /* 21 */ 149 "int 22 (irq22)", /* 22 */ 150 "int 23 (irq23)", /* 23 */ 151 "int 24 (irq24)", /* 24 */ 152 "int 25 (bridge_err)", /* 25 */ 153 "int 26 (pcie_link0)", /* 26 */ 154 "int 27 (pcie_link1)", /* 27 */ 155 "int 28 (irq28)", /* 28 */ 156 "int 29 (pcie_err)", /* 29 */ 157 "int 30 (gpio_b)", /* 30 */ 158 "int 31 (usb)", /* 31 */ 159 }; 160 161 /* 162 * rmixl_irtnames_xls4xx: 163 * - use for XLS4xx, XLS6xx 164 */ 165 static const char * const rmixl_irtnames_xls4xx[NIRTS] = { 166 "int 0 (watchdog)", /* 0 */ 167 "int 1 (timer0)", /* 1 */ 168 "int 2 (timer1)", /* 2 */ 169 "int 3 (timer2)", /* 3 */ 170 "int 4 (timer3)", /* 4 */ 171 "int 5 (timer4)", /* 5 */ 172 "int 6 (timer5)", /* 6 */ 173 "int 7 (timer6)", /* 7 */ 174 "int 8 (timer7)", /* 8 */ 175 "int 9 (uart0)", /* 9 */ 176 "int 10 (uart1)", /* 10 */ 177 "int 11 (i2c0)", /* 11 */ 178 "int 12 (i2c1)", /* 12 */ 179 "int 13 (pcmcia)", /* 13 */ 180 "int 14 (gpio_a)", /* 14 */ 181 "int 15 (irq15)", /* 15 */ 182 "int 16 (bridge_tb)", /* 16 */ 183 "int 17 (gmac0)", /* 17 */ 184 "int 18 (gmac1)", /* 18 */ 185 "int 19 (gmac2)", /* 19 */ 186 "int 20 (gmac3)", /* 20 */ 187 "int 21 (irq21)", /* 21 */ 188 "int 22 (irq22)", /* 22 */ 189 "int 23 (irq23)", /* 23 */ 190 "int 24 (irq24)", /* 24 */ 191 "int 25 (bridge_err)", /* 25 */ 192 "int 26 (pcie_link0)", /* 26 */ 193 "int 27 (pcie_link1)", /* 27 */ 194 "int 28 (pcie_link2)", /* 28 */ 195 "int 29 (pcie_link3)", /* 29 */ 196 "int 30 (gpio_b)", /* 30 */ 197 "int 31 (usb)", /* 31 */ 198 }; 199 200 /* 201 * rmixl_vecnames_common: 202 * - use for unknown cpu implementation 203 * - covers all vectors, not just IRT intrs 204 */ 205 static const char * const rmixl_vecnames_common[NINTRVECS] = { 206 "int 0", /* 0 */ 207 "int 1", /* 1 */ 208 "int 2", /* 2 */ 209 "int 3", /* 3 */ 210 "int 4", /* 4 */ 211 "int 5", /* 5 */ 212 "int 6", /* 6 */ 213 "int 7", /* 7 */ 214 "int 8", /* 8 */ 215 "int 9", /* 9 */ 216 "int 10", /* 10 */ 217 "int 11", /* 11 */ 218 "int 12", /* 12 */ 219 "int 13", /* 13 */ 220 "int 14", /* 14 */ 221 "int 15", /* 15 */ 222 "int 16", /* 16 */ 223 "int 17", /* 17 */ 224 "int 18", /* 18 */ 225 "int 19", /* 19 */ 226 "int 20", /* 20 */ 227 "int 21", /* 21 */ 228 "int 22", /* 22 */ 229 "int 23", /* 23 */ 230 "int 24", /* 24 */ 231 "int 25", /* 25 */ 232 "int 26", /* 26 */ 233 "int 27", /* 27 */ 234 "int 28", /* 28 */ 235 "int 29", /* 29 */ 236 "int 30", /* 30 */ 237 "int 31", /* 31 */ 238 "int 32 (ipi)", /* 32 */ 239 "int 33 (fmn)", /* 33 */ 240 "int 34", /* 34 */ 241 "int 35", /* 35 */ 242 "int 36", /* 36 */ 243 "int 37", /* 37 */ 244 "int 38", /* 38 */ 245 "int 39", /* 39 */ 246 "int 40", /* 40 */ 247 "int 41", /* 41 */ 248 "int 42", /* 42 */ 249 "int 43", /* 43 */ 250 "int 44", /* 44 */ 251 "int 45", /* 45 */ 252 "int 46", /* 46 */ 253 "int 47", /* 47 */ 254 "int 48", /* 48 */ 255 "int 49", /* 49 */ 256 "int 50", /* 50 */ 257 "int 51", /* 51 */ 258 "int 52", /* 52 */ 259 "int 53", /* 53 */ 260 "int 54", /* 54 */ 261 "int 55", /* 55 */ 262 "int 56", /* 56 */ 263 "int 57", /* 57 */ 264 "int 58", /* 58 */ 265 "int 59", /* 59 */ 266 "int 60", /* 60 */ 267 "int 61", /* 61 */ 268 "int 62", /* 63 */ 269 "int 63", /* 63 */ 270 }; 271 272 /* 273 * mask of CPUs attached 274 * once they are attached, this var is read-only so mp safe 275 */ 276 static uint32_t cpu_present_mask; 277 278 rmixl_intrhand_t rmixl_intrhand[NINTRVECS]; 279 280 #ifdef DIAGNOSTIC 281 static int rmixl_pic_init_done; 282 #endif 283 284 285 static void rmixl_irt_init(int); 286 static void rmixl_irt_disestablish(int); 287 static void rmixl_irt_establish(int, int, 288 rmixl_intr_trigger_t, rmixl_intr_polarity_t); 289 290 #ifdef MULTIPROCESSOR 291 static int rmixl_send_ipi(struct cpu_info *, int); 292 static int rmixl_ipi_intr(void *); 293 #endif 294 295 #if defined(IOINTR_DEBUG) || defined(DIAGNOSTIC) 296 int rmixl_intrhand_print_subr(int); 297 int rmixl_intrhand_print(void); 298 int rmixl_irt_print(void); 299 #endif 300 301 302 static inline u_int 303 dclz(uint64_t val) 304 { 305 int nlz; 306 307 asm volatile("dclz %0, %1;" 308 : "=r"(nlz) : "r"(val)); 309 310 return nlz; 311 } 312 313 static inline void 314 rmixl_irt_entry_print(u_int irq) 315 { 316 #if defined(IOINTR_DEBUG) || defined(DDB) 317 uint32_t c0, c1; 318 319 if ((irq < 0) || (irq > NIRTS)) 320 return; 321 c0 = RMIXL_PICREG_READ(RMIXL_PIC_IRTENTRYC0(irq)); 322 c1 = RMIXL_PICREG_READ(RMIXL_PIC_IRTENTRYC1(irq)); 323 printf("irt[%d]: %#x, %#x\n", irq, c0, c1); 324 #endif 325 } 326 327 void 328 evbmips_intr_init(void) 329 { 330 uint32_t r; 331 332 KASSERT(cpu_rmixls(mips_options.mips_cpu)); 333 334 #ifdef IOINTR_DEBUG 335 printf("IPL_NONE=%d, mask %#"PRIx64"\n", 336 IPL_NONE, ipl_eimr_map[IPL_NONE]); 337 printf("IPL_SOFTCLOCK=%d, mask %#"PRIx64"\n", 338 IPL_SOFTCLOCK, ipl_eimr_map[IPL_SOFTCLOCK]); 339 printf("IPL_SOFTNET=%d, mask %#"PRIx64"\n", 340 IPL_SOFTNET, ipl_eimr_map[IPL_SOFTNET]); 341 printf("IPL_VM=%d, mask %#"PRIx64"\n", 342 IPL_VM, ipl_eimr_map[IPL_VM]); 343 printf("IPL_SCHED=%d, mask %#"PRIx64"\n", 344 IPL_SCHED, ipl_eimr_map[IPL_HIGH]); 345 printf("IPL_HIGH=%d, mask %#"PRIx64"\n", 346 IPL_HIGH, ipl_eimr_map[IPL_NONE]); 347 #endif 348 349 #ifdef DIAGNOSTIC 350 if (rmixl_pic_init_done != 0) 351 panic("%s: rmixl_pic_init_done %d", 352 __func__, rmixl_pic_init_done); 353 #endif 354 355 /* 356 * initialize (zero) all IRT Entries in the PIC 357 */ 358 for (int i=0; i < NIRTS; i++) 359 rmixl_irt_init(i); 360 361 /* 362 * disable watchdog NMI, timers 363 * 364 * XXX 365 * WATCHDOG_ENB is preserved because clearing it causes 366 * hang on the XLS616 (but not on the XLS408) 367 */ 368 r = RMIXL_PICREG_READ(RMIXL_PIC_CONTROL); 369 r &= RMIXL_PIC_CONTROL_RESV|RMIXL_PIC_CONTROL_WATCHDOG_ENB; 370 RMIXL_PICREG_WRITE(RMIXL_PIC_CONTROL, r); 371 372 #ifdef DIAGNOSTIC 373 rmixl_pic_init_done = 1; 374 #endif 375 376 } 377 378 /* 379 * establish vector for mips3 count/compare clock interrupt 380 * this ensures we enable in EIRR, 381 * even though cpu_intr() handles the interrupt 382 */ 383 void * 384 rmixl_intr_init_clk(void) 385 { 386 int vec = ffs(MIPS_INT_MASK_5 >> 8) - 1; 387 void *ih = rmixl_vec_establish(vec, 0, IPL_SCHED, NULL, NULL); 388 if (ih == NULL) 389 panic("%s: establish vec %d failed", __func__, vec); 390 391 return ih; 392 } 393 394 #ifdef MULTIPROCESSOR 395 /* 396 * establish IPI interrupt and send function 397 */ 398 void * 399 rmixl_intr_init_ipi(void) 400 { 401 void *ih = rmixl_vec_establish(RMIXL_INTRVEC_IPI, -1, IPL_SCHED, 402 rmixl_ipi_intr, NULL); 403 if (ih == NULL) 404 panic("%s: establish vec %d failed", 405 __func__, RMIXL_INTRVEC_IPI); 406 407 mips_locoresw.lsw_send_ipi = rmixl_send_ipi; 408 409 return ih; 410 } 411 #endif /* MULTIPROCESSOR */ 412 413 /* 414 * initialize per-cpu interrupt stuff in softc 415 * accumulate per-cpu bits in 'cpu_present_mask' 416 */ 417 void 418 rmixl_intr_init_cpu(struct cpu_info *ci) 419 { 420 struct rmixl_cpu_softc *sc = (void *)ci->ci_softc; 421 KASSERT(sc != NULL); 422 423 /* zero the EIRR ? */ 424 uint64_t eirr = 0; 425 asm volatile("dmtc0 %0, $9, 6;" :: "r"(eirr)); 426 427 for (int vec=0; vec < NINTRVECS; vec++) 428 evcnt_attach_dynamic(&sc->sc_vec_evcnts[vec], 429 EVCNT_TYPE_INTR, NULL, 430 device_xname(sc->sc_dev), 431 rmixl_intr_string(vec)); 432 433 KASSERT(ci->ci_cpuid < (sizeof(cpu_present_mask) * 8)); 434 cpu_present_mask |= 1 << ci->ci_cpuid; 435 } 436 437 /* 438 * rmixl_intr_string - return pointer to display name of a PIC-based interrupt 439 */ 440 const char * 441 rmixl_intr_string(int irq) 442 { 443 const char *name; 444 445 if (irq < 0 || irq >= NINTRVECS) 446 panic("%s: irq index %d out of range, max %d", 447 __func__, irq, NIRTS - 1); 448 449 if (irq >= NIRTS) 450 return rmixl_vecnames_common[irq]; 451 452 switch (MIPS_PRID_IMPL(mips_options.mips_cpu_id)) { 453 case MIPS_XLS104: 454 case MIPS_XLS108: 455 case MIPS_XLS204: 456 case MIPS_XLS208: 457 case MIPS_XLS404LITE: 458 case MIPS_XLS408LITE: 459 name = rmixl_irtnames_xls1xx[irq]; 460 break; 461 case MIPS_XLS404: 462 case MIPS_XLS408: 463 case MIPS_XLS416: 464 case MIPS_XLS608: 465 case MIPS_XLS616: 466 name = rmixl_irtnames_xls4xx[irq]; 467 break; 468 default: 469 name = rmixl_vecnames_common[irq]; 470 break; 471 } 472 473 return name; 474 } 475 476 /* 477 * rmixl_irt_thread_mask 478 * 479 * given a bitmask of cpus, return a, IRT thread mask 480 */ 481 static uint32_t 482 rmixl_irt_thread_mask(int cpumask) 483 { 484 uint32_t irtc0; 485 486 #if defined(MULTIPROCESSOR) 487 #ifndef NOTYET 488 if (cpumask == -1) 489 return 1; /* XXX TMP FIXME */ 490 #endif 491 492 /* 493 * discount cpus not present 494 */ 495 cpumask &= cpu_present_mask; 496 497 switch (MIPS_PRID_IMPL(mips_options.mips_cpu_id)) { 498 case MIPS_XLS104: 499 case MIPS_XLS204: 500 case MIPS_XLS404: 501 case MIPS_XLS404LITE: 502 irtc0 = ((cpumask >> 2) << 4) | (cpumask & __BITS(1,0)); 503 irtc0 &= (__BITS(5,4) | __BITS(1,0)); 504 break; 505 case MIPS_XLS108: 506 case MIPS_XLS208: 507 case MIPS_XLS408: 508 case MIPS_XLS408LITE: 509 case MIPS_XLS608: 510 irtc0 = cpumask & __BITS(7,0); 511 break; 512 case MIPS_XLS416: 513 case MIPS_XLS616: 514 irtc0 = cpumask & __BITS(15,0); 515 break; 516 default: 517 panic("%s: unknown cpu ID %#x\n", __func__, 518 mips_options.mips_cpu_id); 519 } 520 #else 521 irtc0 = 1; 522 #endif /* MULTIPROCESSOR */ 523 524 return irtc0; 525 } 526 527 /* 528 * rmixl_irt_init 529 * - invalidate IRT Entry for irq 530 * - unmask Thread#0 in low word (assume we only have 1 thread) 531 */ 532 static void 533 rmixl_irt_init(int irq) 534 { 535 RMIXL_PICREG_WRITE(RMIXL_PIC_IRTENTRYC1(irq), 0); /* high word */ 536 RMIXL_PICREG_WRITE(RMIXL_PIC_IRTENTRYC0(irq), 0); /* low word */ 537 } 538 539 /* 540 * rmixl_irt_disestablish 541 * - invalidate IRT Entry for irq 542 * - writes to IRTENTRYC1 only; leave IRTENTRYC0 as-is 543 */ 544 static void 545 rmixl_irt_disestablish(int irq) 546 { 547 DPRINTF(("%s: irq %d, irtc1 %#x\n", __func__, irq, 0)); 548 rmixl_irt_init(irq); 549 } 550 551 /* 552 * rmixl_irt_establish 553 * - construct an IRT Entry for irq and write to PIC 554 */ 555 static void 556 rmixl_irt_establish(int irq, int cpumask, rmixl_intr_trigger_t trigger, 557 rmixl_intr_polarity_t polarity) 558 { 559 uint32_t irtc1; 560 uint32_t irtc0; 561 562 switch (trigger) { 563 case RMIXL_TRIG_EDGE: 564 case RMIXL_TRIG_LEVEL: 565 break; 566 default: 567 panic("%s: bad trigger %d\n", __func__, trigger); 568 } 569 570 switch (polarity) { 571 case RMIXL_POLR_RISING: 572 case RMIXL_POLR_HIGH: 573 case RMIXL_POLR_FALLING: 574 case RMIXL_POLR_LOW: 575 break; 576 default: 577 panic("%s: bad polarity %d\n", __func__, polarity); 578 } 579 580 /* 581 * XXX IRT entries are not shared 582 */ 583 KASSERT(RMIXL_PICREG_READ(RMIXL_PIC_IRTENTRYC0(irq)) == 0); 584 KASSERT(RMIXL_PICREG_READ(RMIXL_PIC_IRTENTRYC1(irq)) == 0); 585 586 irtc0 = rmixl_irt_thread_mask(cpumask); 587 588 irtc1 = RMIXL_PIC_IRTENTRYC1_VALID; 589 irtc1 |= RMIXL_PIC_IRTENTRYC1_GL; /* local */ 590 591 if (trigger == RMIXL_TRIG_LEVEL) 592 irtc1 |= RMIXL_PIC_IRTENTRYC1_TRG; 593 594 if ((polarity == RMIXL_POLR_FALLING) || (polarity == RMIXL_POLR_LOW)) 595 irtc1 |= RMIXL_PIC_IRTENTRYC1_P; 596 597 irtc1 |= irq; /* route to vector 'irq' */ 598 599 /* 600 * write IRT Entry to PIC 601 */ 602 DPRINTF(("%s: irq %d, irtc0 %#x, irtc1 %#x\n", 603 __func__, irq, irtc0, irtc1)); 604 RMIXL_PICREG_WRITE(RMIXL_PIC_IRTENTRYC0(irq), irtc0); /* low word */ 605 RMIXL_PICREG_WRITE(RMIXL_PIC_IRTENTRYC1(irq), irtc1); /* high word */ 606 } 607 608 void * 609 rmixl_vec_establish(int vec, int cpumask, int ipl, 610 int (*func)(void *), void *arg) 611 { 612 rmixl_intrhand_t *ih; 613 int s; 614 615 DPRINTF(("%s: vec %d, cpumask %#x, ipl %d, func %p, arg %p, " 616 "vec %d\n", 617 __func__, vec, cpumask, ipl, func, arg, vec)); 618 #ifdef DIAGNOSTIC 619 if (rmixl_pic_init_done == 0) 620 panic("%s: called before evbmips_intr_init", __func__); 621 #endif 622 623 /* 624 * check args 625 */ 626 if (vec < 0 || vec >= NINTRVECS) 627 panic("%s: vec %d out of range, max %d", 628 __func__, vec, NINTRVECS - 1); 629 if (ipl <= 0 || ipl >= _IPL_N) 630 panic("%s: ipl %d out of range, min %d, max %d", 631 __func__, ipl, 1, _IPL_N - 1); 632 633 s = splhigh(); 634 635 ih = &rmixl_intrhand[vec]; 636 637 ih->ih_func = func; 638 ih->ih_arg = arg; 639 ih->ih_irq = vec; 640 ih->ih_ipl = ipl; 641 ih->ih_cpumask = cpumask; 642 643 splx(s); 644 645 return ih; 646 } 647 648 void * 649 rmixl_intr_establish(int irq, int cpumask, int ipl, rmixl_intr_trigger_t trigger, 650 rmixl_intr_polarity_t polarity, int (*func)(void *), void *arg) 651 { 652 rmixl_intrhand_t *ih; 653 int s; 654 655 #ifdef DIAGNOSTIC 656 if (rmixl_pic_init_done == 0) 657 panic("%s: called before rmixl_pic_init_done", __func__); 658 #endif 659 660 /* 661 * check args 662 */ 663 if (irq < 0 || irq >= NINTRVECS) 664 panic("%s: irq %d out of range, max %d", 665 __func__, irq, NIRTS - 1); 666 if (ipl <= 0 || ipl >= _IPL_N) 667 panic("%s: ipl %d out of range, min %d, max %d", 668 __func__, ipl, 1, _IPL_N - 1); 669 670 DPRINTF(("%s: irq %d, ipl %d\n", __func__, irq, ipl)); 671 672 s = splhigh(); 673 674 /* 675 * establish vector 676 */ 677 ih = rmixl_vec_establish(irq, cpumask, ipl, func, arg); 678 679 /* 680 * establish IRT Entry 681 */ 682 if (irq < 32) 683 rmixl_irt_establish(irq, cpumask, trigger, polarity); 684 685 splx(s); 686 687 return ih; 688 } 689 690 void 691 rmixl_vec_disestablish(void *cookie) 692 { 693 rmixl_intrhand_t *ih = cookie; 694 int s; 695 696 KASSERT(ih = &rmixl_intrhand[ih->ih_irq]); 697 698 s = splhigh(); 699 700 ih->ih_func = NULL; /* XXX race */ 701 702 splx(s); 703 } 704 705 void 706 rmixl_intr_disestablish(void *cookie) 707 { 708 rmixl_intrhand_t *ih = cookie; 709 int vec; 710 int s; 711 712 vec = ih->ih_irq; 713 714 KASSERT(ih = &rmixl_intrhand[vec]); 715 716 s = splhigh(); 717 718 /* 719 * disable/invalidate the IRT Entry if needed 720 */ 721 if (vec < 32) 722 rmixl_irt_disestablish(vec); 723 724 /* 725 * disasociate from vector and free the handle 726 */ 727 rmixl_vec_disestablish(cookie); 728 729 splx(s); 730 } 731 732 void 733 evbmips_iointr(int ipl, vaddr_t pc, uint32_t pending) 734 { 735 struct rmixl_cpu_softc *sc = (void *)curcpu()->ci_softc; 736 737 DPRINTF(("%s: cpu%ld: ipl %d, pc %#"PRIxVADDR", pending %#x\n", 738 __func__, cpu_number(), ipl, pc, pending)); 739 740 /* 741 * 'pending' arg is a summary that there is something to do 742 * the real pending status is obtained from EIRR 743 */ 744 KASSERT(pending == MIPS_INT_MASK_1); 745 746 for (;;) { 747 rmixl_intrhand_t *ih; 748 uint64_t eirr; 749 uint64_t vecbit; 750 int vec; 751 752 asm volatile("dmfc0 %0, $9, 6;" : "=r"(eirr)); 753 754 #ifdef IOINTR_DEBUG 755 uint64_t eimr; 756 asm volatile("dmfc0 %0, $9, 7;" : "=r"(eimr)); 757 printf("%s: eirr %#"PRIx64", eimr %#"PRIx64", mask %#"PRIx64"\n", 758 __func__, eirr, eimr, ipl_eimr_map[ipl-1]); 759 #endif /* IOINTR_DEBUG */ 760 761 eirr &= ipl_eimr_map[ipl-1]; 762 eirr &= ~(MIPS_SOFT_INT_MASK >> 8); /* mask off soft ints */ 763 if (eirr == 0) 764 break; 765 766 vec = 63 - dclz(eirr); 767 ih = &rmixl_intrhand[vec]; 768 769 int s = splhigh(); 770 vecbit = 1ULL << vec; 771 KASSERT ((vecbit & RMIXL_EIRR_PRESERVE_MASK) == 0); 772 asm volatile("dmfc0 %0, $9, 6;" : "=r"(eirr)); 773 eirr &= RMIXL_EIRR_PRESERVE_MASK; 774 eirr |= vecbit; 775 asm volatile("dmtc0 %0, $9, 6;" :: "r"(eirr)); 776 splx(s); 777 778 if (vec < 32) 779 RMIXL_PICREG_WRITE(RMIXL_PIC_INTRACK, 780 (uint32_t)vecbit); 781 782 if (ih->ih_func != NULL) 783 (void)(*ih->ih_func)(ih->ih_arg); 784 785 sc->sc_vec_evcnts[vec].ev_count++; 786 } 787 } 788 789 #ifdef MULTIPROCESSOR 790 static int 791 rmixl_send_ipi(struct cpu_info *ci, int tag) 792 { 793 const cpuid_t cpu = ci->ci_cpuid; 794 uint32_t core = (uint32_t)(cpu >> 2); 795 uint32_t thread = (uint32_t)(cpu & __BITS(1,0)); 796 uint64_t req = 1 << tag; 797 uint32_t r; 798 extern volatile u_long cpus_running; 799 800 if ((cpus_running & 1 << ci->ci_cpuid) == 0) 801 return -1; 802 803 KASSERT(tag < NIPIS); 804 805 r = (thread << RMIXL_PIC_IPIBASE_ID_THREAD_SHIFT) 806 | (core << RMIXL_PIC_IPIBASE_ID_CORE_SHIFT) 807 | RMIXL_INTRVEC_IPI; 808 809 atomic_or_64(&ci->ci_request_ipis, req); 810 811 RMIXL_PICREG_WRITE(RMIXL_PIC_IPIBASE, r); 812 813 return 0; 814 } 815 816 static int 817 rmixl_ipi_intr(void *arg) 818 { 819 struct cpu_info * const ci = curcpu(); 820 uint64_t ipi_mask; 821 822 ipi_mask = atomic_swap_64(&ci->ci_request_ipis, 0); 823 if (ipi_mask == 0) 824 return 0; 825 826 ipi_process(ci, ipi_mask); 827 828 return 1; 829 } 830 #endif /* MULTIPROCESSOR */ 831 832 #if defined(DIAGNOSTIC) || defined(IOINTR_DEBUG) 833 int 834 rmixl_intrhand_print_subr(int vec) 835 { 836 rmixl_intrhand_t *ih = &rmixl_intrhand[vec]; 837 printf("vec %d: func %p, arg %p, irq %d, ipl %d, mask %#x\n", 838 vec, ih->ih_func, ih->ih_arg, ih->ih_irq, ih->ih_ipl, 839 ih->ih_cpumask); 840 return 0; 841 } 842 int 843 rmixl_intrhand_print(void) 844 { 845 for (int vec=0; vec < NINTRVECS ; vec++) 846 rmixl_intrhand_print_subr(vec); 847 return 0; 848 } 849 int 850 rmixl_irt_print(void) 851 { 852 printf("%s:\n", __func__); 853 for (int irt=0; irt < NIRTS ; irt++) 854 rmixl_irt_entry_print(irt); 855 return 0; 856 } 857 #endif 858
Indexes created Wed Oct 15 16:09:53 GMT 2025