| History log of /src/sys/arch/mips/rmi/rmixl_intr.c |
| Revision | | Date | Author | Comments |
| 1.15 |
| 29-Sep-2022 |
skrll | Remove unnecessary include of <sys/malloc.h>.
|
| 1.14 |
| 29-Sep-2022 |
skrll | Trailing whitespace
|
| 1.13 |
| 09-Apr-2022 |
riastradh | mips/rmixl: Insert appropriate membars around IPIs.
|
| 1.12 |
| 26-Aug-2016 |
skrll | Adjust evbmips_iointr to pass a clockframe pointer and use it for
pwmclock @ voyager.
Suggested by matt@
Hi macallan!
|
| 1.11 |
| 01-Aug-2016 |
dholland | PR 51384 David Binderman: don't shift into the void
|
| 1.10 |
| 23-Apr-2016 |
skrll | branches: 1.10.2;
Merge nick-nhusb
- API / infrastructure changes to support memory management changes.
- Memory management improvements and bug fixes.
- HCDs should now be MP safe
- conversion to KERNHIST based debug
- FS/LS isoc support on ehci(4).
- conversion to kmem(9)
- Some USB 3 support - mostly from Takahiro HAYASHI (t-hash).
- interrupt transfers now get proper DMA operations
- general bug fixes
- kern/48308
- uhub status notification improvements
- umass(4) probe fix (applied to HEAD already)
- ohci(4) short transfer fix
|
| 1.9 |
| 10-Jun-2015 |
matt | Transition from __cpuset_t to kcpuset_t *. This brings the local pmap one
step closer to uvm/pmap, its eventual replacement. Tested on ERLITE MP kernel.
|
| 1.8 |
| 27-Sep-2011 |
jym | branches: 1.8.12; 1.8.30;
Modify *ASSERTMSG() so they are now used as variadic macros. The main goal
is to provide routines that do as KASSERT(9) says: append a message
to the panic format string when the assertion triggers, with optional
arguments.
Fix call sites to reflect the new definition.
Discussed on tech-kern@. See
http://mail-index.netbsd.org/tech-kern/2011/09/07/msg011427.html
|
| 1.7 |
| 10-Jul-2011 |
matt | Fix machine/ includes
|
| 1.6 |
| 01-Jul-2011 |
dyoung | #include <sys/bus.h> instead of <machine/bus.h>.
|
| 1.5 |
| 29-Apr-2011 |
matt | minor constification, format cleanups
|
| 1.4 |
| 14-Apr-2011 |
cliff | - in evbmips_iointr(), call assembly function rmixl_eirr_ack()
to ack the EIRR, instead of using a bunch of asm() here.
- in rmixl_ipi_intr(), remove overly paranoid assert that the given
IPI request is pending; if the request is clear, it was previously processed.
- in rmixl_vecnames_common[], give ipi vectors unique (numbered) names
|
| 1.3 |
| 20-Feb-2011 |
matt | Merge forward from matt-nb5-mips64.
|
| 1.2 |
| 14-Dec-2009 |
matt | branches: 1.2.4; 1.2.6; 1.2.8; 1.2.10;
Merge from matt-nb5-mips64
Merge mips-specific arch files.
|
| 1.1 |
| 13-Sep-2009 |
cliff | branches: 1.1.2;
file rmixl_intr.c was initially added on branch matt-nb5-mips64.
|
| 1.1.2.39 |
| 14-Feb-2014 |
matt | Change KASSERTMSG/KDASSERTMSG to use varadic arguments like HEAD.
panic -> vpanic, add panic wrapper to vpanic.
|
| 1.1.2.38 |
| 05-Nov-2013 |
matt | Add XLP2XX support.
|
| 1.1.2.37 |
| 15-Dec-2012 |
matt | Add initial support for XLP II (XLP2XX/XLP1XX).
|
| 1.1.2.36 |
| 27-Feb-2012 |
matt | Add a test for recursive IPIs.
use __builtin_clzll
|
| 1.1.2.35 |
| 19-Jan-2012 |
matt | Change struct rmixl_cpu_softc to cpu_softc and remove casts.
Fix IPIs.
More FMN cleanup.
|
| 1.1.2.34 |
| 04-Jan-2012 |
matt | Rework Fast Messaging Network support (it's now lockless).
Workaround a problem with bus 0 BAR sizing causing the registers behind
the BAR to become inaccessible.
Move much/most of the startup code from evbmips/rmixl/machdep to
mips/rmi/rmixl_machdep.c
Move the code to find the XLP variant to the early boot so it can be used
early.
8bit and 16bit accessed to PCI bus 0 cause cache errors so chagne the access
of pci mem to 32bits.
|
| 1.1.2.33 |
| 31-Dec-2011 |
matt | Switch to using IST_<foo> instead of private enums.
|
| 1.1.2.32 |
| 31-Dec-2011 |
matt | XLP8xx and XLP3xx have different IRT layouts.
|
| 1.1.2.31 |
| 24-Dec-2011 |
matt | Add XLP support (i2c, console, pci, sdhc works).
|
| 1.1.2.30 |
| 29-Apr-2011 |
matt | Major merge to/from current.
Adds MIPS32/MIPS64 R2 support (24k, 74k, etc.) including COP0_USERLOCAL
Adds support for emulation of rdhwr $3,$29 instruction.
Major cleanup of SMP code. (stable on multi-core / single thread per core)
llsc locking code only used in MP capable kernels.
|
| 1.1.2.29 |
| 08-Feb-2011 |
cliff | - in rmixl_intr_init_clk, use MIPS_INT_MASK_SHIFT instead of 8
when calculating vector number for clock.
|
| 1.1.2.28 |
| 08-Feb-2011 |
cliff | - use mutex_obj_alloc() instead of declaring locks statically
|
| 1.1.2.27 |
| 08-Feb-2011 |
cliff | - remove sc_ih_clk, sc_ih_fmn, sc_ih_ipi from struct rmixl_cpu_softc;
they were unused just taking up space
- rmixl_intr_init_clk() and rmixl_intr_init_ipi() are now type void
|
| 1.1.2.26 |
| 08-Feb-2011 |
cliff | - distinguish between cpuid and cpu index.
|
| 1.1.2.25 |
| 05-Feb-2011 |
cliff | - include opt_multiprocessor.h for MULTIPROCESSOR dependency
- use seperate vectors for various IPI tags, instead of all piling on one.
this theoretically allows different functions to interrupt at different
priorities. the fmn vector number got rippled up in the process.
- add rmixl_ipi_lock to serialize access to RMIXL_PIC_IPIBASE
- add rmixl_intr_lock to serialize access to rest of PIC and rmixl_intrhand[]
- include mips/cpuset.h and use CPUSET_* macros for cpus_running &etc.
|
| 1.1.2.24 |
| 20-Sep-2010 |
cliff | - rmixl_intrhand_t is valid only if ih_func is non-NULL;
set valid at end of rmixl_vec_establish and
set invalid at start of rmixl_vec_disestablish
to allow lockless check if valid in dispatch.
|
| 1.1.2.23 |
| 26-Aug-2010 |
rmind | Fix non-DEBUG/DIAGNOSTIC builds of RMI mips64.
|
| 1.1.2.22 |
| 10-Jun-2010 |
cliff | - remove rmixl_spl_init_cpu calls from rmixl_intr_init_cpu
because rmixl_intr_init_cpu only runs on cpu#0.
rmixl_spl_init_cpu calls are now done in cpu_rmixl_atach (for cpu#0)
or cpu_rmixl_hatch (for other cpus).
- in evbmips_iointr, be sure to mask out count/compare interrupt
along with softints (these are handled elsewhere)
and improve coments
- fix bug in rmixl_send_ipi: 'cpus_running' is bit-indexed
by ci_index, not ci_cpuid
|
| 1.1.2.21 |
| 28-May-2010 |
cliff | rmixl_spl.S:
- where possible, stop using CP0 STATUS to disable all interrupts,zero EIMR instead. more efficient since less meddling with CP0.
assume STATUS[IE] is normally set.
- add rmixl_spl_init_cpu(), to initialize cp0 interrupt control for this cpu
rmixl_intr.c:
- rmixl_intr_init_cpu() calls rmixl_spl_init_cpu()
to set up CP0 interrupt controls for this cpu
|
| 1.1.2.20 |
| 21-May-2010 |
cliff | - rename IRT based interrupts to "pic int ..."
- rename rmixl_vecnames_common to "vec ..."
- move ipl_eimr_map table print into rmixl_ipl_eimr_map_print()
- consolidate debug print funcs at the end of the file
- 'irq' -- being somewhat ambiguous -- renamed to 'irt' throughout
to reflect use as IRT index
- IRT-based interrupts are moved to EIRR/EIMR vectors (bits) 32..63
to avoid all opverlap with EIRR/EIMR bits 0..7 which are CAUSE[8..15].
To date this has been a non-issue since we aren't using the
watchdog or timers there. non-IRT interrupts (FMN and IPI) are moved
to unused portion vectors 8, 9
- in rmixl_intr_init_cpu, instead of writing 0 to EIRR, ack with bits read
(excluding CAUSE[8..15] bits) as defense against possible stale
interrupts inherited from firmware (paranoid -- we aren't seeing any).
- rmixl_irt_establish gets a 'vec' arg for use in IRTENTRYC1 reg
(no longer assume vec = irt)
- set/clear irq bits in ipl_eimr_map[] during interrupt establish/disestablish
- in evbmips_iointr(), mask off ints enabled at higher ipl; we only
dispatch interrupts at highest enabling ipl.
|
| 1.1.2.19 |
| 06-May-2010 |
cliff | fix pcie IRQ assignments for XLS2xx
|
| 1.1.2.18 |
| 01-May-2010 |
cliff | in evbmips_iointr() for RMI, where we ack the EIRR,
replace (relatively expensive) splhigh()/splx()
protection with (more efficient) EIMR-based disable/restore.
|
| 1.1.2.17 |
| 12-Apr-2010 |
cliff | - establishing an ISR now takes 'mpsafe' arg
- obtain/release kernel lock around calls to non-mpsafe ISRs
|
| 1.1.2.16 |
| 29-Mar-2010 |
cliff | - add IRT-based interrupt names for XLR
- rmixl_intr_string() calls chip-type-specific functions
to get appropriate names table
|
| 1.1.2.15 |
| 21-Mar-2010 |
cliff | - rework to make full use of RMI extended interrupt management
provided by EIRR/EIMR registers
- depends on rmixl_spl.S
- add support for IRT based interrupt routing; for now we are still routing
all IRT interrupts to CPU#0.
- note that count/compare clock, IPI and FMN are handled by each CPU since
these are local interrupt sources.
- further changes are still needed for XLR and XLP support
|
| 1.1.2.14 |
| 28-Feb-2010 |
matt | Add #define __INTR_PRIVATE
|
| 1.1.2.13 |
| 23-Feb-2010 |
matt | Instead of a read-only ipl_sr_bits, define a ipl_sr_map struct and fill that
in the interrupt init routine. There's a default ipl_sr_map will operate
correctly, but isn't performant.
|
| 1.1.2.12 |
| 16-Feb-2010 |
matt | Add __HAVE_PREEMPTION support for NetBSD/mips. Kill IPL_PREEMPT since it
isn't needed.
|
| 1.1.2.11 |
| 15-Feb-2010 |
matt | Adapt to the new interrupt framework for NetBSD/mips.
|
| 1.1.2.10 |
| 06-Feb-2010 |
cliff | - when establishing an intr, if malloc fails, be sure to splx on the way out
- in interrupt dispatch, when ack-ing EIRR, preserve the softint bits
|
| 1.1.2.9 |
| 06-Feb-2010 |
matt | A little constification and remove some old softintr cruft.
|
| 1.1.2.8 |
| 29-Jan-2010 |
cliff | - be more thorough about 'mips_cpu_id' based variations
- rip out pcie interrupt related debug stuff
- start thinking about MULTIPROCESSOR IRT entries in rmixl_intr_irt_init()
|
| 1.1.2.7 |
| 20-Jan-2010 |
matt | Adjust things to the new world order.
|
| 1.1.2.6 |
| 12-Dec-2009 |
cliff | - in ipl_sr_bits[], ensure ints for unused vectors are always disabled
and ensure that MIPS_INT_MASK_5 (clock) is enabled as needed
- break IRT entry management out into routines;
this allows e.g. setup of IRT entry for clock without all the
rest of rmixl_intr_irt_establish()
- evbmips_intr_init() now creates IRT entry for mips3 clock interrupt
|
| 1.1.2.5 |
| 13-Nov-2009 |
cliff | - KASSERT this interrupt code being used on XLS family CPU
|
| 1.1.2.4 |
| 09-Nov-2009 |
cliff | - multiple changes; make interrupts work
|
| 1.1.2.3 |
| 25-Sep-2009 |
cliff | chop out some test printf's
|
| 1.1.2.2 |
| 25-Sep-2009 |
cliff | rmixl gets interrupt support
|
| 1.1.2.1 |
| 13-Sep-2009 |
cliff | add netbsd support for RMI XLS6ATX_7A board and XL SoC family
|
| 1.2.10.1 |
| 05-Mar-2011 |
bouyer | Sync with HEAD
|
| 1.2.8.1 |
| 06-Jun-2011 |
jruoho | Sync with HEAD.
|
| 1.2.6.3 |
| 31-May-2011 |
rmind | sync with head
|
| 1.2.6.2 |
| 21-Apr-2011 |
rmind | sync with head
|
| 1.2.6.1 |
| 05-Mar-2011 |
rmind | sync with head
|
| 1.2.4.2 |
| 11-Mar-2010 |
yamt | sync with head
|
| 1.2.4.1 |
| 14-Dec-2009 |
yamt | file rmixl_intr.c was added on branch yamt-nfs-mp on 2010-03-11 15:02:41 +0000
|
| 1.8.30.2 |
| 05-Oct-2016 |
skrll | Sync with HEAD
|
| 1.8.30.1 |
| 22-Sep-2015 |
skrll | Sync with HEAD
|
| 1.8.12.1 |
| 03-Dec-2017 |
jdolecek | update from HEAD
|
| 1.10.2.1 |
| 06-Aug-2016 |
pgoyette | Sync with HEAD
|
