rmixl_intr.c revision 1.1.2.17
1 /* $NetBSD: rmixl_intr.c,v 1.1.2.17 2010/04/12 22:40:55 cliff Exp $ */ 2 3 /*- 4 * Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or 8 * without modification, are permitted provided that the following 9 * conditions are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above 13 * copyright notice, this list of conditions and the following 14 * disclaimer in the documentation and/or other materials provided 15 * with the distribution. 16 * 3. The names of the authors may not be used to endorse or promote 17 * products derived from this software without specific prior 18 * written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY 21 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 23 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, 25 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 27 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 29 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 30 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 31 * OF SUCH DAMAGE. 32 */ 33 /*- 34 * Copyright (c) 2001 The NetBSD Foundation, Inc. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to The NetBSD Foundation 38 * by Jason R. Thorpe. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 49 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 50 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 51 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 52 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 53 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 54 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 55 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 56 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 57 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 58 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 59 * POSSIBILITY OF SUCH DAMAGE. 60 */ 61 62 /* 63 * Platform-specific interrupt support for the RMI XLP, XLR, XLS 64 */ 65 66 #include <sys/cdefs.h> 67 __KERNEL_RCSID(0, "$NetBSD: rmixl_intr.c,v 1.1.2.17 2010/04/12 22:40:55 cliff Exp $"); 68 69 #include "opt_ddb.h" 70 #define __INTR_PRIVATE 71 72 #include <sys/param.h> 73 #include <sys/queue.h> 74 #include <sys/malloc.h> 75 #include <sys/systm.h> 76 #include <sys/device.h> 77 #include <sys/kernel.h> 78 #include <sys/atomic.h> 79 #include <sys/cpu.h> 80 81 #include <machine/bus.h> 82 #include <machine/intr.h> 83 84 #include <mips/cpu.h> 85 #include <mips/locore.h> 86 87 #include <mips/rmi/rmixlreg.h> 88 #include <mips/rmi/rmixlvar.h> 89 90 #include <mips/rmi/rmixl_cpuvar.h> 91 #include <mips/rmi/rmixl_intr.h> 92 93 #include <dev/pci/pcireg.h> 94 #include <dev/pci/pcivar.h> 95 96 // #define IOINTR_DEBUG 1 97 #ifdef IOINTR_DEBUG 98 int iointr_debug = IOINTR_DEBUG; 99 # define DPRINTF(x) do { if (iointr_debug) printf x ; } while(0) 100 #else 101 # define DPRINTF(x) 102 #endif 103 104 #define RMIXL_PICREG_READ(off) \ 105 RMIXL_IOREG_READ(RMIXL_IO_DEV_PIC + (off)) 106 #define RMIXL_PICREG_WRITE(off, val) \ 107 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PIC + (off), (val)) 108 109 /* 110 * do not clear these when acking EIRR 111 * (otherwise they get lost) 112 */ 113 #define RMIXL_EIRR_PRESERVE_MASK \ 114 ((MIPS_INT_MASK_5|MIPS_SOFT_INT_MASK) >> 8) 115 116 /* 117 * IRT assignments depends on the RMI chip family 118 * (XLS1xx vs. XLS2xx vs. XLS3xx vs. XLS6xx) 119 * use the right irq (and display string table) for the CPU that's running. 120 */ 121 122 /* 123 * rmixl_irtnames_xlrxxx 124 * - use for XLRxxx 125 */ 126 static const char * const rmixl_irtnames_xlrxxx[NIRTS] = { 127 "int 0 (watchdog)", /* 0 */ 128 "int 1 (timer0)", /* 1 */ 129 "int 2 (timer1)", /* 2 */ 130 "int 3 (timer2)", /* 3 */ 131 "int 4 (timer3)", /* 4 */ 132 "int 5 (timer4)", /* 5 */ 133 "int 6 (timer5)", /* 6 */ 134 "int 7 (timer6)", /* 7 */ 135 "int 8 (timer7)", /* 8 */ 136 "int 9 (uart0)", /* 9 */ 137 "int 10 (uart1)", /* 10 */ 138 "int 11 (i2c0)", /* 11 */ 139 "int 12 (i2c1)", /* 12 */ 140 "int 13 (pcmcia)", /* 13 */ 141 "int 14 (gpio)", /* 14 */ 142 "int 15 (hyper)", /* 15 */ 143 "int 16 (pcix)", /* 16 */ 144 "int 17 (gmac0)", /* 17 */ 145 "int 18 (gmac1)", /* 18 */ 146 "int 19 (gmac2)", /* 19 */ 147 "int 20 (gmac3)", /* 20 */ 148 "int 21 (xgs0)", /* 21 */ 149 "int 22 (xgs1)", /* 22 */ 150 "int 23 (irq23)", /* 23 */ 151 "int 24 (hyper_fatal)", /* 24 */ 152 "int 25 (bridge_aerr)", /* 25 */ 153 "int 26 (bridge_berr)", /* 26 */ 154 "int 27 (bridge_tb)", /* 27 */ 155 "int 28 (bridge_nmi)", /* 28 */ 156 "int 29 (bridge_sram_derr)", /* 29 */ 157 "int 30 (gpio_fatal)", /* 30 */ 158 "int 31 (reserved)", /* 31 */ 159 }; 160 161 /* 162 * rmixl_irtnames_xls1xx 163 * - use for XLS1xx, XLS2xx, XLS4xx-Lite 164 */ 165 static const char * const rmixl_irtnames_xls1xx[NIRTS] = { 166 "int 0 (watchdog)", /* 0 */ 167 "int 1 (timer0)", /* 1 */ 168 "int 2 (timer1)", /* 2 */ 169 "int 3 (timer2)", /* 3 */ 170 "int 4 (timer3)", /* 4 */ 171 "int 5 (timer4)", /* 5 */ 172 "int 6 (timer5)", /* 6 */ 173 "int 7 (timer6)", /* 7 */ 174 "int 8 (timer7)", /* 8 */ 175 "int 9 (uart0)", /* 9 */ 176 "int 10 (uart1)", /* 10 */ 177 "int 11 (i2c0)", /* 11 */ 178 "int 12 (i2c1)", /* 12 */ 179 "int 13 (pcmcia)", /* 13 */ 180 "int 14 (gpio_a)", /* 14 */ 181 "int 15 (irq15)", /* 15 */ 182 "int 16 (bridge_tb)", /* 16 */ 183 "int 17 (gmac0)", /* 17 */ 184 "int 18 (gmac1)", /* 18 */ 185 "int 19 (gmac2)", /* 19 */ 186 "int 20 (gmac3)", /* 20 */ 187 "int 21 (irq21)", /* 21 */ 188 "int 22 (irq22)", /* 22 */ 189 "int 23 (irq23)", /* 23 */ 190 "int 24 (irq24)", /* 24 */ 191 "int 25 (bridge_err)", /* 25 */ 192 "int 26 (pcie_link0)", /* 26 */ 193 "int 27 (pcie_link1)", /* 27 */ 194 "int 28 (irq28)", /* 28 */ 195 "int 29 (pcie_err)", /* 29 */ 196 "int 30 (gpio_b)", /* 30 */ 197 "int 31 (usb)", /* 31 */ 198 }; 199 200 /* 201 * rmixl_irtnames_xls4xx: 202 * - use for XLS4xx, XLS6xx 203 */ 204 static const char * const rmixl_irtnames_xls4xx[NIRTS] = { 205 "int 0 (watchdog)", /* 0 */ 206 "int 1 (timer0)", /* 1 */ 207 "int 2 (timer1)", /* 2 */ 208 "int 3 (timer2)", /* 3 */ 209 "int 4 (timer3)", /* 4 */ 210 "int 5 (timer4)", /* 5 */ 211 "int 6 (timer5)", /* 6 */ 212 "int 7 (timer6)", /* 7 */ 213 "int 8 (timer7)", /* 8 */ 214 "int 9 (uart0)", /* 9 */ 215 "int 10 (uart1)", /* 10 */ 216 "int 11 (i2c0)", /* 11 */ 217 "int 12 (i2c1)", /* 12 */ 218 "int 13 (pcmcia)", /* 13 */ 219 "int 14 (gpio_a)", /* 14 */ 220 "int 15 (irq15)", /* 15 */ 221 "int 16 (bridge_tb)", /* 16 */ 222 "int 17 (gmac0)", /* 17 */ 223 "int 18 (gmac1)", /* 18 */ 224 "int 19 (gmac2)", /* 19 */ 225 "int 20 (gmac3)", /* 20 */ 226 "int 21 (irq21)", /* 21 */ 227 "int 22 (irq22)", /* 22 */ 228 "int 23 (irq23)", /* 23 */ 229 "int 24 (irq24)", /* 24 */ 230 "int 25 (bridge_err)", /* 25 */ 231 "int 26 (pcie_link0)", /* 26 */ 232 "int 27 (pcie_link1)", /* 27 */ 233 "int 28 (pcie_link2)", /* 28 */ 234 "int 29 (pcie_link3)", /* 29 */ 235 "int 30 (gpio_b)", /* 30 */ 236 "int 31 (usb)", /* 31 */ 237 }; 238 239 /* 240 * rmixl_vecnames_common: 241 * - use for unknown cpu implementation 242 * - covers all vectors, not just IRT intrs 243 */ 244 static const char * const rmixl_vecnames_common[NINTRVECS] = { 245 "int 0", /* 0 */ 246 "int 1", /* 1 */ 247 "int 2", /* 2 */ 248 "int 3", /* 3 */ 249 "int 4", /* 4 */ 250 "int 5", /* 5 */ 251 "int 6", /* 6 */ 252 "int 7", /* 7 */ 253 "int 8", /* 8 */ 254 "int 9", /* 9 */ 255 "int 10", /* 10 */ 256 "int 11", /* 11 */ 257 "int 12", /* 12 */ 258 "int 13", /* 13 */ 259 "int 14", /* 14 */ 260 "int 15", /* 15 */ 261 "int 16", /* 16 */ 262 "int 17", /* 17 */ 263 "int 18", /* 18 */ 264 "int 19", /* 19 */ 265 "int 20", /* 20 */ 266 "int 21", /* 21 */ 267 "int 22", /* 22 */ 268 "int 23", /* 23 */ 269 "int 24", /* 24 */ 270 "int 25", /* 25 */ 271 "int 26", /* 26 */ 272 "int 27", /* 27 */ 273 "int 28", /* 28 */ 274 "int 29", /* 29 */ 275 "int 30", /* 30 */ 276 "int 31", /* 31 */ 277 "int 32 (ipi)", /* 32 */ 278 "int 33 (fmn)", /* 33 */ 279 "int 34", /* 34 */ 280 "int 35", /* 35 */ 281 "int 36", /* 36 */ 282 "int 37", /* 37 */ 283 "int 38", /* 38 */ 284 "int 39", /* 39 */ 285 "int 40", /* 40 */ 286 "int 41", /* 41 */ 287 "int 42", /* 42 */ 288 "int 43", /* 43 */ 289 "int 44", /* 44 */ 290 "int 45", /* 45 */ 291 "int 46", /* 46 */ 292 "int 47", /* 47 */ 293 "int 48", /* 48 */ 294 "int 49", /* 49 */ 295 "int 50", /* 50 */ 296 "int 51", /* 51 */ 297 "int 52", /* 52 */ 298 "int 53", /* 53 */ 299 "int 54", /* 54 */ 300 "int 55", /* 55 */ 301 "int 56", /* 56 */ 302 "int 57", /* 57 */ 303 "int 58", /* 58 */ 304 "int 59", /* 59 */ 305 "int 60", /* 60 */ 306 "int 61", /* 61 */ 307 "int 62", /* 63 */ 308 "int 63", /* 63 */ 309 }; 310 311 /* 312 * mask of CPUs attached 313 * once they are attached, this var is read-only so mp safe 314 */ 315 static uint32_t cpu_present_mask; 316 317 rmixl_intrhand_t rmixl_intrhand[NINTRVECS]; 318 319 #ifdef DIAGNOSTIC 320 static int rmixl_pic_init_done; 321 #endif 322 323 324 static const char *rmixl_intr_string_xlr(int); 325 static const char *rmixl_intr_string_xls(int); 326 static uint32_t rmixl_irt_thread_mask(int); 327 static void rmixl_irt_init(int); 328 static void rmixl_irt_disestablish(int); 329 static void rmixl_irt_establish(int, int, 330 rmixl_intr_trigger_t, rmixl_intr_polarity_t); 331 332 #ifdef MULTIPROCESSOR 333 static int rmixl_send_ipi(struct cpu_info *, int); 334 static int rmixl_ipi_intr(void *); 335 #endif 336 337 #if defined(IOINTR_DEBUG) || defined(DIAGNOSTIC) 338 int rmixl_intrhand_print_subr(int); 339 int rmixl_intrhand_print(void); 340 int rmixl_irt_print(void); 341 #endif 342 343 344 static inline u_int 345 dclz(uint64_t val) 346 { 347 int nlz; 348 349 asm volatile("dclz %0, %1;" 350 : "=r"(nlz) : "r"(val)); 351 352 return nlz; 353 } 354 355 static inline void 356 rmixl_irt_entry_print(u_int irq) 357 { 358 #if defined(IOINTR_DEBUG) || defined(DDB) 359 uint32_t c0, c1; 360 361 if ((irq < 0) || (irq > NIRTS)) 362 return; 363 c0 = RMIXL_PICREG_READ(RMIXL_PIC_IRTENTRYC0(irq)); 364 c1 = RMIXL_PICREG_READ(RMIXL_PIC_IRTENTRYC1(irq)); 365 printf("irt[%d]: %#x, %#x\n", irq, c0, c1); 366 #endif 367 } 368 369 void 370 evbmips_intr_init(void) 371 { 372 uint32_t r; 373 374 KASSERT(cpu_rmixlr(mips_options.mips_cpu) 375 || cpu_rmixls(mips_options.mips_cpu)); 376 377 #ifdef IOINTR_DEBUG 378 printf("IPL_NONE=%d, mask %#"PRIx64"\n", 379 IPL_NONE, ipl_eimr_map[IPL_NONE]); 380 printf("IPL_SOFTCLOCK=%d, mask %#"PRIx64"\n", 381 IPL_SOFTCLOCK, ipl_eimr_map[IPL_SOFTCLOCK]); 382 printf("IPL_SOFTNET=%d, mask %#"PRIx64"\n", 383 IPL_SOFTNET, ipl_eimr_map[IPL_SOFTNET]); 384 printf("IPL_VM=%d, mask %#"PRIx64"\n", 385 IPL_VM, ipl_eimr_map[IPL_VM]); 386 printf("IPL_SCHED=%d, mask %#"PRIx64"\n", 387 IPL_SCHED, ipl_eimr_map[IPL_HIGH]); 388 printf("IPL_HIGH=%d, mask %#"PRIx64"\n", 389 IPL_HIGH, ipl_eimr_map[IPL_NONE]); 390 #endif 391 392 #ifdef DIAGNOSTIC 393 if (rmixl_pic_init_done != 0) 394 panic("%s: rmixl_pic_init_done %d", 395 __func__, rmixl_pic_init_done); 396 #endif 397 398 /* 399 * initialize (zero) all IRT Entries in the PIC 400 */ 401 for (int i=0; i < NIRTS; i++) 402 rmixl_irt_init(i); 403 404 /* 405 * disable watchdog NMI, timers 406 * 407 * XXX 408 * WATCHDOG_ENB is preserved because clearing it causes 409 * hang on the XLS616 (but not on the XLS408) 410 */ 411 r = RMIXL_PICREG_READ(RMIXL_PIC_CONTROL); 412 r &= RMIXL_PIC_CONTROL_RESV|RMIXL_PIC_CONTROL_WATCHDOG_ENB; 413 RMIXL_PICREG_WRITE(RMIXL_PIC_CONTROL, r); 414 415 #ifdef DIAGNOSTIC 416 rmixl_pic_init_done = 1; 417 #endif 418 419 } 420 421 /* 422 * establish vector for mips3 count/compare clock interrupt 423 * this ensures we enable in EIRR, 424 * even though cpu_intr() handles the interrupt 425 * note the 'mpsafe' arg here is a placeholder only 426 */ 427 void * 428 rmixl_intr_init_clk(void) 429 { 430 int vec = ffs(MIPS_INT_MASK_5 >> 8) - 1; 431 void *ih = rmixl_vec_establish(vec, 0, IPL_SCHED, NULL, NULL, false); 432 if (ih == NULL) 433 panic("%s: establish vec %d failed", __func__, vec); 434 435 return ih; 436 } 437 438 #ifdef MULTIPROCESSOR 439 /* 440 * establish IPI interrupt and send function 441 */ 442 void * 443 rmixl_intr_init_ipi(void) 444 { 445 void *ih = rmixl_vec_establish(RMIXL_INTRVEC_IPI, -1, IPL_SCHED, 446 rmixl_ipi_intr, NULL, false); 447 if (ih == NULL) 448 panic("%s: establish vec %d failed", 449 __func__, RMIXL_INTRVEC_IPI); 450 451 mips_locoresw.lsw_send_ipi = rmixl_send_ipi; 452 453 return ih; 454 } 455 #endif /* MULTIPROCESSOR */ 456 457 /* 458 * initialize per-cpu interrupt stuff in softc 459 * accumulate per-cpu bits in 'cpu_present_mask' 460 */ 461 void 462 rmixl_intr_init_cpu(struct cpu_info *ci) 463 { 464 struct rmixl_cpu_softc *sc = (void *)ci->ci_softc; 465 KASSERT(sc != NULL); 466 467 /* zero the EIRR ? */ 468 uint64_t eirr = 0; 469 asm volatile("dmtc0 %0, $9, 6;" :: "r"(eirr)); 470 471 for (int vec=0; vec < NINTRVECS; vec++) 472 evcnt_attach_dynamic(&sc->sc_vec_evcnts[vec], 473 EVCNT_TYPE_INTR, NULL, 474 device_xname(sc->sc_dev), 475 rmixl_intr_string(vec)); 476 477 KASSERT(ci->ci_cpuid < (sizeof(cpu_present_mask) * 8)); 478 cpu_present_mask |= 1 << ci->ci_cpuid; 479 } 480 481 /* 482 * rmixl_intr_string - return pointer to display name of a PIC-based interrupt 483 */ 484 const char * 485 rmixl_intr_string(int irq) 486 { 487 if (irq < 0 || irq >= NINTRVECS) 488 panic("%s: irq index %d out of range, max %d", 489 __func__, irq, NIRTS - 1); 490 491 if (irq >= NIRTS) 492 return rmixl_vecnames_common[irq]; 493 494 switch(cpu_rmixl_chip_type(mips_options.mips_cpu)) { 495 case CIDFL_RMI_TYPE_XLR: 496 return rmixl_intr_string_xlr(irq); 497 case CIDFL_RMI_TYPE_XLS: 498 return rmixl_intr_string_xls(irq); 499 case CIDFL_RMI_TYPE_XLP: 500 panic("%s: RMI XLP not yet supported", __func__); 501 } 502 503 return "undefined"; /* appease gcc */ 504 } 505 506 static const char * 507 rmixl_intr_string_xlr(int irq) 508 { 509 return rmixl_irtnames_xlrxxx[irq]; 510 } 511 512 static const char * 513 rmixl_intr_string_xls(int irq) 514 { 515 const char *name; 516 517 switch (MIPS_PRID_IMPL(mips_options.mips_cpu_id)) { 518 case MIPS_XLS104: 519 case MIPS_XLS108: 520 case MIPS_XLS204: 521 case MIPS_XLS208: 522 case MIPS_XLS404LITE: 523 case MIPS_XLS408LITE: 524 name = rmixl_irtnames_xls1xx[irq]; 525 break; 526 case MIPS_XLS404: 527 case MIPS_XLS408: 528 case MIPS_XLS416: 529 case MIPS_XLS608: 530 case MIPS_XLS616: 531 name = rmixl_irtnames_xls4xx[irq]; 532 break; 533 default: 534 name = rmixl_vecnames_common[irq]; 535 break; 536 } 537 538 return name; 539 } 540 541 /* 542 * rmixl_irt_thread_mask 543 * 544 * given a bitmask of cpus, return a, IRT thread mask 545 */ 546 static uint32_t 547 rmixl_irt_thread_mask(int cpumask) 548 { 549 uint32_t irtc0; 550 551 #if defined(MULTIPROCESSOR) 552 #ifndef NOTYET 553 if (cpumask == -1) 554 return 1; /* XXX TMP FIXME */ 555 #endif 556 557 /* 558 * discount cpus not present 559 */ 560 cpumask &= cpu_present_mask; 561 562 switch (MIPS_PRID_IMPL(mips_options.mips_cpu_id)) { 563 case MIPS_XLS104: 564 case MIPS_XLS204: 565 case MIPS_XLS404: 566 case MIPS_XLS404LITE: 567 irtc0 = ((cpumask >> 2) << 4) | (cpumask & __BITS(1,0)); 568 irtc0 &= (__BITS(5,4) | __BITS(1,0)); 569 break; 570 case MIPS_XLS108: 571 case MIPS_XLS208: 572 case MIPS_XLS408: 573 case MIPS_XLS408LITE: 574 case MIPS_XLS608: 575 irtc0 = cpumask & __BITS(7,0); 576 break; 577 case MIPS_XLS416: 578 case MIPS_XLS616: 579 irtc0 = cpumask & __BITS(15,0); 580 break; 581 default: 582 panic("%s: unknown cpu ID %#x\n", __func__, 583 mips_options.mips_cpu_id); 584 } 585 #else 586 irtc0 = 1; 587 #endif /* MULTIPROCESSOR */ 588 589 return irtc0; 590 } 591 592 /* 593 * rmixl_irt_init 594 * - invalidate IRT Entry for irq 595 * - unmask Thread#0 in low word (assume we only have 1 thread) 596 */ 597 static void 598 rmixl_irt_init(int irq) 599 { 600 RMIXL_PICREG_WRITE(RMIXL_PIC_IRTENTRYC1(irq), 0); /* high word */ 601 RMIXL_PICREG_WRITE(RMIXL_PIC_IRTENTRYC0(irq), 0); /* low word */ 602 } 603 604 /* 605 * rmixl_irt_disestablish 606 * - invalidate IRT Entry for irq 607 * - writes to IRTENTRYC1 only; leave IRTENTRYC0 as-is 608 */ 609 static void 610 rmixl_irt_disestablish(int irq) 611 { 612 DPRINTF(("%s: irq %d, irtc1 %#x\n", __func__, irq, 0)); 613 rmixl_irt_init(irq); 614 } 615 616 /* 617 * rmixl_irt_establish 618 * - construct an IRT Entry for irq and write to PIC 619 */ 620 static void 621 rmixl_irt_establish(int irq, int cpumask, rmixl_intr_trigger_t trigger, 622 rmixl_intr_polarity_t polarity) 623 { 624 uint32_t irtc1; 625 uint32_t irtc0; 626 627 switch (trigger) { 628 case RMIXL_TRIG_EDGE: 629 case RMIXL_TRIG_LEVEL: 630 break; 631 default: 632 panic("%s: bad trigger %d\n", __func__, trigger); 633 } 634 635 switch (polarity) { 636 case RMIXL_POLR_RISING: 637 case RMIXL_POLR_HIGH: 638 case RMIXL_POLR_FALLING: 639 case RMIXL_POLR_LOW: 640 break; 641 default: 642 panic("%s: bad polarity %d\n", __func__, polarity); 643 } 644 645 /* 646 * XXX IRT entries are not shared 647 */ 648 KASSERT(RMIXL_PICREG_READ(RMIXL_PIC_IRTENTRYC0(irq)) == 0); 649 KASSERT(RMIXL_PICREG_READ(RMIXL_PIC_IRTENTRYC1(irq)) == 0); 650 651 irtc0 = rmixl_irt_thread_mask(cpumask); 652 653 irtc1 = RMIXL_PIC_IRTENTRYC1_VALID; 654 irtc1 |= RMIXL_PIC_IRTENTRYC1_GL; /* local */ 655 656 if (trigger == RMIXL_TRIG_LEVEL) 657 irtc1 |= RMIXL_PIC_IRTENTRYC1_TRG; 658 659 if ((polarity == RMIXL_POLR_FALLING) || (polarity == RMIXL_POLR_LOW)) 660 irtc1 |= RMIXL_PIC_IRTENTRYC1_P; 661 662 irtc1 |= irq; /* route to vector 'irq' */ 663 664 /* 665 * write IRT Entry to PIC 666 */ 667 DPRINTF(("%s: irq %d, irtc0 %#x, irtc1 %#x\n", 668 __func__, irq, irtc0, irtc1)); 669 RMIXL_PICREG_WRITE(RMIXL_PIC_IRTENTRYC0(irq), irtc0); /* low word */ 670 RMIXL_PICREG_WRITE(RMIXL_PIC_IRTENTRYC1(irq), irtc1); /* high word */ 671 } 672 673 void * 674 rmixl_vec_establish(int vec, int cpumask, int ipl, 675 int (*func)(void *), void *arg, bool mpsafe) 676 { 677 rmixl_intrhand_t *ih; 678 int s; 679 680 DPRINTF(("%s: vec %d, cpumask %#x, ipl %d, func %p, arg %p, " 681 "vec %d\n", 682 __func__, vec, cpumask, ipl, func, arg, vec)); 683 #ifdef DIAGNOSTIC 684 if (rmixl_pic_init_done == 0) 685 panic("%s: called before evbmips_intr_init", __func__); 686 #endif 687 688 /* 689 * check args 690 */ 691 if (vec < 0 || vec >= NINTRVECS) 692 panic("%s: vec %d out of range, max %d", 693 __func__, vec, NINTRVECS - 1); 694 if (ipl <= 0 || ipl >= _IPL_N) 695 panic("%s: ipl %d out of range, min %d, max %d", 696 __func__, ipl, 1, _IPL_N - 1); 697 698 s = splhigh(); 699 700 ih = &rmixl_intrhand[vec]; 701 702 ih->ih_func = func; 703 ih->ih_arg = arg; 704 ih->ih_mpsafe = mpsafe; 705 ih->ih_irq = vec; 706 ih->ih_ipl = ipl; 707 ih->ih_cpumask = cpumask; 708 709 splx(s); 710 711 return ih; 712 } 713 714 void * 715 rmixl_intr_establish(int irq, int cpumask, int ipl, 716 rmixl_intr_trigger_t trigger, rmixl_intr_polarity_t polarity, 717 int (*func)(void *), void *arg, bool mpsafe) 718 { 719 rmixl_intrhand_t *ih; 720 int s; 721 722 #ifdef DIAGNOSTIC 723 if (rmixl_pic_init_done == 0) 724 panic("%s: called before rmixl_pic_init_done", __func__); 725 #endif 726 727 /* 728 * check args 729 */ 730 if (irq < 0 || irq >= NINTRVECS) 731 panic("%s: irq %d out of range, max %d", 732 __func__, irq, NIRTS - 1); 733 if (ipl <= 0 || ipl >= _IPL_N) 734 panic("%s: ipl %d out of range, min %d, max %d", 735 __func__, ipl, 1, _IPL_N - 1); 736 737 DPRINTF(("%s: irq %d, ipl %d\n", __func__, irq, ipl)); 738 739 s = splhigh(); 740 741 /* 742 * establish vector 743 */ 744 ih = rmixl_vec_establish(irq, cpumask, ipl, func, arg, mpsafe); 745 746 /* 747 * establish IRT Entry 748 */ 749 if (irq < 32) 750 rmixl_irt_establish(irq, cpumask, trigger, polarity); 751 752 splx(s); 753 754 return ih; 755 } 756 757 void 758 rmixl_vec_disestablish(void *cookie) 759 { 760 rmixl_intrhand_t *ih = cookie; 761 int s; 762 763 KASSERT(ih = &rmixl_intrhand[ih->ih_irq]); 764 765 s = splhigh(); 766 767 ih->ih_func = NULL; /* XXX race */ 768 769 splx(s); 770 } 771 772 void 773 rmixl_intr_disestablish(void *cookie) 774 { 775 rmixl_intrhand_t *ih = cookie; 776 int vec; 777 int s; 778 779 vec = ih->ih_irq; 780 781 KASSERT(ih = &rmixl_intrhand[vec]); 782 783 s = splhigh(); 784 785 /* 786 * disable/invalidate the IRT Entry if needed 787 */ 788 if (vec < 32) 789 rmixl_irt_disestablish(vec); 790 791 /* 792 * disasociate from vector and free the handle 793 */ 794 rmixl_vec_disestablish(cookie); 795 796 splx(s); 797 } 798 799 void 800 evbmips_iointr(int ipl, vaddr_t pc, uint32_t pending) 801 { 802 struct rmixl_cpu_softc *sc = (void *)curcpu()->ci_softc; 803 804 DPRINTF(("%s: cpu%ld: ipl %d, pc %#"PRIxVADDR", pending %#x\n", 805 __func__, cpu_number(), ipl, pc, pending)); 806 807 /* 808 * 'pending' arg is a summary that there is something to do 809 * the real pending status is obtained from EIRR 810 */ 811 KASSERT(pending == MIPS_INT_MASK_1); 812 813 for (;;) { 814 rmixl_intrhand_t *ih; 815 uint64_t eirr; 816 uint64_t vecbit; 817 int vec; 818 819 asm volatile("dmfc0 %0, $9, 6;" : "=r"(eirr)); 820 821 #ifdef IOINTR_DEBUG 822 uint64_t eimr; 823 asm volatile("dmfc0 %0, $9, 7;" : "=r"(eimr)); 824 printf("%s: eirr %#"PRIx64", eimr %#"PRIx64", mask %#"PRIx64"\n", 825 __func__, eirr, eimr, ipl_eimr_map[ipl-1]); 826 #endif /* IOINTR_DEBUG */ 827 828 eirr &= ipl_eimr_map[ipl-1]; 829 eirr &= ~(MIPS_SOFT_INT_MASK >> 8); /* mask off soft ints */ 830 if (eirr == 0) 831 break; 832 833 vec = 63 - dclz(eirr); 834 ih = &rmixl_intrhand[vec]; 835 836 int s = splhigh(); 837 vecbit = 1ULL << vec; 838 KASSERT ((vecbit & RMIXL_EIRR_PRESERVE_MASK) == 0); 839 asm volatile("dmfc0 %0, $9, 6;" : "=r"(eirr)); 840 eirr &= RMIXL_EIRR_PRESERVE_MASK; 841 eirr |= vecbit; 842 asm volatile("dmtc0 %0, $9, 6;" :: "r"(eirr)); 843 splx(s); 844 845 if (vec < 32) 846 RMIXL_PICREG_WRITE(RMIXL_PIC_INTRACK, 847 (uint32_t)vecbit); 848 849 if (ih->ih_func != NULL) { 850 #ifdef MULTIPROCESSOR 851 if (ih->ih_mpsafe) { 852 (void)(*ih->ih_func)(ih->ih_arg); 853 } else { 854 KERNEL_LOCK(1, NULL); 855 (void)(*ih->ih_func)(ih->ih_arg); 856 KERNEL_UNLOCK_ONE(NULL); 857 } 858 #else 859 (void)(*ih->ih_func)(ih->ih_arg); 860 #endif /* MULTIPROCESSOR */ 861 } 862 863 sc->sc_vec_evcnts[vec].ev_count++; 864 } 865 } 866 867 #ifdef MULTIPROCESSOR 868 static int 869 rmixl_send_ipi(struct cpu_info *ci, int tag) 870 { 871 const cpuid_t cpu = ci->ci_cpuid; 872 uint32_t core = (uint32_t)(cpu >> 2); 873 uint32_t thread = (uint32_t)(cpu & __BITS(1,0)); 874 uint64_t req = 1 << tag; 875 uint32_t r; 876 extern volatile u_long cpus_running; 877 878 if ((cpus_running & 1 << ci->ci_cpuid) == 0) 879 return -1; 880 881 KASSERT(tag < NIPIS); 882 883 r = (thread << RMIXL_PIC_IPIBASE_ID_THREAD_SHIFT) 884 | (core << RMIXL_PIC_IPIBASE_ID_CORE_SHIFT) 885 | RMIXL_INTRVEC_IPI; 886 887 atomic_or_64(&ci->ci_request_ipis, req); 888 889 RMIXL_PICREG_WRITE(RMIXL_PIC_IPIBASE, r); 890 891 return 0; 892 } 893 894 static int 895 rmixl_ipi_intr(void *arg) 896 { 897 struct cpu_info * const ci = curcpu(); 898 uint64_t ipi_mask; 899 900 ipi_mask = atomic_swap_64(&ci->ci_request_ipis, 0); 901 if (ipi_mask == 0) 902 return 0; 903 904 ipi_process(ci, ipi_mask); 905 906 return 1; 907 } 908 #endif /* MULTIPROCESSOR */ 909 910 #if defined(DIAGNOSTIC) || defined(IOINTR_DEBUG) 911 int 912 rmixl_intrhand_print_subr(int vec) 913 { 914 rmixl_intrhand_t *ih = &rmixl_intrhand[vec]; 915 printf("vec %d: func %p, arg %p, irq %d, ipl %d, mask %#x\n", 916 vec, ih->ih_func, ih->ih_arg, ih->ih_irq, ih->ih_ipl, 917 ih->ih_cpumask); 918 return 0; 919 } 920 int 921 rmixl_intrhand_print(void) 922 { 923 for (int vec=0; vec < NINTRVECS ; vec++) 924 rmixl_intrhand_print_subr(vec); 925 return 0; 926 } 927 int 928 rmixl_irt_print(void) 929 { 930 printf("%s:\n", __func__); 931 for (int irt=0; irt < NIRTS ; irt++) 932 rmixl_irt_entry_print(irt); 933 return 0; 934 } 935 #endif 936
Indexes created Wed Oct 15 16:09:53 GMT 2025