rmixl_intr.c revision 1.1.2.24
1 /* $NetBSD: rmixl_intr.c,v 1.1.2.24 2010/09/20 19:41:05 cliff Exp $ */ 2 3 /*- 4 * Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or 8 * without modification, are permitted provided that the following 9 * conditions are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above 13 * copyright notice, this list of conditions and the following 14 * disclaimer in the documentation and/or other materials provided 15 * with the distribution. 16 * 3. The names of the authors may not be used to endorse or promote 17 * products derived from this software without specific prior 18 * written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY 21 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 23 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, 25 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 27 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 29 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 30 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 31 * OF SUCH DAMAGE. 32 */ 33 /*- 34 * Copyright (c) 2001 The NetBSD Foundation, Inc. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to The NetBSD Foundation 38 * by Jason R. Thorpe. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 49 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 50 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 51 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 52 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 53 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 54 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 55 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 56 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 57 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 58 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 59 * POSSIBILITY OF SUCH DAMAGE. 60 */ 61 62 /* 63 * Platform-specific interrupt support for the RMI XLP, XLR, XLS 64 */ 65 66 #include <sys/cdefs.h> 67 __KERNEL_RCSID(0, "$NetBSD: rmixl_intr.c,v 1.1.2.24 2010/09/20 19:41:05 cliff Exp $"); 68 69 #include "opt_ddb.h" 70 #define __INTR_PRIVATE 71 72 #include <sys/param.h> 73 #include <sys/queue.h> 74 #include <sys/malloc.h> 75 #include <sys/systm.h> 76 #include <sys/device.h> 77 #include <sys/kernel.h> 78 #include <sys/atomic.h> 79 #include <sys/cpu.h> 80 81 #include <machine/bus.h> 82 #include <machine/intr.h> 83 84 #include <mips/cpu.h> 85 #include <mips/locore.h> 86 87 #include <mips/rmi/rmixlreg.h> 88 #include <mips/rmi/rmixlvar.h> 89 90 #include <mips/rmi/rmixl_cpuvar.h> 91 #include <mips/rmi/rmixl_intr.h> 92 93 #include <dev/pci/pcireg.h> 94 #include <dev/pci/pcivar.h> 95 96 // #define IOINTR_DEBUG 1 97 #ifdef IOINTR_DEBUG 98 int iointr_debug = IOINTR_DEBUG; 99 # define DPRINTF(x) do { if (iointr_debug) printf x ; } while(0) 100 #else 101 # define DPRINTF(x) 102 #endif 103 104 #define RMIXL_PICREG_READ(off) \ 105 RMIXL_IOREG_READ(RMIXL_IO_DEV_PIC + (off)) 106 #define RMIXL_PICREG_WRITE(off, val) \ 107 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PIC + (off), (val)) 108 109 /* 110 * do not clear these when acking EIRR 111 * (otherwise they get lost) 112 */ 113 #define RMIXL_EIRR_PRESERVE_MASK \ 114 ((MIPS_INT_MASK_5|MIPS_SOFT_INT_MASK) >> 8) 115 116 /* 117 * IRT assignments depends on the RMI chip family 118 * (XLS1xx vs. XLS2xx vs. XLS3xx vs. XLS6xx) 119 * use the right display string table for the CPU that's running. 120 */ 121 122 /* 123 * rmixl_irtnames_xlrxxx 124 * - use for XLRxxx 125 */ 126 static const char * const rmixl_irtnames_xlrxxx[NIRTS] = { 127 "pic int 0 (watchdog)", /* 0 */ 128 "pic int 1 (timer0)", /* 1 */ 129 "pic int 2 (timer1)", /* 2 */ 130 "pic int 3 (timer2)", /* 3 */ 131 "pic int 4 (timer3)", /* 4 */ 132 "pic int 5 (timer4)", /* 5 */ 133 "pic int 6 (timer5)", /* 6 */ 134 "pic int 7 (timer6)", /* 7 */ 135 "pic int 8 (timer7)", /* 8 */ 136 "pic int 9 (uart0)", /* 9 */ 137 "pic int 10 (uart1)", /* 10 */ 138 "pic int 11 (i2c0)", /* 11 */ 139 "pic int 12 (i2c1)", /* 12 */ 140 "pic int 13 (pcmcia)", /* 13 */ 141 "pic int 14 (gpio)", /* 14 */ 142 "pic int 15 (hyper)", /* 15 */ 143 "pic int 16 (pcix)", /* 16 */ 144 "pic int 17 (gmac0)", /* 17 */ 145 "pic int 18 (gmac1)", /* 18 */ 146 "pic int 19 (gmac2)", /* 19 */ 147 "pic int 20 (gmac3)", /* 20 */ 148 "pic int 21 (xgs0)", /* 21 */ 149 "pic int 22 (xgs1)", /* 22 */ 150 "pic int 23 (irq23)", /* 23 */ 151 "pic int 24 (hyper_fatal)", /* 24 */ 152 "pic int 25 (bridge_aerr)", /* 25 */ 153 "pic int 26 (bridge_berr)", /* 26 */ 154 "pic int 27 (bridge_tb)", /* 27 */ 155 "pic int 28 (bridge_nmi)", /* 28 */ 156 "pic int 29 (bridge_sram_derr)",/* 29 */ 157 "pic int 30 (gpio_fatal)", /* 30 */ 158 "pic int 31 (reserved)", /* 31 */ 159 }; 160 161 /* 162 * rmixl_irtnames_xls2xx 163 * - use for XLS2xx 164 */ 165 static const char * const rmixl_irtnames_xls2xx[NIRTS] = { 166 "pic int 0 (watchdog)", /* 0 */ 167 "pic int 1 (timer0)", /* 1 */ 168 "pic int 2 (timer1)", /* 2 */ 169 "pic int 3 (timer2)", /* 3 */ 170 "pic int 4 (timer3)", /* 4 */ 171 "pic int 5 (timer4)", /* 5 */ 172 "pic int 6 (timer5)", /* 6 */ 173 "pic int 7 (timer6)", /* 7 */ 174 "pic int 8 (timer7)", /* 8 */ 175 "pic int 9 (uart0)", /* 9 */ 176 "pic int 10 (uart1)", /* 10 */ 177 "pic int 11 (i2c0)", /* 11 */ 178 "pic int 12 (i2c1)", /* 12 */ 179 "pic int 13 (pcmcia)", /* 13 */ 180 "pic int 14 (gpio_a)", /* 14 */ 181 "pic int 15 (irq15)", /* 15 */ 182 "pic int 16 (bridge_tb)", /* 16 */ 183 "pic int 17 (gmac0)", /* 17 */ 184 "pic int 18 (gmac1)", /* 18 */ 185 "pic int 19 (gmac2)", /* 19 */ 186 "pic int 20 (gmac3)", /* 20 */ 187 "pic int 21 (irq21)", /* 21 */ 188 "pic int 22 (irq22)", /* 22 */ 189 "pic int 23 (pcie_link2)", /* 23 */ 190 "pic int 24 (pcie_link3)", /* 24 */ 191 "pic int 25 (bridge_err)", /* 25 */ 192 "pic int 26 (pcie_link0)", /* 26 */ 193 "pic int 27 (pcie_link1)", /* 27 */ 194 "pic int 28 (irq28)", /* 28 */ 195 "pic int 29 (pcie_err)", /* 29 */ 196 "pic int 30 (gpio_b)", /* 30 */ 197 "pic int 31 (usb)", /* 31 */ 198 }; 199 200 /* 201 * rmixl_irtnames_xls1xx 202 * - use for XLS1xx, XLS4xx-Lite 203 */ 204 static const char * const rmixl_irtnames_xls1xx[NIRTS] = { 205 "pic int 0 (watchdog)", /* 0 */ 206 "pic int 1 (timer0)", /* 1 */ 207 "pic int 2 (timer1)", /* 2 */ 208 "pic int 3 (timer2)", /* 3 */ 209 "pic int 4 (timer3)", /* 4 */ 210 "pic int 5 (timer4)", /* 5 */ 211 "pic int 6 (timer5)", /* 6 */ 212 "pic int 7 (timer6)", /* 7 */ 213 "pic int 8 (timer7)", /* 8 */ 214 "pic int 9 (uart0)", /* 9 */ 215 "pic int 10 (uart1)", /* 10 */ 216 "pic int 11 (i2c0)", /* 11 */ 217 "pic int 12 (i2c1)", /* 12 */ 218 "pic int 13 (pcmcia)", /* 13 */ 219 "pic int 14 (gpio_a)", /* 14 */ 220 "pic int 15 (irq15)", /* 15 */ 221 "pic int 16 (bridge_tb)", /* 16 */ 222 "pic int 17 (gmac0)", /* 17 */ 223 "pic int 18 (gmac1)", /* 18 */ 224 "pic int 19 (gmac2)", /* 19 */ 225 "pic int 20 (gmac3)", /* 20 */ 226 "pic int 21 (irq21)", /* 21 */ 227 "pic int 22 (irq22)", /* 22 */ 228 "pic int 23 (irq23)", /* 23 */ 229 "pic int 24 (irq24)", /* 24 */ 230 "pic int 25 (bridge_err)", /* 25 */ 231 "pic int 26 (pcie_link0)", /* 26 */ 232 "pic int 27 (pcie_link1)", /* 27 */ 233 "pic int 28 (irq28)", /* 28 */ 234 "pic int 29 (pcie_err)", /* 29 */ 235 "pic int 30 (gpio_b)", /* 30 */ 236 "pic int 31 (usb)", /* 31 */ 237 }; 238 239 /* 240 * rmixl_irtnames_xls4xx: 241 * - use for XLS4xx, XLS6xx 242 */ 243 static const char * const rmixl_irtnames_xls4xx[NIRTS] = { 244 "pic int 0 (watchdog)", /* 0 */ 245 "pic int 1 (timer0)", /* 1 */ 246 "pic int 2 (timer1)", /* 2 */ 247 "pic int 3 (timer2)", /* 3 */ 248 "pic int 4 (timer3)", /* 4 */ 249 "pic int 5 (timer4)", /* 5 */ 250 "pic int 6 (timer5)", /* 6 */ 251 "pic int 7 (timer6)", /* 7 */ 252 "pic int 8 (timer7)", /* 8 */ 253 "pic int 9 (uart0)", /* 9 */ 254 "pic int 10 (uart1)", /* 10 */ 255 "pic int 11 (i2c0)", /* 11 */ 256 "pic int 12 (i2c1)", /* 12 */ 257 "pic int 13 (pcmcia)", /* 13 */ 258 "pic int 14 (gpio_a)", /* 14 */ 259 "pic int 15 (irq15)", /* 15 */ 260 "pic int 16 (bridge_tb)", /* 16 */ 261 "pic int 17 (gmac0)", /* 17 */ 262 "pic int 18 (gmac1)", /* 18 */ 263 "pic int 19 (gmac2)", /* 19 */ 264 "pic int 20 (gmac3)", /* 20 */ 265 "pic int 21 (irq21)", /* 21 */ 266 "pic int 22 (irq22)", /* 22 */ 267 "pic int 23 (irq23)", /* 23 */ 268 "pic int 24 (irq24)", /* 24 */ 269 "pic int 25 (bridge_err)", /* 25 */ 270 "pic int 26 (pcie_link0)", /* 26 */ 271 "pic int 27 (pcie_link1)", /* 27 */ 272 "pic int 28 (pcie_link2)", /* 28 */ 273 "pic int 29 (pcie_link3)", /* 29 */ 274 "pic int 30 (gpio_b)", /* 30 */ 275 "pic int 31 (usb)", /* 31 */ 276 }; 277 278 /* 279 * rmixl_vecnames_common: 280 * - use for unknown cpu implementation 281 * - covers all vectors, not just IRT intrs 282 */ 283 static const char * const rmixl_vecnames_common[NINTRVECS] = { 284 "vec 0", /* 0 */ 285 "vec 1", /* 1 */ 286 "vec 2", /* 2 */ 287 "vec 3", /* 3 */ 288 "vec 4", /* 4 */ 289 "vec 5", /* 5 */ 290 "vec 6", /* 6 */ 291 "vec 7", /* 7 */ 292 "vec 8 (ipi)", /* 8 */ 293 "vec 9 (fmn)", /* 9 */ 294 "vec 10", /* 10 */ 295 "vec 11", /* 11 */ 296 "vec 12", /* 12 */ 297 "vec 13", /* 13 */ 298 "vec 14", /* 14 */ 299 "vec 15", /* 15 */ 300 "vec 16", /* 16 */ 301 "vec 17", /* 17 */ 302 "vec 18", /* 18 */ 303 "vec 19", /* 19 */ 304 "vec 20", /* 20 */ 305 "vec 21", /* 21 */ 306 "vec 22", /* 22 */ 307 "vec 23", /* 23 */ 308 "vec 24", /* 24 */ 309 "vec 25", /* 25 */ 310 "vec 26", /* 26 */ 311 "vec 27", /* 27 */ 312 "vec 28", /* 28 */ 313 "vec 29", /* 29 */ 314 "vec 30", /* 30 */ 315 "vec 31", /* 31 */ 316 "vec 32", /* 32 */ 317 "vec 33", /* 33 */ 318 "vec 34", /* 34 */ 319 "vec 35", /* 35 */ 320 "vec 36", /* 36 */ 321 "vec 37", /* 37 */ 322 "vec 38", /* 38 */ 323 "vec 39", /* 39 */ 324 "vec 40", /* 40 */ 325 "vec 41", /* 41 */ 326 "vec 42", /* 42 */ 327 "vec 43", /* 43 */ 328 "vec 44", /* 44 */ 329 "vec 45", /* 45 */ 330 "vec 46", /* 46 */ 331 "vec 47", /* 47 */ 332 "vec 48", /* 48 */ 333 "vec 49", /* 49 */ 334 "vec 50", /* 50 */ 335 "vec 51", /* 51 */ 336 "vec 52", /* 52 */ 337 "vec 53", /* 53 */ 338 "vec 54", /* 54 */ 339 "vec 55", /* 55 */ 340 "vec 56", /* 56 */ 341 "vec 57", /* 57 */ 342 "vec 58", /* 58 */ 343 "vec 59", /* 59 */ 344 "vec 60", /* 60 */ 345 "vec 61", /* 61 */ 346 "vec 62", /* 63 */ 347 "vec 63", /* 63 */ 348 }; 349 350 /* 351 * mask of CPUs attached 352 * once they are attached, this var is read-only so mp safe 353 */ 354 static uint32_t cpu_present_mask; 355 356 rmixl_intrhand_t rmixl_intrhand[NINTRVECS]; 357 358 #ifdef DIAGNOSTIC 359 static int rmixl_pic_init_done; 360 #endif 361 362 363 static const char *rmixl_intr_string_xlr(int); 364 static const char *rmixl_intr_string_xls(int); 365 static uint32_t rmixl_irt_thread_mask(int); 366 static void rmixl_irt_init(int); 367 static void rmixl_irt_disestablish(int); 368 static void rmixl_irt_establish(int, int, int, 369 rmixl_intr_trigger_t, rmixl_intr_polarity_t); 370 371 #ifdef MULTIPROCESSOR 372 static int rmixl_send_ipi(struct cpu_info *, int); 373 static int rmixl_ipi_intr(void *); 374 #endif 375 376 #if defined(DIAGNOSTIC) || defined(IOINTR_DEBUG) || defined(DDB) 377 int rmixl_intrhand_print_subr(int); 378 int rmixl_intrhand_print(void); 379 int rmixl_irt_print(void); 380 void rmixl_ipl_eimr_map_print(void); 381 #endif 382 383 384 static inline u_int 385 dclz(uint64_t val) 386 { 387 int nlz; 388 389 asm volatile("dclz %0, %1;" 390 : "=r"(nlz) : "r"(val)); 391 392 return nlz; 393 } 394 395 void 396 evbmips_intr_init(void) 397 { 398 uint32_t r; 399 400 KASSERT(cpu_rmixlr(mips_options.mips_cpu) 401 || cpu_rmixls(mips_options.mips_cpu)); 402 403 404 #ifdef DIAGNOSTIC 405 if (rmixl_pic_init_done != 0) 406 panic("%s: rmixl_pic_init_done %d", 407 __func__, rmixl_pic_init_done); 408 #endif 409 410 /* 411 * initialize (zero) all IRT Entries in the PIC 412 */ 413 for (int i=0; i < NIRTS; i++) 414 rmixl_irt_init(i); 415 416 /* 417 * disable watchdog NMI, timers 418 * 419 * XXX 420 * WATCHDOG_ENB is preserved because clearing it causes 421 * hang on the XLS616 (but not on the XLS408) 422 */ 423 r = RMIXL_PICREG_READ(RMIXL_PIC_CONTROL); 424 r &= RMIXL_PIC_CONTROL_RESV|RMIXL_PIC_CONTROL_WATCHDOG_ENB; 425 RMIXL_PICREG_WRITE(RMIXL_PIC_CONTROL, r); 426 427 #ifdef DIAGNOSTIC 428 rmixl_pic_init_done = 1; 429 #endif 430 431 } 432 433 /* 434 * establish vector for mips3 count/compare clock interrupt 435 * this ensures we enable in EIRR, 436 * even though cpu_intr() handles the interrupt 437 * note the 'mpsafe' arg here is a placeholder only 438 */ 439 void * 440 rmixl_intr_init_clk(void) 441 { 442 int vec = ffs(MIPS_INT_MASK_5 >> 8) - 1; 443 void *ih = rmixl_vec_establish(vec, 0, IPL_SCHED, NULL, NULL, false); 444 if (ih == NULL) 445 panic("%s: establish vec %d failed", __func__, vec); 446 447 return ih; 448 } 449 450 #ifdef MULTIPROCESSOR 451 /* 452 * establish IPI interrupt and send function 453 */ 454 void * 455 rmixl_intr_init_ipi(void) 456 { 457 void *ih = rmixl_vec_establish(RMIXL_INTRVEC_IPI, -1, IPL_SCHED, 458 rmixl_ipi_intr, NULL, false); 459 if (ih == NULL) 460 panic("%s: establish vec %d failed", 461 __func__, RMIXL_INTRVEC_IPI); 462 463 mips_locoresw.lsw_send_ipi = rmixl_send_ipi; 464 465 return ih; 466 } 467 #endif /* MULTIPROCESSOR */ 468 469 /* 470 * initialize per-cpu interrupt stuff in softc 471 * accumulate per-cpu bits in 'cpu_present_mask' 472 */ 473 void 474 rmixl_intr_init_cpu(struct cpu_info *ci) 475 { 476 struct rmixl_cpu_softc *sc = (void *)ci->ci_softc; 477 478 KASSERT(sc != NULL); 479 480 for (int vec=0; vec < NINTRVECS; vec++) 481 evcnt_attach_dynamic(&sc->sc_vec_evcnts[vec], 482 EVCNT_TYPE_INTR, NULL, 483 device_xname(sc->sc_dev), 484 rmixl_intr_string(vec)); 485 486 KASSERT(ci->ci_cpuid < (sizeof(cpu_present_mask) * 8)); 487 cpu_present_mask |= 1 << ci->ci_cpuid; 488 } 489 490 /* 491 * rmixl_intr_string - return pointer to display name of a PIC-based interrupt 492 */ 493 const char * 494 rmixl_intr_string(int vec) 495 { 496 int irt; 497 498 if (vec < 0 || vec >= NINTRVECS) 499 panic("%s: vec index %d out of range, max %d", 500 __func__, vec, NINTRVECS - 1); 501 502 if (! RMIXL_VECTOR_IS_IRT(vec)) 503 return rmixl_vecnames_common[vec]; 504 505 irt = RMIXL_VECTOR_IRT(vec); 506 switch(cpu_rmixl_chip_type(mips_options.mips_cpu)) { 507 case CIDFL_RMI_TYPE_XLR: 508 return rmixl_intr_string_xlr(irt); 509 case CIDFL_RMI_TYPE_XLS: 510 return rmixl_intr_string_xls(irt); 511 case CIDFL_RMI_TYPE_XLP: 512 panic("%s: RMI XLP not yet supported", __func__); 513 } 514 515 return "undefined"; /* appease gcc */ 516 } 517 518 static const char * 519 rmixl_intr_string_xlr(int irt) 520 { 521 return rmixl_irtnames_xlrxxx[irt]; 522 } 523 524 static const char * 525 rmixl_intr_string_xls(int irt) 526 { 527 const char *name; 528 529 switch (MIPS_PRID_IMPL(mips_options.mips_cpu_id)) { 530 case MIPS_XLS104: 531 case MIPS_XLS108: 532 case MIPS_XLS404LITE: 533 case MIPS_XLS408LITE: 534 name = rmixl_irtnames_xls1xx[irt]; 535 break; 536 case MIPS_XLS204: 537 case MIPS_XLS208: 538 name = rmixl_irtnames_xls2xx[irt]; 539 break; 540 case MIPS_XLS404: 541 case MIPS_XLS408: 542 case MIPS_XLS416: 543 case MIPS_XLS608: 544 case MIPS_XLS616: 545 name = rmixl_irtnames_xls4xx[irt]; 546 break; 547 default: 548 name = rmixl_vecnames_common[RMIXL_IRT_VECTOR(irt)]; 549 break; 550 } 551 552 return name; 553 } 554 555 /* 556 * rmixl_irt_thread_mask 557 * 558 * given a bitmask of cpus, return a, IRT thread mask 559 */ 560 static uint32_t 561 rmixl_irt_thread_mask(int cpumask) 562 { 563 uint32_t irtc0; 564 565 #if defined(MULTIPROCESSOR) 566 #ifndef NOTYET 567 if (cpumask == -1) 568 return 1; /* XXX TMP FIXME */ 569 #endif 570 571 /* 572 * discount cpus not present 573 */ 574 cpumask &= cpu_present_mask; 575 576 switch (MIPS_PRID_IMPL(mips_options.mips_cpu_id)) { 577 case MIPS_XLS104: 578 case MIPS_XLS204: 579 case MIPS_XLS404: 580 case MIPS_XLS404LITE: 581 irtc0 = ((cpumask >> 2) << 4) | (cpumask & __BITS(1,0)); 582 irtc0 &= (__BITS(5,4) | __BITS(1,0)); 583 break; 584 case MIPS_XLS108: 585 case MIPS_XLS208: 586 case MIPS_XLS408: 587 case MIPS_XLS408LITE: 588 case MIPS_XLS608: 589 irtc0 = cpumask & __BITS(7,0); 590 break; 591 case MIPS_XLS416: 592 case MIPS_XLS616: 593 irtc0 = cpumask & __BITS(15,0); 594 break; 595 default: 596 panic("%s: unknown cpu ID %#x\n", __func__, 597 mips_options.mips_cpu_id); 598 } 599 #else 600 irtc0 = 1; 601 #endif /* MULTIPROCESSOR */ 602 603 return irtc0; 604 } 605 606 /* 607 * rmixl_irt_init 608 * - initialize IRT Entry for given index 609 * - unmask Thread#0 in low word (assume we only have 1 thread) 610 */ 611 static void 612 rmixl_irt_init(int irt) 613 { 614 KASSERT(irt < NIRTS); 615 RMIXL_PICREG_WRITE(RMIXL_PIC_IRTENTRYC1(irt), 0); /* high word */ 616 RMIXL_PICREG_WRITE(RMIXL_PIC_IRTENTRYC0(irt), 0); /* low word */ 617 } 618 619 /* 620 * rmixl_irt_disestablish 621 * - invalidate IRT Entry for given index 622 */ 623 static void 624 rmixl_irt_disestablish(int irt) 625 { 626 DPRINTF(("%s: irt %d, irtc1 %#x\n", __func__, irt, 0)); 627 rmixl_irt_init(irt); 628 } 629 630 /* 631 * rmixl_irt_establish 632 * - construct an IRT Entry for irt and write to PIC 633 */ 634 static void 635 rmixl_irt_establish(int irt, int vec, int cpumask, rmixl_intr_trigger_t trigger, 636 rmixl_intr_polarity_t polarity) 637 { 638 uint32_t irtc1; 639 uint32_t irtc0; 640 641 if (irt >= NIRTS) 642 panic("%s: bad irt %d\n", __func__, irt); 643 644 if (! RMIXL_VECTOR_IS_IRT(vec)) 645 panic("%s: bad vec %d\n", __func__, vec); 646 647 switch (trigger) { 648 case RMIXL_TRIG_EDGE: 649 case RMIXL_TRIG_LEVEL: 650 break; 651 default: 652 panic("%s: bad trigger %d\n", __func__, trigger); 653 } 654 655 switch (polarity) { 656 case RMIXL_POLR_RISING: 657 case RMIXL_POLR_HIGH: 658 case RMIXL_POLR_FALLING: 659 case RMIXL_POLR_LOW: 660 break; 661 default: 662 panic("%s: bad polarity %d\n", __func__, polarity); 663 } 664 665 /* 666 * XXX IRT entries are not shared 667 */ 668 KASSERT(RMIXL_PICREG_READ(RMIXL_PIC_IRTENTRYC0(irt)) == 0); 669 KASSERT(RMIXL_PICREG_READ(RMIXL_PIC_IRTENTRYC1(irt)) == 0); 670 671 irtc0 = rmixl_irt_thread_mask(cpumask); 672 673 irtc1 = RMIXL_PIC_IRTENTRYC1_VALID; 674 irtc1 |= RMIXL_PIC_IRTENTRYC1_GL; /* local */ 675 676 if (trigger == RMIXL_TRIG_LEVEL) 677 irtc1 |= RMIXL_PIC_IRTENTRYC1_TRG; 678 679 if ((polarity == RMIXL_POLR_FALLING) || (polarity == RMIXL_POLR_LOW)) 680 irtc1 |= RMIXL_PIC_IRTENTRYC1_P; 681 682 irtc1 |= vec; /* vector in EIRR */ 683 684 /* 685 * write IRT Entry to PIC 686 */ 687 DPRINTF(("%s: irt %d, irtc0 %#x, irtc1 %#x\n", 688 __func__, irt, irtc0, irtc1)); 689 RMIXL_PICREG_WRITE(RMIXL_PIC_IRTENTRYC0(irt), irtc0); /* low word */ 690 RMIXL_PICREG_WRITE(RMIXL_PIC_IRTENTRYC1(irt), irtc1); /* high word */ 691 } 692 693 void * 694 rmixl_vec_establish(int vec, int cpumask, int ipl, 695 int (*func)(void *), void *arg, bool mpsafe) 696 { 697 rmixl_intrhand_t *ih; 698 uint64_t eimr_bit; 699 int s; 700 701 DPRINTF(("%s: vec %d, cpumask %#x, ipl %d, func %p, arg %p\n" 702 __func__, vec, cpumask, ipl, func, arg)); 703 #ifdef DIAGNOSTIC 704 if (rmixl_pic_init_done == 0) 705 panic("%s: called before evbmips_intr_init", __func__); 706 #endif 707 708 /* 709 * check args 710 */ 711 if (vec < 0 || vec >= NINTRVECS) 712 panic("%s: vec %d out of range, max %d", 713 __func__, vec, NINTRVECS - 1); 714 if (ipl <= 0 || ipl >= _IPL_N) 715 panic("%s: ipl %d out of range, min %d, max %d", 716 __func__, ipl, 1, _IPL_N - 1); 717 718 s = splhigh(); 719 720 ih = &rmixl_intrhand[vec]; 721 if (ih->ih_func != NULL) { 722 #ifdef DIAGNOSTIC 723 printf("%s: intrhand[%d] busy\n", __func__, vec); 724 #endif 725 splx(s); 726 return NULL; 727 } 728 729 ih->ih_arg = arg; 730 ih->ih_mpsafe = mpsafe; 731 ih->ih_vec = vec; 732 ih->ih_ipl = ipl; 733 ih->ih_cpumask = cpumask; 734 735 eimr_bit = (uint64_t)1 << vec; 736 for (int i=ih->ih_ipl; --i >= 0; ) { 737 KASSERT((ipl_eimr_map[i] & eimr_bit) == 0); 738 ipl_eimr_map[i] |= eimr_bit; 739 } 740 741 ih->ih_func = func; /* do this last */ 742 743 splx(s); 744 745 return ih; 746 } 747 748 /* 749 * rmixl_intr_establish 750 * - used to establish an IRT-based interrupt only 751 */ 752 void * 753 rmixl_intr_establish(int irt, int cpumask, int ipl, 754 rmixl_intr_trigger_t trigger, rmixl_intr_polarity_t polarity, 755 int (*func)(void *), void *arg, bool mpsafe) 756 { 757 rmixl_intrhand_t *ih; 758 int vec; 759 int s; 760 761 #ifdef DIAGNOSTIC 762 if (rmixl_pic_init_done == 0) 763 panic("%s: called before rmixl_pic_init_done", __func__); 764 #endif 765 766 /* 767 * check args 768 */ 769 if (irt < 0 || irt >= NIRTS) 770 panic("%s: irt %d out of range, max %d", 771 __func__, irt, NIRTS - 1); 772 if (ipl <= 0 || ipl >= _IPL_N) 773 panic("%s: ipl %d out of range, min %d, max %d", 774 __func__, ipl, 1, _IPL_N - 1); 775 776 vec = RMIXL_IRT_VECTOR(irt); 777 778 DPRINTF(("%s: irt %d, vec %d, ipl %d\n", __func__, irt, vec, ipl)); 779 780 s = splhigh(); 781 782 /* 783 * establish vector 784 */ 785 ih = rmixl_vec_establish(vec, cpumask, ipl, func, arg, mpsafe); 786 787 /* 788 * establish IRT Entry 789 */ 790 rmixl_irt_establish(irt, vec, cpumask, trigger, polarity); 791 792 splx(s); 793 794 return ih; 795 } 796 797 void 798 rmixl_vec_disestablish(void *cookie) 799 { 800 rmixl_intrhand_t *ih = cookie; 801 uint64_t eimr_bit; 802 int s; 803 804 KASSERT(ih->ih_vec < NINTRVECS); 805 KASSERT(ih == &rmixl_intrhand[ih->ih_vec]); 806 807 s = splhigh(); 808 809 ih->ih_func = NULL; /* do this first */ 810 811 eimr_bit = (uint64_t)1 << ih->ih_vec; 812 for (int i=ih->ih_ipl; --i >= 0; ) { 813 KASSERT((ipl_eimr_map[i] & eimr_bit) != 0); 814 ipl_eimr_map[i] ^= eimr_bit; 815 } 816 817 splx(s); 818 } 819 820 void 821 rmixl_intr_disestablish(void *cookie) 822 { 823 rmixl_intrhand_t *ih = cookie; 824 int vec; 825 int s; 826 827 vec = ih->ih_vec; 828 829 KASSERT(vec < NINTRVECS); 830 KASSERT(ih == &rmixl_intrhand[vec]); 831 832 s = splhigh(); 833 834 /* 835 * disable/invalidate the IRT Entry if needed 836 */ 837 if (RMIXL_VECTOR_IS_IRT(vec)) 838 rmixl_irt_disestablish(vec); 839 840 /* 841 * disasociate from vector and free the handle 842 */ 843 rmixl_vec_disestablish(cookie); 844 845 splx(s); 846 } 847 848 void 849 evbmips_iointr(int ipl, vaddr_t pc, uint32_t pending) 850 { 851 struct rmixl_cpu_softc *sc = (void *)curcpu()->ci_softc; 852 853 DPRINTF(("%s: cpu%ld: ipl %d, pc %#"PRIxVADDR", pending %#x\n", 854 __func__, cpu_number(), ipl, pc, pending)); 855 856 /* 857 * 'pending' arg is a summary that there is something to do 858 * the real pending status is obtained from EIRR 859 */ 860 KASSERT(pending == MIPS_INT_MASK_1); 861 862 for (;;) { 863 rmixl_intrhand_t *ih; 864 uint64_t eirr; 865 uint64_t eimr; 866 uint64_t vecbit; 867 int vec; 868 869 asm volatile("dmfc0 %0, $9, 6;" : "=r"(eirr)); 870 asm volatile("dmfc0 %0, $9, 7;" : "=r"(eimr)); 871 872 #ifdef IOINTR_DEBUG 873 printf("%s: eirr %#"PRIx64", eimr %#"PRIx64", mask %#"PRIx64"\n", 874 __func__, eirr, eimr, ipl_eimr_map[ipl-1]); 875 #endif /* IOINTR_DEBUG */ 876 877 /* 878 * reduce eirr to 879 * - ints that are enabled at or below this ipl 880 * - exclude count/compare clock and soft ints 881 * they are handled elsewhere 882 */ 883 eirr &= ipl_eimr_map[ipl-1]; 884 eirr &= ~ipl_eimr_map[ipl]; 885 eirr &= ~((MIPS_INT_MASK_5 | MIPS_SOFT_INT_MASK) >> 8); 886 if (eirr == 0) 887 break; 888 889 vec = 63 - dclz(eirr); 890 ih = &rmixl_intrhand[vec]; 891 vecbit = 1ULL << vec; 892 KASSERT (ih->ih_ipl == ipl); 893 KASSERT ((vecbit & eimr) == 0); 894 KASSERT ((vecbit & RMIXL_EIRR_PRESERVE_MASK) == 0); 895 896 /* 897 * ack in EIRR the irq we are about to handle 898 * disable all interrupt to prevent a race that would allow 899 * e.g. softints set from a higher interrupt getting 900 * clobbered by the EIRR read-modify-write 901 */ 902 asm volatile("dmtc0 $0, $9, 7;"); 903 asm volatile("dmfc0 %0, $9, 6;" : "=r"(eirr)); 904 eirr &= RMIXL_EIRR_PRESERVE_MASK; 905 eirr |= vecbit; 906 asm volatile("dmtc0 %0, $9, 6;" :: "r"(eirr)); 907 asm volatile("dmtc0 %0, $9, 7;" :: "r"(eimr)); 908 909 if (RMIXL_VECTOR_IS_IRT(vec)) 910 RMIXL_PICREG_WRITE(RMIXL_PIC_INTRACK, 911 1 << RMIXL_VECTOR_IRT(vec)); 912 913 if (ih->ih_func != NULL) { 914 #ifdef MULTIPROCESSOR 915 if (ih->ih_mpsafe) { 916 (void)(*ih->ih_func)(ih->ih_arg); 917 } else { 918 KERNEL_LOCK(1, NULL); 919 (void)(*ih->ih_func)(ih->ih_arg); 920 KERNEL_UNLOCK_ONE(NULL); 921 } 922 #else 923 (void)(*ih->ih_func)(ih->ih_arg); 924 #endif /* MULTIPROCESSOR */ 925 } 926 sc->sc_vec_evcnts[vec].ev_count++; 927 } 928 } 929 930 #ifdef MULTIPROCESSOR 931 static int 932 rmixl_send_ipi(struct cpu_info *ci, int tag) 933 { 934 const cpuid_t cpu = ci->ci_cpuid; 935 uint32_t core = (uint32_t)(cpu >> 2); 936 uint32_t thread = (uint32_t)(cpu & __BITS(1,0)); 937 uint64_t req = 1 << tag; 938 uint32_t r; 939 extern volatile u_long cpus_running; 940 941 if ((cpus_running & 1 << ci->ci_index) == 0) 942 return -1; 943 944 KASSERT(tag < NIPIS); 945 946 r = (thread << RMIXL_PIC_IPIBASE_ID_THREAD_SHIFT) 947 | (core << RMIXL_PIC_IPIBASE_ID_CORE_SHIFT) 948 | RMIXL_INTRVEC_IPI; 949 950 atomic_or_64(&ci->ci_request_ipis, req); 951 952 RMIXL_PICREG_WRITE(RMIXL_PIC_IPIBASE, r); 953 954 return 0; 955 } 956 957 static int 958 rmixl_ipi_intr(void *arg) 959 { 960 struct cpu_info * const ci = curcpu(); 961 uint64_t ipi_mask; 962 963 ipi_mask = atomic_swap_64(&ci->ci_request_ipis, 0); 964 if (ipi_mask == 0) 965 return 0; 966 967 ipi_process(ci, ipi_mask); 968 969 return 1; 970 } 971 #endif /* MULTIPROCESSOR */ 972 973 #if defined(DIAGNOSTIC) || defined(IOINTR_DEBUG) || defined(DDB) 974 int 975 rmixl_intrhand_print_subr(int vec) 976 { 977 rmixl_intrhand_t *ih = &rmixl_intrhand[vec]; 978 printf("vec %d: func %p, arg %p, vec %d, ipl %d, mask %#x\n", 979 vec, ih->ih_func, ih->ih_arg, ih->ih_vec, ih->ih_ipl, 980 ih->ih_cpumask); 981 return 0; 982 } 983 int 984 rmixl_intrhand_print(void) 985 { 986 for (int vec=0; vec < NINTRVECS ; vec++) 987 rmixl_intrhand_print_subr(vec); 988 return 0; 989 } 990 991 static inline void 992 rmixl_irt_entry_print(u_int irt) 993 { 994 uint32_t c0, c1; 995 996 if ((irt < 0) || (irt > NIRTS)) 997 return; 998 c0 = RMIXL_PICREG_READ(RMIXL_PIC_IRTENTRYC0(irt)); 999 c1 = RMIXL_PICREG_READ(RMIXL_PIC_IRTENTRYC1(irt)); 1000 printf("irt[%d]: %#x, %#x\n", irt, c0, c1); 1001 } 1002 1003 int 1004 rmixl_irt_print(void) 1005 { 1006 printf("%s:\n", __func__); 1007 for (int irt=0; irt < NIRTS ; irt++) 1008 rmixl_irt_entry_print(irt); 1009 return 0; 1010 } 1011 1012 void 1013 rmixl_ipl_eimr_map_print(void) 1014 { 1015 printf("IPL_NONE=%d, mask %#"PRIx64"\n", 1016 IPL_NONE, ipl_eimr_map[IPL_NONE]); 1017 printf("IPL_SOFTCLOCK=%d, mask %#"PRIx64"\n", 1018 IPL_SOFTCLOCK, ipl_eimr_map[IPL_SOFTCLOCK]); 1019 printf("IPL_SOFTNET=%d, mask %#"PRIx64"\n", 1020 IPL_SOFTNET, ipl_eimr_map[IPL_SOFTNET]); 1021 printf("IPL_VM=%d, mask %#"PRIx64"\n", 1022 IPL_VM, ipl_eimr_map[IPL_VM]); 1023 printf("IPL_SCHED=%d, mask %#"PRIx64"\n", 1024 IPL_SCHED, ipl_eimr_map[IPL_SCHED]); 1025 printf("IPL_DDB=%d, mask %#"PRIx64"\n", 1026 IPL_DDB, ipl_eimr_map[IPL_DDB]); 1027 printf("IPL_HIGH=%d, mask %#"PRIx64"\n", 1028 IPL_HIGH, ipl_eimr_map[IPL_HIGH]); 1029 } 1030 1031 #endif 1032
Indexes created Thu Oct 16 14:10:15 GMT 2025