rmixl_intr.c revision 1.1.2.30
1 /* $NetBSD: rmixl_intr.c,v 1.1.2.30 2011/04/29 08:26:32 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or 8 * without modification, are permitted provided that the following 9 * conditions are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above 13 * copyright notice, this list of conditions and the following 14 * disclaimer in the documentation and/or other materials provided 15 * with the distribution. 16 * 3. The names of the authors may not be used to endorse or promote 17 * products derived from this software without specific prior 18 * written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY 21 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 23 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, 25 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 27 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 29 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 30 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 31 * OF SUCH DAMAGE. 32 */ 33 /*- 34 * Copyright (c) 2001 The NetBSD Foundation, Inc. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to The NetBSD Foundation 38 * by Jason R. Thorpe. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 49 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 50 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 51 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 52 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 53 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 54 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 55 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 56 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 57 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 58 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 59 * POSSIBILITY OF SUCH DAMAGE. 60 */ 61 62 /* 63 * Platform-specific interrupt support for the RMI XLP, XLR, XLS 64 */ 65 66 #include <sys/cdefs.h> 67 __KERNEL_RCSID(0, "$NetBSD: rmixl_intr.c,v 1.1.2.30 2011/04/29 08:26:32 matt Exp $"); 68 69 #include "opt_ddb.h" 70 #include "opt_multiprocessor.h" 71 #define __INTR_PRIVATE 72 73 #include <sys/param.h> 74 #include <sys/queue.h> 75 #include <sys/malloc.h> 76 #include <sys/systm.h> 77 #include <sys/device.h> 78 #include <sys/kernel.h> 79 #include <sys/atomic.h> 80 #include <sys/mutex.h> 81 #include <sys/cpu.h> 82 83 #include <machine/bus.h> 84 #include <machine/intr.h> 85 86 #include <mips/cpu.h> 87 #include <mips/cpuset.h> 88 #include <mips/locore.h> 89 90 #include <mips/rmi/rmixlreg.h> 91 #include <mips/rmi/rmixlvar.h> 92 93 #include <mips/rmi/rmixl_cpuvar.h> 94 #include <mips/rmi/rmixl_intr.h> 95 96 #include <dev/pci/pcireg.h> 97 #include <dev/pci/pcivar.h> 98 99 //#define IOINTR_DEBUG 1 100 #ifdef IOINTR_DEBUG 101 int iointr_debug = IOINTR_DEBUG; 102 # define DPRINTF(x) do { if (iointr_debug) printf x ; } while(0) 103 #else 104 # define DPRINTF(x) 105 #endif 106 107 #define RMIXL_PICREG_READ(off) \ 108 RMIXL_IOREG_READ(RMIXL_IO_DEV_PIC + (off)) 109 #define RMIXL_PICREG_WRITE(off, val) \ 110 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PIC + (off), (val)) 111 112 /* 113 * do not clear these when acking EIRR 114 * (otherwise they get lost) 115 */ 116 #define RMIXL_EIRR_PRESERVE_MASK \ 117 ((MIPS_INT_MASK_5|MIPS_SOFT_INT_MASK) >> 8) 118 119 /* 120 * IRT assignments depends on the RMI chip family 121 * (XLS1xx vs. XLS2xx vs. XLS3xx vs. XLS6xx) 122 * use the right display string table for the CPU that's running. 123 */ 124 125 /* 126 * rmixl_irtnames_xlrxxx 127 * - use for XLRxxx 128 */ 129 static const char * const rmixl_irtnames_xlrxxx[NIRTS] = { 130 "pic int 0 (watchdog)", /* 0 */ 131 "pic int 1 (timer0)", /* 1 */ 132 "pic int 2 (timer1)", /* 2 */ 133 "pic int 3 (timer2)", /* 3 */ 134 "pic int 4 (timer3)", /* 4 */ 135 "pic int 5 (timer4)", /* 5 */ 136 "pic int 6 (timer5)", /* 6 */ 137 "pic int 7 (timer6)", /* 7 */ 138 "pic int 8 (timer7)", /* 8 */ 139 "pic int 9 (uart0)", /* 9 */ 140 "pic int 10 (uart1)", /* 10 */ 141 "pic int 11 (i2c0)", /* 11 */ 142 "pic int 12 (i2c1)", /* 12 */ 143 "pic int 13 (pcmcia)", /* 13 */ 144 "pic int 14 (gpio)", /* 14 */ 145 "pic int 15 (hyper)", /* 15 */ 146 "pic int 16 (pcix)", /* 16 */ 147 "pic int 17 (gmac0)", /* 17 */ 148 "pic int 18 (gmac1)", /* 18 */ 149 "pic int 19 (gmac2)", /* 19 */ 150 "pic int 20 (gmac3)", /* 20 */ 151 "pic int 21 (xgs0)", /* 21 */ 152 "pic int 22 (xgs1)", /* 22 */ 153 "pic int 23 (irq23)", /* 23 */ 154 "pic int 24 (hyper_fatal)", /* 24 */ 155 "pic int 25 (bridge_aerr)", /* 25 */ 156 "pic int 26 (bridge_berr)", /* 26 */ 157 "pic int 27 (bridge_tb)", /* 27 */ 158 "pic int 28 (bridge_nmi)", /* 28 */ 159 "pic int 29 (bridge_sram_derr)",/* 29 */ 160 "pic int 30 (gpio_fatal)", /* 30 */ 161 "pic int 31 (reserved)", /* 31 */ 162 }; 163 164 /* 165 * rmixl_irtnames_xls2xx 166 * - use for XLS2xx 167 */ 168 static const char * const rmixl_irtnames_xls2xx[NIRTS] = { 169 "pic int 0 (watchdog)", /* 0 */ 170 "pic int 1 (timer0)", /* 1 */ 171 "pic int 2 (timer1)", /* 2 */ 172 "pic int 3 (timer2)", /* 3 */ 173 "pic int 4 (timer3)", /* 4 */ 174 "pic int 5 (timer4)", /* 5 */ 175 "pic int 6 (timer5)", /* 6 */ 176 "pic int 7 (timer6)", /* 7 */ 177 "pic int 8 (timer7)", /* 8 */ 178 "pic int 9 (uart0)", /* 9 */ 179 "pic int 10 (uart1)", /* 10 */ 180 "pic int 11 (i2c0)", /* 11 */ 181 "pic int 12 (i2c1)", /* 12 */ 182 "pic int 13 (pcmcia)", /* 13 */ 183 "pic int 14 (gpio_a)", /* 14 */ 184 "pic int 15 (irq15)", /* 15 */ 185 "pic int 16 (bridge_tb)", /* 16 */ 186 "pic int 17 (gmac0)", /* 17 */ 187 "pic int 18 (gmac1)", /* 18 */ 188 "pic int 19 (gmac2)", /* 19 */ 189 "pic int 20 (gmac3)", /* 20 */ 190 "pic int 21 (irq21)", /* 21 */ 191 "pic int 22 (irq22)", /* 22 */ 192 "pic int 23 (pcie_link2)", /* 23 */ 193 "pic int 24 (pcie_link3)", /* 24 */ 194 "pic int 25 (bridge_err)", /* 25 */ 195 "pic int 26 (pcie_link0)", /* 26 */ 196 "pic int 27 (pcie_link1)", /* 27 */ 197 "pic int 28 (irq28)", /* 28 */ 198 "pic int 29 (pcie_err)", /* 29 */ 199 "pic int 30 (gpio_b)", /* 30 */ 200 "pic int 31 (usb)", /* 31 */ 201 }; 202 203 /* 204 * rmixl_irtnames_xls1xx 205 * - use for XLS1xx, XLS4xx-Lite 206 */ 207 static const char * const rmixl_irtnames_xls1xx[NIRTS] = { 208 "pic int 0 (watchdog)", /* 0 */ 209 "pic int 1 (timer0)", /* 1 */ 210 "pic int 2 (timer1)", /* 2 */ 211 "pic int 3 (timer2)", /* 3 */ 212 "pic int 4 (timer3)", /* 4 */ 213 "pic int 5 (timer4)", /* 5 */ 214 "pic int 6 (timer5)", /* 6 */ 215 "pic int 7 (timer6)", /* 7 */ 216 "pic int 8 (timer7)", /* 8 */ 217 "pic int 9 (uart0)", /* 9 */ 218 "pic int 10 (uart1)", /* 10 */ 219 "pic int 11 (i2c0)", /* 11 */ 220 "pic int 12 (i2c1)", /* 12 */ 221 "pic int 13 (pcmcia)", /* 13 */ 222 "pic int 14 (gpio_a)", /* 14 */ 223 "pic int 15 (irq15)", /* 15 */ 224 "pic int 16 (bridge_tb)", /* 16 */ 225 "pic int 17 (gmac0)", /* 17 */ 226 "pic int 18 (gmac1)", /* 18 */ 227 "pic int 19 (gmac2)", /* 19 */ 228 "pic int 20 (gmac3)", /* 20 */ 229 "pic int 21 (irq21)", /* 21 */ 230 "pic int 22 (irq22)", /* 22 */ 231 "pic int 23 (irq23)", /* 23 */ 232 "pic int 24 (irq24)", /* 24 */ 233 "pic int 25 (bridge_err)", /* 25 */ 234 "pic int 26 (pcie_link0)", /* 26 */ 235 "pic int 27 (pcie_link1)", /* 27 */ 236 "pic int 28 (irq28)", /* 28 */ 237 "pic int 29 (pcie_err)", /* 29 */ 238 "pic int 30 (gpio_b)", /* 30 */ 239 "pic int 31 (usb)", /* 31 */ 240 }; 241 242 /* 243 * rmixl_irtnames_xls4xx: 244 * - use for XLS4xx, XLS6xx 245 */ 246 static const char * const rmixl_irtnames_xls4xx[NIRTS] = { 247 "pic int 0 (watchdog)", /* 0 */ 248 "pic int 1 (timer0)", /* 1 */ 249 "pic int 2 (timer1)", /* 2 */ 250 "pic int 3 (timer2)", /* 3 */ 251 "pic int 4 (timer3)", /* 4 */ 252 "pic int 5 (timer4)", /* 5 */ 253 "pic int 6 (timer5)", /* 6 */ 254 "pic int 7 (timer6)", /* 7 */ 255 "pic int 8 (timer7)", /* 8 */ 256 "pic int 9 (uart0)", /* 9 */ 257 "pic int 10 (uart1)", /* 10 */ 258 "pic int 11 (i2c0)", /* 11 */ 259 "pic int 12 (i2c1)", /* 12 */ 260 "pic int 13 (pcmcia)", /* 13 */ 261 "pic int 14 (gpio_a)", /* 14 */ 262 "pic int 15 (irq15)", /* 15 */ 263 "pic int 16 (bridge_tb)", /* 16 */ 264 "pic int 17 (gmac0)", /* 17 */ 265 "pic int 18 (gmac1)", /* 18 */ 266 "pic int 19 (gmac2)", /* 19 */ 267 "pic int 20 (gmac3)", /* 20 */ 268 "pic int 21 (irq21)", /* 21 */ 269 "pic int 22 (irq22)", /* 22 */ 270 "pic int 23 (irq23)", /* 23 */ 271 "pic int 24 (irq24)", /* 24 */ 272 "pic int 25 (bridge_err)", /* 25 */ 273 "pic int 26 (pcie_link0)", /* 26 */ 274 "pic int 27 (pcie_link1)", /* 27 */ 275 "pic int 28 (pcie_link2)", /* 28 */ 276 "pic int 29 (pcie_link3)", /* 29 */ 277 "pic int 30 (gpio_b)", /* 30 */ 278 "pic int 31 (usb)", /* 31 */ 279 }; 280 281 /* 282 * rmixl_vecnames_common: 283 * - use for unknown cpu implementation 284 * - covers all vectors, not just IRT intrs 285 */ 286 static const char * const rmixl_vecnames_common[NINTRVECS] = { 287 "vec 0", /* 0 */ 288 "vec 1", /* 1 */ 289 "vec 2", /* 2 */ 290 "vec 3", /* 3 */ 291 "vec 4", /* 4 */ 292 "vec 5", /* 5 */ 293 "vec 6", /* 6 */ 294 "vec 7", /* 7 */ 295 "vec 8 (ipi 0)", /* 8 */ 296 "vec 9 (ipi 1)", /* 9 */ 297 "vec 10 (ipi 2)", /* 10 */ 298 "vec 11 (ipi 3)", /* 11 */ 299 "vec 12 (ipi 4)", /* 12 */ 300 "vec 13 (ipi 5)", /* 13 */ 301 "vec 14 (ipi 6)", /* 14 */ 302 "vec 15 (fmn)", /* 15 */ 303 "vec 16", /* 16 */ 304 "vec 17", /* 17 */ 305 "vec 18", /* 18 */ 306 "vec 19", /* 19 */ 307 "vec 20", /* 20 */ 308 "vec 21", /* 21 */ 309 "vec 22", /* 22 */ 310 "vec 23", /* 23 */ 311 "vec 24", /* 24 */ 312 "vec 25", /* 25 */ 313 "vec 26", /* 26 */ 314 "vec 27", /* 27 */ 315 "vec 28", /* 28 */ 316 "vec 29", /* 29 */ 317 "vec 30", /* 30 */ 318 "vec 31", /* 31 */ 319 "vec 32", /* 32 */ 320 "vec 33", /* 33 */ 321 "vec 34", /* 34 */ 322 "vec 35", /* 35 */ 323 "vec 36", /* 36 */ 324 "vec 37", /* 37 */ 325 "vec 38", /* 38 */ 326 "vec 39", /* 39 */ 327 "vec 40", /* 40 */ 328 "vec 41", /* 41 */ 329 "vec 42", /* 42 */ 330 "vec 43", /* 43 */ 331 "vec 44", /* 44 */ 332 "vec 45", /* 45 */ 333 "vec 46", /* 46 */ 334 "vec 47", /* 47 */ 335 "vec 48", /* 48 */ 336 "vec 49", /* 49 */ 337 "vec 50", /* 50 */ 338 "vec 51", /* 51 */ 339 "vec 52", /* 52 */ 340 "vec 53", /* 53 */ 341 "vec 54", /* 54 */ 342 "vec 55", /* 55 */ 343 "vec 56", /* 56 */ 344 "vec 57", /* 57 */ 345 "vec 58", /* 58 */ 346 "vec 59", /* 59 */ 347 "vec 60", /* 60 */ 348 "vec 61", /* 61 */ 349 "vec 62", /* 63 */ 350 "vec 63", /* 63 */ 351 }; 352 353 /* 354 * mask of CPUs attached 355 * once they are attached, this var is read-only so mp safe 356 */ 357 static uint32_t cpu_present_mask; 358 359 kmutex_t *rmixl_ipi_lock; /* covers RMIXL_PIC_IPIBASE */ 360 kmutex_t *rmixl_intr_lock; /* covers rest of PIC, and rmixl_intrhand[] */ 361 rmixl_intrhand_t rmixl_intrhand[NINTRVECS]; 362 363 #ifdef DIAGNOSTIC 364 static int rmixl_pic_init_done; 365 #endif 366 367 368 static const char *rmixl_intr_string_xlr(int); 369 static const char *rmixl_intr_string_xls(int); 370 static uint32_t rmixl_irt_thread_mask(int); 371 static void rmixl_irt_init(int); 372 static void rmixl_irt_disestablish(int); 373 static void rmixl_irt_establish(int, int, int, 374 rmixl_intr_trigger_t, rmixl_intr_polarity_t); 375 376 #ifdef MULTIPROCESSOR 377 static int rmixl_send_ipi(struct cpu_info *, int); 378 static int rmixl_ipi_intr(void *); 379 #endif 380 381 #if defined(DIAGNOSTIC) || defined(IOINTR_DEBUG) || defined(DDB) 382 int rmixl_intrhand_print_subr(int); 383 int rmixl_intrhand_print(void); 384 int rmixl_irt_print(void); 385 void rmixl_ipl_eimr_map_print(void); 386 #endif 387 388 389 static inline u_int 390 dclz(uint64_t val) 391 { 392 int nlz; 393 394 asm volatile("dclz %0, %1;" 395 : "=r"(nlz) : "r"(val)); 396 397 return nlz; 398 } 399 400 void 401 evbmips_intr_init(void) 402 { 403 uint32_t r; 404 405 KASSERT(cpu_rmixlr(mips_options.mips_cpu) 406 || cpu_rmixls(mips_options.mips_cpu)); 407 408 409 #ifdef DIAGNOSTIC 410 if (rmixl_pic_init_done != 0) 411 panic("%s: rmixl_pic_init_done %d", 412 __func__, rmixl_pic_init_done); 413 #endif 414 415 rmixl_ipi_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_HIGH); 416 rmixl_intr_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_HIGH); 417 418 mutex_enter(rmixl_intr_lock); 419 420 /* 421 * initialize (zero) all IRT Entries in the PIC 422 */ 423 for (u_int i = 0; i < NIRTS; i++) { 424 rmixl_irt_init(i); 425 } 426 427 /* 428 * disable watchdog NMI, timers 429 * 430 * XXX 431 * WATCHDOG_ENB is preserved because clearing it causes 432 * hang on the XLS616 (but not on the XLS408) 433 */ 434 r = RMIXL_PICREG_READ(RMIXL_PIC_CONTROL); 435 r &= RMIXL_PIC_CONTROL_RESV|RMIXL_PIC_CONTROL_WATCHDOG_ENB; 436 RMIXL_PICREG_WRITE(RMIXL_PIC_CONTROL, r); 437 438 #ifdef DIAGNOSTIC 439 rmixl_pic_init_done = 1; 440 #endif 441 mutex_exit(rmixl_intr_lock); 442 443 } 444 445 /* 446 * establish vector for mips3 count/compare clock interrupt 447 * this ensures we enable in EIRR, 448 * even though cpu_intr() handles the interrupt 449 * note the 'mpsafe' arg here is a placeholder only 450 */ 451 void 452 rmixl_intr_init_clk(void) 453 { 454 const int vec = ffs(MIPS_INT_MASK_5 >> MIPS_INT_MASK_SHIFT) - 1; 455 456 mutex_enter(rmixl_intr_lock); 457 458 void *ih = rmixl_vec_establish(vec, 0, IPL_SCHED, NULL, NULL, false); 459 if (ih == NULL) 460 panic("%s: establish vec %d failed", __func__, vec); 461 462 mutex_exit(rmixl_intr_lock); 463 } 464 465 #ifdef MULTIPROCESSOR 466 /* 467 * establish IPI interrupt and send function 468 */ 469 void 470 rmixl_intr_init_ipi(void) 471 { 472 mutex_enter(rmixl_intr_lock); 473 474 for (u_int ipi = 0; ipi < NIPIS; ipi++) { 475 const u_int vec = RMIXL_INTRVEC_IPI + ipi; 476 void * const ih = rmixl_vec_establish(vec, -1, IPL_SCHED, 477 rmixl_ipi_intr, (void *)(uintptr_t)ipi, true); 478 if (ih == NULL) 479 panic("%s: establish ipi %d at vec %d failed", 480 __func__, ipi, vec); 481 } 482 483 mips_locoresw.lsw_send_ipi = rmixl_send_ipi; 484 485 mutex_exit(rmixl_intr_lock); 486 } 487 #endif /* MULTIPROCESSOR */ 488 489 /* 490 * initialize per-cpu interrupt stuff in softc 491 * accumulate per-cpu bits in 'cpu_present_mask' 492 */ 493 void 494 rmixl_intr_init_cpu(struct cpu_info *ci) 495 { 496 struct rmixl_cpu_softc *sc = (void *)ci->ci_softc; 497 498 KASSERT(sc != NULL); 499 500 for (int vec=0; vec < NINTRVECS; vec++) 501 evcnt_attach_dynamic(&sc->sc_vec_evcnts[vec], 502 EVCNT_TYPE_INTR, NULL, 503 device_xname(sc->sc_dev), 504 rmixl_intr_string(vec)); 505 506 KASSERT(cpu_index(ci) < (sizeof(cpu_present_mask) * 8)); 507 atomic_or_32((volatile uint32_t *)&cpu_present_mask, 1 << cpu_index(ci)); 508 } 509 510 /* 511 * rmixl_intr_string - return pointer to display name of a PIC-based interrupt 512 */ 513 const char * 514 rmixl_intr_string(int vec) 515 { 516 int irt; 517 518 if (vec < 0 || vec >= NINTRVECS) 519 panic("%s: vec index %d out of range, max %d", 520 __func__, vec, NINTRVECS - 1); 521 522 if (! RMIXL_VECTOR_IS_IRT(vec)) 523 return rmixl_vecnames_common[vec]; 524 525 irt = RMIXL_VECTOR_IRT(vec); 526 switch(cpu_rmixl_chip_type(mips_options.mips_cpu)) { 527 case CIDFL_RMI_TYPE_XLR: 528 return rmixl_intr_string_xlr(irt); 529 case CIDFL_RMI_TYPE_XLS: 530 return rmixl_intr_string_xls(irt); 531 case CIDFL_RMI_TYPE_XLP: 532 panic("%s: RMI XLP not yet supported", __func__); 533 } 534 535 return "undefined"; /* appease gcc */ 536 } 537 538 static const char * 539 rmixl_intr_string_xlr(int irt) 540 { 541 return rmixl_irtnames_xlrxxx[irt]; 542 } 543 544 static const char * 545 rmixl_intr_string_xls(int irt) 546 { 547 const char *name; 548 549 switch (MIPS_PRID_IMPL(mips_options.mips_cpu_id)) { 550 case MIPS_XLS104: 551 case MIPS_XLS108: 552 case MIPS_XLS404LITE: 553 case MIPS_XLS408LITE: 554 name = rmixl_irtnames_xls1xx[irt]; 555 break; 556 case MIPS_XLS204: 557 case MIPS_XLS208: 558 name = rmixl_irtnames_xls2xx[irt]; 559 break; 560 case MIPS_XLS404: 561 case MIPS_XLS408: 562 case MIPS_XLS416: 563 case MIPS_XLS608: 564 case MIPS_XLS616: 565 name = rmixl_irtnames_xls4xx[irt]; 566 break; 567 default: 568 name = rmixl_vecnames_common[RMIXL_IRT_VECTOR(irt)]; 569 break; 570 } 571 572 return name; 573 } 574 575 /* 576 * rmixl_irt_thread_mask 577 * 578 * given a bitmask of cpus, return a, IRT thread mask 579 */ 580 static uint32_t 581 rmixl_irt_thread_mask(int cpumask) 582 { 583 uint32_t irtc0; 584 585 #if defined(MULTIPROCESSOR) 586 #ifndef NOTYET 587 if (cpumask == -1) 588 return 1; /* XXX TMP FIXME */ 589 #endif 590 591 /* 592 * discount cpus not present 593 */ 594 cpumask &= cpu_present_mask; 595 596 switch (MIPS_PRID_IMPL(mips_options.mips_cpu_id)) { 597 case MIPS_XLS104: 598 case MIPS_XLS204: 599 case MIPS_XLS404: 600 case MIPS_XLS404LITE: 601 irtc0 = ((cpumask >> 2) << 4) | (cpumask & __BITS(1,0)); 602 irtc0 &= (__BITS(5,4) | __BITS(1,0)); 603 break; 604 case MIPS_XLS108: 605 case MIPS_XLS208: 606 case MIPS_XLS408: 607 case MIPS_XLS408LITE: 608 case MIPS_XLS608: 609 irtc0 = cpumask & __BITS(7,0); 610 break; 611 case MIPS_XLS416: 612 case MIPS_XLS616: 613 irtc0 = cpumask & __BITS(15,0); 614 break; 615 default: 616 panic("%s: unknown cpu ID %#x\n", __func__, 617 mips_options.mips_cpu_id); 618 } 619 #else 620 irtc0 = 1; 621 #endif /* MULTIPROCESSOR */ 622 623 return irtc0; 624 } 625 626 /* 627 * rmixl_irt_init 628 * - initialize IRT Entry for given index 629 * - unmask Thread#0 in low word (assume we only have 1 thread) 630 */ 631 static void 632 rmixl_irt_init(int irt) 633 { 634 KASSERT(irt < NIRTS); 635 RMIXL_PICREG_WRITE(RMIXL_PIC_IRTENTRYC1(irt), 0); /* high word */ 636 RMIXL_PICREG_WRITE(RMIXL_PIC_IRTENTRYC0(irt), 0); /* low word */ 637 } 638 639 /* 640 * rmixl_irt_disestablish 641 * - invalidate IRT Entry for given index 642 */ 643 static void 644 rmixl_irt_disestablish(int irt) 645 { 646 KASSERT(mutex_owned(rmixl_intr_lock)); 647 DPRINTF(("%s: irt %d, irtc1 %#x\n", __func__, irt, 0)); 648 rmixl_irt_init(irt); 649 } 650 651 /* 652 * rmixl_irt_establish 653 * - construct an IRT Entry for irt and write to PIC 654 */ 655 static void 656 rmixl_irt_establish(int irt, int vec, int cpumask, rmixl_intr_trigger_t trigger, 657 rmixl_intr_polarity_t polarity) 658 { 659 uint32_t irtc1; 660 uint32_t irtc0; 661 662 KASSERT(mutex_owned(rmixl_intr_lock)); 663 664 if (irt >= NIRTS) 665 panic("%s: bad irt %d\n", __func__, irt); 666 667 if (! RMIXL_VECTOR_IS_IRT(vec)) 668 panic("%s: bad vec %d\n", __func__, vec); 669 670 switch (trigger) { 671 case RMIXL_TRIG_EDGE: 672 case RMIXL_TRIG_LEVEL: 673 break; 674 default: 675 panic("%s: bad trigger %d\n", __func__, trigger); 676 } 677 678 switch (polarity) { 679 case RMIXL_POLR_RISING: 680 case RMIXL_POLR_HIGH: 681 case RMIXL_POLR_FALLING: 682 case RMIXL_POLR_LOW: 683 break; 684 default: 685 panic("%s: bad polarity %d\n", __func__, polarity); 686 } 687 688 /* 689 * XXX IRT entries are not shared 690 */ 691 KASSERT(RMIXL_PICREG_READ(RMIXL_PIC_IRTENTRYC0(irt)) == 0); 692 KASSERT(RMIXL_PICREG_READ(RMIXL_PIC_IRTENTRYC1(irt)) == 0); 693 694 irtc0 = rmixl_irt_thread_mask(cpumask); 695 696 irtc1 = RMIXL_PIC_IRTENTRYC1_VALID; 697 irtc1 |= RMIXL_PIC_IRTENTRYC1_GL; /* local */ 698 KASSERT((irtc1 & RMIXL_PIC_IRTENTRYC1_NMI) == 0); 699 700 if (trigger == RMIXL_TRIG_LEVEL) 701 irtc1 |= RMIXL_PIC_IRTENTRYC1_TRG; 702 KASSERT((irtc1 & RMIXL_PIC_IRTENTRYC1_NMI) == 0); 703 704 if ((polarity == RMIXL_POLR_FALLING) || (polarity == RMIXL_POLR_LOW)) 705 irtc1 |= RMIXL_PIC_IRTENTRYC1_P; 706 KASSERT((irtc1 & RMIXL_PIC_IRTENTRYC1_NMI) == 0); 707 708 irtc1 |= vec; /* vector in EIRR */ 709 KASSERT((irtc1 & RMIXL_PIC_IRTENTRYC1_NMI) == 0); 710 711 /* 712 * write IRT Entry to PIC 713 */ 714 DPRINTF(("%s: vec %d (%#x), irt %d, irtc0 %#x, irtc1 %#x\n", 715 __func__, vec, vec, irt, irtc0, irtc1)); 716 RMIXL_PICREG_WRITE(RMIXL_PIC_IRTENTRYC0(irt), irtc0); /* low word */ 717 RMIXL_PICREG_WRITE(RMIXL_PIC_IRTENTRYC1(irt), irtc1); /* high word */ 718 } 719 720 void * 721 rmixl_vec_establish(int vec, int cpumask, int ipl, 722 int (*func)(void *), void *arg, bool mpsafe) 723 { 724 rmixl_intrhand_t *ih; 725 uint64_t eimr_bit; 726 int s; 727 728 KASSERT(mutex_owned(rmixl_intr_lock)); 729 730 DPRINTF(("%s: vec %d cpumask %#x ipl %d func %p arg %p mpsafe %d\n", 731 __func__, vec, cpumask, ipl, func, arg, mpsafe)); 732 #ifdef DIAGNOSTIC 733 if (rmixl_pic_init_done == 0) 734 panic("%s: called before evbmips_intr_init", __func__); 735 #endif 736 737 /* 738 * check args 739 */ 740 if (vec < 0 || vec >= NINTRVECS) 741 panic("%s: vec %d out of range, max %d", 742 __func__, vec, NINTRVECS - 1); 743 if (ipl <= 0 || ipl >= _IPL_N) 744 panic("%s: ipl %d out of range, min %d, max %d", 745 __func__, ipl, 1, _IPL_N - 1); 746 747 s = splhigh(); 748 749 ih = &rmixl_intrhand[vec]; 750 if (ih->ih_func != NULL) { 751 #ifdef DIAGNOSTIC 752 printf("%s: intrhand[%d] busy\n", __func__, vec); 753 #endif 754 splx(s); 755 return NULL; 756 } 757 758 ih->ih_arg = arg; 759 ih->ih_mpsafe = mpsafe; 760 ih->ih_vec = vec; 761 ih->ih_ipl = ipl; 762 ih->ih_cpumask = cpumask; 763 764 eimr_bit = (uint64_t)1 << vec; 765 for (int i=ih->ih_ipl; --i >= 0; ) { 766 KASSERT((ipl_eimr_map[i] & eimr_bit) == 0); 767 ipl_eimr_map[i] |= eimr_bit; 768 } 769 770 ih->ih_func = func; /* do this last */ 771 772 splx(s); 773 774 return ih; 775 } 776 777 /* 778 * rmixl_intr_establish 779 * - used to establish an IRT-based interrupt only 780 */ 781 void * 782 rmixl_intr_establish(int irt, int cpumask, int ipl, 783 rmixl_intr_trigger_t trigger, rmixl_intr_polarity_t polarity, 784 int (*func)(void *), void *arg, bool mpsafe) 785 { 786 rmixl_intrhand_t *ih; 787 int vec; 788 789 #ifdef DIAGNOSTIC 790 if (rmixl_pic_init_done == 0) 791 panic("%s: called before rmixl_pic_init_done", __func__); 792 #endif 793 794 /* 795 * check args 796 */ 797 if (irt < 0 || irt >= NIRTS) 798 panic("%s: irt %d out of range, max %d", 799 __func__, irt, NIRTS - 1); 800 if (ipl <= 0 || ipl >= _IPL_N) 801 panic("%s: ipl %d out of range, min %d, max %d", 802 __func__, ipl, 1, _IPL_N - 1); 803 804 vec = RMIXL_IRT_VECTOR(irt); 805 806 DPRINTF(("%s: irt %d, vec %d, ipl %d\n", __func__, irt, vec, ipl)); 807 808 mutex_enter(rmixl_intr_lock); 809 810 /* 811 * establish vector 812 */ 813 ih = rmixl_vec_establish(vec, cpumask, ipl, func, arg, mpsafe); 814 815 /* 816 * establish IRT Entry 817 */ 818 rmixl_irt_establish(irt, vec, cpumask, trigger, polarity); 819 820 mutex_exit(rmixl_intr_lock); 821 822 return ih; 823 } 824 825 void 826 rmixl_vec_disestablish(void *cookie) 827 { 828 rmixl_intrhand_t *ih = cookie; 829 uint64_t eimr_bit; 830 831 KASSERT(mutex_owned(rmixl_intr_lock)); 832 KASSERT(ih->ih_vec < NINTRVECS); 833 KASSERT(ih == &rmixl_intrhand[ih->ih_vec]); 834 835 ih->ih_func = NULL; /* do this first */ 836 837 eimr_bit = (uint64_t)1 << ih->ih_vec; 838 for (int i=ih->ih_ipl; --i >= 0; ) { 839 KASSERT((ipl_eimr_map[i] & eimr_bit) != 0); 840 ipl_eimr_map[i] ^= eimr_bit; 841 } 842 } 843 844 void 845 rmixl_intr_disestablish(void *cookie) 846 { 847 rmixl_intrhand_t *ih = cookie; 848 const int vec = ih->ih_vec; 849 850 KASSERT(vec < NINTRVECS); 851 KASSERT(ih == &rmixl_intrhand[vec]); 852 853 mutex_enter(rmixl_intr_lock); 854 855 /* 856 * disable/invalidate the IRT Entry if needed 857 */ 858 if (RMIXL_VECTOR_IS_IRT(vec)) 859 rmixl_irt_disestablish(vec); 860 861 /* 862 * disasociate from vector and free the handle 863 */ 864 rmixl_vec_disestablish(cookie); 865 866 mutex_exit(rmixl_intr_lock); 867 } 868 869 void 870 evbmips_iointr(int ipl, vaddr_t pc, uint32_t pending) 871 { 872 struct rmixl_cpu_softc *sc = (void *)curcpu()->ci_softc; 873 874 DPRINTF(("%s: cpu%u: ipl %d, pc %#"PRIxVADDR", pending %#x\n", 875 __func__, cpu_number(), ipl, pc, pending)); 876 877 /* 878 * 'pending' arg is a summary that there is something to do 879 * the real pending status is obtained from EIRR 880 */ 881 KASSERT(pending == MIPS_INT_MASK_1); 882 883 for (;;) { 884 rmixl_intrhand_t *ih; 885 uint64_t eirr; 886 uint64_t eimr; 887 uint64_t vecbit; 888 int vec; 889 890 asm volatile("dmfc0 %0, $9, 6;" : "=r"(eirr)); 891 asm volatile("dmfc0 %0, $9, 7;" : "=r"(eimr)); 892 893 #ifdef IOINTR_DEBUG 894 printf("%s: cpu%u: eirr %#"PRIx64", eimr %#"PRIx64", mask %#"PRIx64"\n", 895 __func__, cpu_number(), eirr, eimr, ipl_eimr_map[ipl-1]); 896 #endif /* IOINTR_DEBUG */ 897 898 /* 899 * reduce eirr to 900 * - ints that are enabled at or below this ipl 901 * - exclude count/compare clock and soft ints 902 * they are handled elsewhere 903 */ 904 eirr &= ipl_eimr_map[ipl-1]; 905 eirr &= ~ipl_eimr_map[ipl]; 906 eirr &= ~((MIPS_INT_MASK_5 | MIPS_SOFT_INT_MASK) >> 8); 907 if (eirr == 0) 908 break; 909 910 vec = 63 - dclz(eirr); 911 ih = &rmixl_intrhand[vec]; 912 vecbit = 1ULL << vec; 913 KASSERT (ih->ih_ipl == ipl); 914 KASSERT ((vecbit & eimr) == 0); 915 KASSERT ((vecbit & RMIXL_EIRR_PRESERVE_MASK) == 0); 916 917 /* 918 * ack in EIRR, and in PIC if needed, 919 * the irq we are about to handle 920 */ 921 rmixl_eirr_ack(eimr, vecbit, RMIXL_EIRR_PRESERVE_MASK); 922 if (RMIXL_VECTOR_IS_IRT(vec)) 923 RMIXL_PICREG_WRITE(RMIXL_PIC_INTRACK, 924 1 << RMIXL_VECTOR_IRT(vec)); 925 926 if (ih->ih_func != NULL) { 927 #ifdef MULTIPROCESSOR 928 if (ih->ih_mpsafe) { 929 (void)(*ih->ih_func)(ih->ih_arg); 930 } else { 931 KASSERTMSG(ipl == IPL_VM, 932 ("%s: %s: ipl (%d) != IPL_VM for KERNEL_LOCK", 933 __func__, sc->sc_vec_evcnts[vec].ev_name, 934 ipl)); 935 KERNEL_LOCK(1, NULL); 936 (void)(*ih->ih_func)(ih->ih_arg); 937 KERNEL_UNLOCK_ONE(NULL); 938 } 939 #else 940 (void)(*ih->ih_func)(ih->ih_arg); 941 #endif /* MULTIPROCESSOR */ 942 } 943 KASSERT(ipl == ih->ih_ipl); 944 KASSERTMSG(curcpu()->ci_cpl >= ipl, 945 ("%s: after %s: cpl (%d) < ipl %d", 946 __func__, sc->sc_vec_evcnts[vec].ev_name, 947 ipl, curcpu()->ci_cpl)); 948 sc->sc_vec_evcnts[vec].ev_count++; 949 } 950 } 951 952 #ifdef MULTIPROCESSOR 953 static int 954 rmixl_send_ipi(struct cpu_info *ci, int tag) 955 { 956 const cpuid_t cpuid = ci->ci_cpuid; 957 uint32_t core = (uint32_t)(cpuid >> 2); 958 uint32_t thread = (uint32_t)(cpuid & __BITS(1,0)); 959 uint64_t req = 1 << tag; 960 uint32_t r; 961 962 if (! CPUSET_HAS_P(cpus_running, cpu_index(ci))) 963 return -1; 964 965 KASSERT((tag >= 0) && (tag < NIPIS)); 966 967 r = (thread << RMIXL_PIC_IPIBASE_ID_THREAD_SHIFT) 968 | (core << RMIXL_PIC_IPIBASE_ID_CORE_SHIFT) 969 | (RMIXL_INTRVEC_IPI + tag); 970 971 mutex_enter(rmixl_ipi_lock); 972 atomic_or_64(&ci->ci_request_ipis, req); 973 RMIXL_PICREG_WRITE(RMIXL_PIC_IPIBASE, r); 974 mutex_exit(rmixl_ipi_lock); 975 976 return 0; 977 } 978 979 static int 980 rmixl_ipi_intr(void *arg) 981 { 982 struct cpu_info * const ci = curcpu(); 983 const uint64_t ipi_mask = 1 << (uintptr_t)arg; 984 985 KASSERT(ci->ci_cpl >= IPL_SCHED); 986 KASSERT((uintptr_t)arg < NIPIS); 987 988 /* if the request is clear, it was previously processed */ 989 if ((ci->ci_request_ipis & ipi_mask) == 0) 990 return 0; 991 992 atomic_or_64(&ci->ci_active_ipis, ipi_mask); 993 atomic_and_64(&ci->ci_request_ipis, ~ipi_mask); 994 995 ipi_process(ci, ipi_mask); 996 997 atomic_and_64(&ci->ci_active_ipis, ~ipi_mask); 998 999 return 1; 1000 } 1001 #endif /* MULTIPROCESSOR */ 1002 1003 #if defined(DIAGNOSTIC) || defined(IOINTR_DEBUG) || defined(DDB) 1004 int 1005 rmixl_intrhand_print_subr(int vec) 1006 { 1007 rmixl_intrhand_t *ih = &rmixl_intrhand[vec]; 1008 printf("vec %d: func %p, arg %p, vec %d, ipl %d, mask %#x\n", 1009 vec, ih->ih_func, ih->ih_arg, ih->ih_vec, ih->ih_ipl, 1010 ih->ih_cpumask); 1011 return 0; 1012 } 1013 int 1014 rmixl_intrhand_print(void) 1015 { 1016 for (int vec=0; vec < NINTRVECS ; vec++) 1017 rmixl_intrhand_print_subr(vec); 1018 return 0; 1019 } 1020 1021 static inline void 1022 rmixl_irt_entry_print(u_int irt) 1023 { 1024 uint32_t c0, c1; 1025 1026 if ((irt < 0) || (irt > NIRTS)) 1027 return; 1028 c0 = RMIXL_PICREG_READ(RMIXL_PIC_IRTENTRYC0(irt)); 1029 c1 = RMIXL_PICREG_READ(RMIXL_PIC_IRTENTRYC1(irt)); 1030 printf("irt[%d]: %#x, %#x\n", irt, c0, c1); 1031 } 1032 1033 int 1034 rmixl_irt_print(void) 1035 { 1036 printf("%s:\n", __func__); 1037 for (int irt=0; irt < NIRTS ; irt++) 1038 rmixl_irt_entry_print(irt); 1039 return 0; 1040 } 1041 1042 void 1043 rmixl_ipl_eimr_map_print(void) 1044 { 1045 printf("IPL_NONE=%d, mask %#"PRIx64"\n", 1046 IPL_NONE, ipl_eimr_map[IPL_NONE]); 1047 printf("IPL_SOFTCLOCK=%d, mask %#"PRIx64"\n", 1048 IPL_SOFTCLOCK, ipl_eimr_map[IPL_SOFTCLOCK]); 1049 printf("IPL_SOFTNET=%d, mask %#"PRIx64"\n", 1050 IPL_SOFTNET, ipl_eimr_map[IPL_SOFTNET]); 1051 printf("IPL_VM=%d, mask %#"PRIx64"\n", 1052 IPL_VM, ipl_eimr_map[IPL_VM]); 1053 printf("IPL_SCHED=%d, mask %#"PRIx64"\n", 1054 IPL_SCHED, ipl_eimr_map[IPL_SCHED]); 1055 printf("IPL_DDB=%d, mask %#"PRIx64"\n", 1056 IPL_DDB, ipl_eimr_map[IPL_DDB]); 1057 printf("IPL_HIGH=%d, mask %#"PRIx64"\n", 1058 IPL_HIGH, ipl_eimr_map[IPL_HIGH]); 1059 } 1060 1061 #endif 1062
Indexes created Fri Oct 17 23:09:53 GMT 2025