rmixl_intr.c revision 1.1.2.33
1 /* $NetBSD: rmixl_intr.c,v 1.1.2.33 2011/12/31 08:20:43 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or 8 * without modification, are permitted provided that the following 9 * conditions are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above 13 * copyright notice, this list of conditions and the following 14 * disclaimer in the documentation and/or other materials provided 15 * with the distribution. 16 * 3. The names of the authors may not be used to endorse or promote 17 * products derived from this software without specific prior 18 * written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY 21 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 23 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, 25 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 27 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 29 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 30 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 31 * OF SUCH DAMAGE. 32 */ 33 /*- 34 * Copyright (c) 2001 The NetBSD Foundation, Inc. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to The NetBSD Foundation 38 * by Jason R. Thorpe. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 49 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 50 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 51 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 52 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 53 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 54 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 55 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 56 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 57 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 58 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 59 * POSSIBILITY OF SUCH DAMAGE. 60 */ 61 62 /* 63 * Platform-specific interrupt support for the RMI XLP, XLR, XLS 64 */ 65 66 #include <sys/cdefs.h> 67 __KERNEL_RCSID(0, "$NetBSD: rmixl_intr.c,v 1.1.2.33 2011/12/31 08:20:43 matt Exp $"); 68 69 #include "opt_ddb.h" 70 #include "opt_multiprocessor.h" 71 #define __INTR_PRIVATE 72 73 #include <sys/param.h> 74 #include <sys/queue.h> 75 #include <sys/malloc.h> 76 #include <sys/systm.h> 77 #include <sys/device.h> 78 #include <sys/kernel.h> 79 #include <sys/atomic.h> 80 #include <sys/mutex.h> 81 #include <sys/cpu.h> 82 83 #include <machine/bus.h> 84 #include <machine/intr.h> 85 86 #include <mips/cpu.h> 87 #include <mips/cpuset.h> 88 #include <mips/locore.h> 89 90 #include <mips/rmi/rmixlreg.h> 91 #include <mips/rmi/rmixlvar.h> 92 93 #include <mips/rmi/rmixl_cpuvar.h> 94 #include <mips/rmi/rmixl_intr.h> 95 96 #include <dev/pci/pcireg.h> 97 #include <dev/pci/pcivar.h> 98 99 //#define IOINTR_DEBUG 1 100 #ifdef IOINTR_DEBUG 101 int iointr_debug = IOINTR_DEBUG; 102 # define DPRINTF(x) do { if (iointr_debug) printf x ; } while(0) 103 #else 104 # define DPRINTF(x) 105 #endif 106 107 #define RMIXL_PICREG_READ(off) \ 108 RMIXL_IOREG_READ(RMIXL_IO_DEV_PIC + (off)) 109 #define RMIXL_PICREG_WRITE(off, val) \ 110 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PIC + (off), (val)) 111 112 /* XXX this will need to deal with node */ 113 #define RMIXLP_PICREG_READ(off) \ 114 rmixlp_read_8(RMIXLP_PIC_PCITAG, (off)) 115 #define RMIXLP_PICREG_WRITE(off, val) \ 116 rmixlp_write_8(RMIXLP_PIC_PCITAG, (off), (val)); 117 118 /* 119 * do not clear these when acking EIRR 120 * (otherwise they get lost) 121 */ 122 #define RMIXL_EIRR_PRESERVE_MASK \ 123 ((MIPS_INT_MASK_5|MIPS_SOFT_INT_MASK) >> 8) 124 125 /* 126 * IRT assignments depends on the RMI chip family 127 * (XLS1xx vs. XLS2xx vs. XLS3xx vs. XLS6xx) 128 * use the right display string table for the CPU that's running. 129 */ 130 131 #ifdef MIPS64_XLR 132 /* 133 * rmixl_irtnames_xlrxxx 134 * - use for XLRxxx 135 */ 136 static const char * const rmixl_irtnames_xlrxxx[RMIXLR_NIRTS] = { 137 "pic int 0 (watchdog)", /* 0 */ 138 "pic int 1 (timer0)", /* 1 */ 139 "pic int 2 (timer1)", /* 2 */ 140 "pic int 3 (timer2)", /* 3 */ 141 "pic int 4 (timer3)", /* 4 */ 142 "pic int 5 (timer4)", /* 5 */ 143 "pic int 6 (timer5)", /* 6 */ 144 "pic int 7 (timer6)", /* 7 */ 145 "pic int 8 (timer7)", /* 8 */ 146 "pic int 9 (uart0)", /* 9 */ 147 "pic int 10 (uart1)", /* 10 */ 148 "pic int 11 (i2c0)", /* 11 */ 149 "pic int 12 (i2c1)", /* 12 */ 150 "pic int 13 (pcmcia)", /* 13 */ 151 "pic int 14 (gpio)", /* 14 */ 152 "pic int 15 (hyper)", /* 15 */ 153 "pic int 16 (pcix)", /* 16 */ 154 "pic int 17 (gmac0)", /* 17 */ 155 "pic int 18 (gmac1)", /* 18 */ 156 "pic int 19 (gmac2)", /* 19 */ 157 "pic int 20 (gmac3)", /* 20 */ 158 "pic int 21 (xgs0)", /* 21 */ 159 "pic int 22 (xgs1)", /* 22 */ 160 "pic int 23 (?)", /* 23 */ 161 "pic int 24 (hyper_fatal)", /* 24 */ 162 "pic int 25 (bridge_aerr)", /* 25 */ 163 "pic int 26 (bridge_berr)", /* 26 */ 164 "pic int 27 (bridge_tb)", /* 27 */ 165 "pic int 28 (bridge_nmi)", /* 28 */ 166 "pic int 29 (bridge_sram_derr)",/* 29 */ 167 "pic int 30 (gpio_fatal)", /* 30 */ 168 "pic int 31 (reserved)", /* 31 */ 169 }; 170 #endif /* MIPS64_XLR */ 171 172 #ifdef MIPS64_XLS 173 /* 174 * rmixl_irtnames_xls2xx 175 * - use for XLS2xx 176 */ 177 static const char * const rmixl_irtnames_xls2xx[RMIXLS_NIRTS] = { 178 "pic int 0 (watchdog)", /* 0 */ 179 "pic int 1 (timer0)", /* 1 */ 180 "pic int 2 (timer1)", /* 2 */ 181 "pic int 3 (timer2)", /* 3 */ 182 "pic int 4 (timer3)", /* 4 */ 183 "pic int 5 (timer4)", /* 5 */ 184 "pic int 6 (timer5)", /* 6 */ 185 "pic int 7 (timer6)", /* 7 */ 186 "pic int 8 (timer7)", /* 8 */ 187 "pic int 9 (uart0)", /* 9 */ 188 "pic int 10 (uart1)", /* 10 */ 189 "pic int 11 (i2c0)", /* 11 */ 190 "pic int 12 (i2c1)", /* 12 */ 191 "pic int 13 (pcmcia)", /* 13 */ 192 "pic int 14 (gpio_a)", /* 14 */ 193 "pic int 15 (?)", /* 15 */ 194 "pic int 16 (bridge_tb)", /* 16 */ 195 "pic int 17 (gmac0)", /* 17 */ 196 "pic int 18 (gmac1)", /* 18 */ 197 "pic int 19 (gmac2)", /* 19 */ 198 "pic int 20 (gmac3)", /* 20 */ 199 "pic int 21 (?)", /* 21 */ 200 "pic int 22 (?)", /* 22 */ 201 "pic int 23 (pcie_link2)", /* 23 */ 202 "pic int 24 (pcie_link3)", /* 24 */ 203 "pic int 25 (bridge_err)", /* 25 */ 204 "pic int 26 (pcie_link0)", /* 26 */ 205 "pic int 27 (pcie_link1)", /* 27 */ 206 "pic int 28 (?)", /* 28 */ 207 "pic int 29 (pcie_err)", /* 29 */ 208 "pic int 30 (gpio_b)", /* 30 */ 209 "pic int 31 (usb)", /* 31 */ 210 }; 211 212 /* 213 * rmixl_irtnames_xls1xx 214 * - use for XLS1xx, XLS4xx-Lite 215 */ 216 static const char * const rmixl_irtnames_xls1xx[RMIXLS_NIRTS] = { 217 "pic int 0 (watchdog)", /* 0 */ 218 "pic int 1 (timer0)", /* 1 */ 219 "pic int 2 (timer1)", /* 2 */ 220 "pic int 3 (timer2)", /* 3 */ 221 "pic int 4 (timer3)", /* 4 */ 222 "pic int 5 (timer4)", /* 5 */ 223 "pic int 6 (timer5)", /* 6 */ 224 "pic int 7 (timer6)", /* 7 */ 225 "pic int 8 (timer7)", /* 8 */ 226 "pic int 9 (uart0)", /* 9 */ 227 "pic int 10 (uart1)", /* 10 */ 228 "pic int 11 (i2c0)", /* 11 */ 229 "pic int 12 (i2c1)", /* 12 */ 230 "pic int 13 (pcmcia)", /* 13 */ 231 "pic int 14 (gpio_a)", /* 14 */ 232 "pic int 15 (?)", /* 15 */ 233 "pic int 16 (bridge_tb)", /* 16 */ 234 "pic int 17 (gmac0)", /* 17 */ 235 "pic int 18 (gmac1)", /* 18 */ 236 "pic int 19 (gmac2)", /* 19 */ 237 "pic int 20 (gmac3)", /* 20 */ 238 "pic int 21 (?)", /* 21 */ 239 "pic int 22 (?)", /* 22 */ 240 "pic int 23 (?)", /* 23 */ 241 "pic int 24 (?)", /* 24 */ 242 "pic int 25 (bridge_err)", /* 25 */ 243 "pic int 26 (pcie_link0)", /* 26 */ 244 "pic int 27 (pcie_link1)", /* 27 */ 245 "pic int 28 (?)", /* 28 */ 246 "pic int 29 (pcie_err)", /* 29 */ 247 "pic int 30 (gpio_b)", /* 30 */ 248 "pic int 31 (usb)", /* 31 */ 249 }; 250 251 /* 252 * rmixl_irtnames_xls4xx: 253 * - use for XLS4xx, XLS6xx 254 */ 255 static const char * const rmixl_irtnames_xls4xx[RMIXLS_NIRTS] = { 256 "pic int 0 (watchdog)", /* 0 */ 257 "pic int 1 (timer0)", /* 1 */ 258 "pic int 2 (timer1)", /* 2 */ 259 "pic int 3 (timer2)", /* 3 */ 260 "pic int 4 (timer3)", /* 4 */ 261 "pic int 5 (timer4)", /* 5 */ 262 "pic int 6 (timer5)", /* 6 */ 263 "pic int 7 (timer6)", /* 7 */ 264 "pic int 8 (timer7)", /* 8 */ 265 "pic int 9 (uart0)", /* 9 */ 266 "pic int 10 (uart1)", /* 10 */ 267 "pic int 11 (i2c0)", /* 11 */ 268 "pic int 12 (i2c1)", /* 12 */ 269 "pic int 13 (pcmcia)", /* 13 */ 270 "pic int 14 (gpio_a)", /* 14 */ 271 "pic int 15 (?)", /* 15 */ 272 "pic int 16 (bridge_tb)", /* 16 */ 273 "pic int 17 (gmac0)", /* 17 */ 274 "pic int 18 (gmac1)", /* 18 */ 275 "pic int 19 (gmac2)", /* 19 */ 276 "pic int 20 (gmac3)", /* 20 */ 277 "pic int 21 (?)", /* 21 */ 278 "pic int 22 (?)", /* 22 */ 279 "pic int 23 (?)", /* 23 */ 280 "pic int 24 (?)", /* 24 */ 281 "pic int 25 (bridge_err)", /* 25 */ 282 "pic int 26 (pcie_link0)", /* 26 */ 283 "pic int 27 (pcie_link1)", /* 27 */ 284 "pic int 28 (pcie_link2)", /* 28 */ 285 "pic int 29 (pcie_link3)", /* 29 */ 286 "pic int 30 (gpio_b)", /* 30 */ 287 "pic int 31 (usb)", /* 31 */ 288 }; 289 #endif /* MIPS64_XLS */ 290 291 #ifdef MIPS64_XLP 292 /* 293 * rmixl_irtnames_xlp: 294 * - use for XLP 295 */ 296 static const char * const rmixl_irtnames_xlp8xx[RMIXLP_NIRTS] = { 297 [ 0] = "pic int 0 (watchdog0)", 298 [ 1] = "pic int 1 (watchdog1)", 299 [ 2] = "pic int 2 (watchdogNMI0)", 300 [ 3] = "pic int 3 (watchdogNMI1)", 301 [ 4] = "pic int 4 (timer0)", 302 [ 5] = "pic int 5 (timer1)", 303 [ 6] = "pic int 6 (timer2)", 304 [ 7] = "pic int 7 (timer3)", 305 [ 8] = "pic int 8 (timer4)", 306 [ 9] = "pic int 9 (timer5)", 307 [ 10] = "pic int 10 (timer6)", 308 [ 11] = "pic int 11 (timer7)", 309 [ 12] = "pic int 12 (fmn0)", 310 [ 13] = "pic int 13 (fmn1)", 311 [ 14] = "pic int 14 (fmn2)", 312 [ 15] = "pic int 15 (fmn3)", 313 [ 16] = "pic int 16 (fmn4)", 314 [ 17] = "pic int 17 (fmn5)", 315 [ 18] = "pic int 18 (fmn6)", 316 [ 19] = "pic int 19 (fmn7)", 317 [ 20] = "pic int 20 (fmn8)", 318 [ 21] = "pic int 21 (fmn9)", 319 [ 22] = "pic int 22 (fmn10)", 320 [ 23] = "pic int 23 (fmn11)", 321 [ 24] = "pic int 24 (fmn12)", 322 [ 25] = "pic int 25 (fmn13)", 323 [ 26] = "pic int 26 (fmn14)", 324 [ 27] = "pic int 27 (fmn15)", 325 [ 28] = "pic int 28 (fmn16)", 326 [ 29] = "pic int 29 (fmn17)", 327 [ 30] = "pic int 30 (fmn18)", 328 [ 31] = "pic int 31 (fmn19)", 329 [ 32] = "pic int 22 (fmn20)", 330 [ 33] = "pic int 23 (fmn21)", 331 [ 34] = "pic int 24 (fmn22)", 332 [ 35] = "pic int 25 (fmn23)", 333 [ 36] = "pic int 26 (fmn24)", 334 [ 37] = "pic int 27 (fmn25)", 335 [ 38] = "pic int 28 (fmn26)", 336 [ 39] = "pic int 29 (fmn27)", 337 [ 40] = "pic int 30 (fmn28)", 338 [ 41] = "pic int 31 (fmn29)", 339 [ 42] = "pic int 42 (fmn30)", 340 [ 43] = "pic int 43 (fmn31)", 341 [ 44] = "pic int 44 (fmnerr0)", 342 [ 45] = "pic int 45 (fmnerr1)", 343 [ 46] = "pic int 46 (pcie_msix0)", 344 [ 47] = "pic int 47 (pcie_msix1)", 345 [ 48] = "pic int 48 (pcie_msix2)", 346 [ 49] = "pic int 49 (pcie_msix3)", 347 [ 50] = "pic int 50 (pcie_msix4)", 348 [ 51] = "pic int 51 (pcie_msix5)", 349 [ 52] = "pic int 52 (pcie_msix6)", 350 [ 53] = "pic int 53 (pcie_msix7)", 351 [ 54] = "pic int 54 (pcie_msix8)", 352 [ 55] = "pic int 55 (pcie_msix9)", 353 [ 56] = "pic int 56 (pcie_msix10)", 354 [ 57] = "pic int 57 (pcie_msix11)", 355 [ 58] = "pic int 58 (pcie_msix12)", 356 [ 59] = "pic int 59 (pcie_msix13)", 357 [ 60] = "pic int 60 (pcie_msix14)", 358 [ 61] = "pic int 61 (pcie_msix15)", 359 [ 62] = "pic int 62 (pcie_msix16)", 360 [ 63] = "pic int 63 (pcie_msix17)", 361 [ 64] = "pic int 64 (pcie_msix18)", 362 [ 65] = "pic int 65 (pcie_msix19)", 363 [ 66] = "pic int 66 (pcie_msix20)", 364 [ 67] = "pic int 67 (pcie_msix21)", 365 [ 68] = "pic int 68 (pcie_msix22)", 366 [ 69] = "pic int 69 (pcie_msix23)", 367 [ 70] = "pic int 70 (pcie_msix24)", 368 [ 71] = "pic int 71 (pcie_msix25)", 369 [ 72] = "pic int 72 (pcie_msix26)", 370 [ 73] = "pic int 73 (pcie_msix27)", 371 [ 74] = "pic int 74 (pcie_msix28)", 372 [ 75] = "pic int 75 (pcie_msix29)", 373 [ 76] = "pic int 76 (pcie_msix30)", 374 [ 77] = "pic int 77 (pcie_msix31)", 375 [ 78] = "pic int 78 (pcie_link0)", 376 [ 79] = "pic int 79 (pcie_link1)", 377 [ 80] = "pic int 80 (pcie_link2)", 378 [ 81] = "pic int 81 (pcie_link3)", 379 [ 82] = "pic int 82 (nae0)", 380 [ 83] = "pic int 83 (nae1)", 381 [ 84] = "pic int 84 (nae2)", 382 [ 85] = "pic int 85 (nae3)", 383 [ 86] = "pic int 86 (nae4)", 384 [ 87] = "pic int 87 (nae5)", 385 [ 88] = "pic int 88 (nae6)", 386 [ 89] = "pic int 89 (nae7)", 387 [ 90] = "pic int 90 (nae8)", 388 [ 91] = "pic int 91 (nae9)", 389 [ 92] = "pic int 92 (nae10)", 390 [ 93] = "pic int 93 (nae11)", 391 [ 94] = "pic int 94 (nae12)", 392 [ 95] = "pic int 95 (nae13)", 393 [ 96] = "pic int 96 (nae14)", 394 [ 97] = "pic int 97 (nae15)", 395 [ 98] = "pic int 98 (nae16)", 396 [ 99] = "pic int 99 (nae17)", 397 [100] = "pic int 100 (nae18)", 398 [101] = "pic int 101 (?)", 399 [102] = "pic int 102 (naecom0)", 400 [103] = "pic int 103 (naecom1)", 401 [104] = "pic int 104 (?)", 402 [105] = "pic int 105 (?)", 403 [106] = "pic int 106 (?)", 404 [107] = "pic int 107 (?)", 405 [108] = "pic int 108 (?)", 406 [109] = "pic int 109 (?)", 407 [110] = "pic int 100 (?)", 408 [111] = "pic int 111 (?)", 409 [112] = "pic int 112 (?)", 410 [113] = "pic int 113 (?)", 411 [114] = "pic int 114 (poe)", 412 [115] = "pic int 115 (ehci0)", 413 [116] = "pic int 116 (ohci0)", 414 [117] = "pic int 117 (ohci1)", 415 [118] = "pic int 118 (ehci1)", 416 [119] = "pic int 119 (ohci2)", 417 [120] = "pic int 120 (ohci3)", 418 [121] = "pic int 121 (dma)", 419 [122] = "pic int 122 (sae)", 420 [123] = "pic int 123 (pke)", 421 [124] = "pic int 124 (cde0)", 422 [125] = "pic int 125 (cde1)", 423 [126] = "pic int 126 (cde2)", 424 [127] = "pic int 127 (cde3)", 425 [128] = "pic int 128 (?)", 426 [129] = "pic int 129 (ici0)", 427 [130] = "pic int 130 (ici1)", 428 [131] = "pic int 131 (ici2)", 429 [132] = "pic int 132 (kbp)", 430 [133] = "pic int 133 (uart0)", 431 [134] = "pic int 134 (uart1)", 432 [135] = "pic int 135 (i2c0)", 433 [136] = "pic int 136 (i2c1)", 434 [137] = "pic int 137 (sysmgt0)", 435 [138] = "pic int 138 (sysmgt1)", 436 [139] = "pic int 139 (jtag)", 437 [140] = "pic int 140 (pic)", 438 [141] = "pic int 141 (?)", 439 [142] = "pic int 142 (?)", 440 [143] = "pic int 143 (?)", 441 [144] = "pic int 144 (?)", 442 [145] = "pic int 145 (?)", 443 [146] = "pic int 146 (gpio0)", 444 [147] = "pic int 147 (gpio1)", 445 [148] = "pic int 148 (gpio2)", 446 [149] = "pic int 149 (gpio3)", 447 [150] = "pic int 150 (norflash)", 448 [151] = "pic int 151 (nandflash)", 449 [152] = "pic int 152 (spi)", 450 [153] = "pic int 153 (mmc/sd)", 451 [154] = "pic int 154 (mem-io-bridge)", 452 [155] = "pic int 155 (l3)", 453 [156] = "pic int 156 (gcu)", 454 [157] = "pic int 157 (dram3_0)", 455 [158] = "pic int 158 (dram3_1)", 456 [159] = "pic int 159 (tracebuf)", 457 }; 458 459 /* 460 * rmixl_irtnames_xlp: 461 * - use for XLP 462 */ 463 static const char * const rmixl_irtnames_xlp3xx[RMIXLP_NIRTS] = { 464 [ 0] = "pic int 0 (watchdog0)", 465 [ 1] = "pic int 1 (watchdog1)", 466 [ 2] = "pic int 2 (watchdogNMI0)", 467 [ 3] = "pic int 3 (watchdogNMI1)", 468 [ 4] = "pic int 4 (timer0)", 469 [ 5] = "pic int 5 (timer1)", 470 [ 6] = "pic int 6 (timer2)", 471 [ 7] = "pic int 7 (timer3)", 472 [ 8] = "pic int 8 (timer4)", 473 [ 9] = "pic int 9 (timer5)", 474 [ 10] = "pic int 10 (timer6)", 475 [ 11] = "pic int 11 (timer7)", 476 [ 12] = "pic int 12 (gpio0)", 477 [ 13] = "pic int 13 (gpio1)", 478 [ 14] = "pic int 14 (gpio2)", 479 [ 15] = "pic int 15 (gpio3)", 480 [ 16] = "pic int 16 (gpio4)", 481 [ 17] = "pic int 17 (gpio5)", 482 [ 18] = "pic int 18 (gpio6)", 483 [ 19] = "pic int 19 (gpio7)", 484 [ 20] = "pic int 20 (gpio8)", 485 [ 21] = "pic int 21 (gpio0)", 486 [ 22] = "pic int 22 (gpio10)", 487 [ 23] = "pic int 23 (gpio11)", 488 [ 24] = "pic int 24 (?)", 489 [ 25] = "pic int 25 (?)", 490 [ 26] = "pic int 26 (?)", 491 [ 27] = "pic int 27 (?)", 492 [ 28] = "pic int 28 (fmn0)", 493 [ 29] = "pic int 29 (fmn1)", 494 [ 30] = "pic int 30 (fmn2)", 495 [ 31] = "pic int 31 (fmn3)", 496 [ 32] = "pic int 22 (fmn4)", 497 [ 33] = "pic int 23 (fmn5)", 498 [ 34] = "pic int 24 (fmn6)", 499 [ 35] = "pic int 25 (fmn7)", 500 [ 36] = "pic int 26 (fmn8)", 501 [ 37] = "pic int 27 (fmn9)", 502 [ 38] = "pic int 28 (fmn10)", 503 [ 39] = "pic int 29 (fmn11)", 504 [ 40] = "pic int 30 (fmn12)", 505 [ 41] = "pic int 31 (fmn13)", 506 [ 42] = "pic int 42 (fmn14)", 507 [ 43] = "pic int 43 (fmn15)", 508 [ 44] = "pic int 44 (fmnerr0)", 509 [ 45] = "pic int 45 (fmnerr1)", 510 [ 46] = "pic int 46 (pcie_msix0)", 511 [ 47] = "pic int 47 (pcie_msix1)", 512 [ 48] = "pic int 48 (pcie_msix2)", 513 [ 49] = "pic int 49 (pcie_msix3)", 514 [ 50] = "pic int 50 (pcie_msix4)", 515 [ 51] = "pic int 51 (pcie_msix5)", 516 [ 52] = "pic int 52 (pcie_msix6)", 517 [ 53] = "pic int 53 (pcie_msix7)", 518 [ 54] = "pic int 54 (pcie_msix8)", 519 [ 55] = "pic int 55 (pcie_msix9)", 520 [ 56] = "pic int 56 (pcie_msix10)", 521 [ 57] = "pic int 57 (pcie_msix11)", 522 [ 58] = "pic int 58 (pcie_msix12)", 523 [ 59] = "pic int 59 (pcie_msix13)", 524 [ 60] = "pic int 60 (pcie_msix14)", 525 [ 61] = "pic int 61 (pcie_msix15)", 526 [ 62] = "pic int 62 (pcie_msix16)", 527 [ 63] = "pic int 63 (pcie_msix17)", 528 [ 64] = "pic int 64 (pcie_msix18)", 529 [ 65] = "pic int 65 (pcie_msix19)", 530 [ 66] = "pic int 66 (pcie_msix20)", 531 [ 67] = "pic int 67 (pcie_msix21)", 532 [ 68] = "pic int 68 (pcie_msix22)", 533 [ 69] = "pic int 69 (pcie_msix23)", 534 [ 70] = "pic int 70 (pcie_msix24)", 535 [ 71] = "pic int 71 (pcie_msix25)", 536 [ 72] = "pic int 72 (pcie_msix26)", 537 [ 73] = "pic int 73 (pcie_msix27)", 538 [ 74] = "pic int 74 (pcie_msix28)", 539 [ 75] = "pic int 75 (pcie_msix29)", 540 [ 76] = "pic int 76 (pcie_msix30)", 541 [ 77] = "pic int 77 (pcie_msix31)", 542 [ 78] = "pic int 78 (pcie_link0)", 543 [ 79] = "pic int 79 (pcie_link1)", 544 [ 80] = "pic int 80 (pcie_link2)", 545 [ 81] = "pic int 81 (pcie_link3)", 546 [ 82] = "pic int 82 (?)", 547 [ 83] = "pic int 83 (?)", 548 [ 84] = "pic int 84 (?)", 549 [ 85] = "pic int 85 (?)", 550 [ 86] = "pic int 86 (?)", 551 [ 87] = "pic int 87 (?)", 552 [ 88] = "pic int 88 (?)", 553 [ 89] = "pic int 89 (?)", 554 [ 90] = "pic int 90 (?)", 555 [ 91] = "pic int 91 (?)", 556 [ 92] = "pic int 92 (?)", 557 [ 93] = "pic int 93 (?)", 558 [ 94] = "pic int 94 (?)", 559 [ 95] = "pic int 95 (?)", 560 [ 96] = "pic int 96 (?)", 561 [ 97] = "pic int 97 (?)", 562 [ 98] = "pic int 98 (nae0)", 563 [ 99] = "pic int 99 (nae1)", 564 [100] = "pic int 100 (nae2)", 565 [101] = "pic int 101 (nae3)", 566 [102] = "pic int 102 (nae4)", 567 [103] = "pic int 103 (nae5)", 568 [104] = "pic int 104 (nae6)", 569 [105] = "pic int 105 (nae7)", 570 [106] = "pic int 106 (nae8)", 571 [107] = "pic int 107 (?)", 572 [108] = "pic int 108 (?)", 573 [109] = "pic int 109 (?)", 574 [110] = "pic int 100 (naecom0)", 575 [111] = "pic int 111 (naecom1)", 576 [112] = "pic int 112 (?)", 577 [113] = "pic int 113 (?)", 578 [114] = "pic int 114 (poe)", 579 [115] = "pic int 115 (ehci0)", 580 [116] = "pic int 116 (ohci0)", 581 [117] = "pic int 117 (ohci1)", 582 [118] = "pic int 118 (ehci1)", 583 [119] = "pic int 119 (ohci2)", 584 [120] = "pic int 120 (ohci3)", 585 [121] = "pic int 121 (dma)", 586 [122] = "pic int 122 (sae)", 587 [123] = "pic int 123 (pke)", 588 [124] = "pic int 124 (?)", 589 [125] = "pic int 125 (?)", 590 [126] = "pic int 126 (?)", 591 [127] = "pic int 127 (?)", 592 [128] = "pic int 128 (?)", 593 [129] = "pic int 129 (?)", 594 [130] = "pic int 130 (?)", 595 [131] = "pic int 131 (?)", 596 [132] = "pic int 132 (?)", 597 [133] = "pic int 133 (uart0)", 598 [134] = "pic int 134 (uart1)", 599 [135] = "pic int 135 (i2c0)", 600 [136] = "pic int 136 (i2c1)", 601 [137] = "pic int 137 (sysmgt0)", 602 [138] = "pic int 138 (sysmgt1)", 603 [139] = "pic int 139 (jtag)", 604 [140] = "pic int 140 (pic)", 605 [141] = "pic int 141 (rxe0)", 606 [142] = "pic int 142 (rxe1)", 607 [143] = "pic int 143 (sata)", 608 [144] = "pic int 144 (srio0)", 609 [145] = "pic int 145 (srio1)", 610 [146] = "pic int 146 (srio2)", 611 [147] = "pic int 147 (srio3)", 612 [148] = "pic int 148 (srio4)", 613 [149] = "pic int 149 (?)", 614 [150] = "pic int 150 (norflash)", 615 [151] = "pic int 151 (nandflash)", 616 [152] = "pic int 152 (spi)", 617 [153] = "pic int 153 (mmc/sd)", 618 [154] = "pic int 154 (mem-io-bridge)", 619 [155] = "pic int 155 (l3)", 620 [156] = "pic int 156 (?)", 621 [157] = "pic int 157 (dram3_0)", 622 [158] = "pic int 158 (dram3_1)", 623 [159] = "pic int 159 (tracebuf)", 624 }; 625 626 #endif /* MIPS64_XLP */ 627 /* 628 * rmixl_vecnames_common: 629 * - use for unknown cpu implementation 630 * - covers all vectors, not just IRT intrs 631 */ 632 static const char * const rmixl_vecnames_common[NINTRVECS] = { 633 "vec 0 (sw0)", /* 0 */ 634 "vec 1 (sw1)", /* 1 */ 635 "vec 2 (hw2)", /* 2 */ 636 "vec 3 (hw3)", /* 3 */ 637 "vec 4 (hw4)", /* 4 */ 638 "vec 5 (hw5)", /* 5 */ 639 "vec 6 (hw6)", /* 6 */ 640 "vec 7 (hw7)", /* 7 */ 641 "vec 8", /* 8 */ 642 "vec 9", /* 9 */ 643 "vec 10", /* 10 */ 644 "vec 11", /* 11 */ 645 "vec 12", /* 12 */ 646 "vec 13", /* 13 */ 647 "vec 14", /* 14 */ 648 "vec 15", /* 15 */ 649 "vec 16", /* 16 */ 650 "vec 17", /* 17 */ 651 "vec 18", /* 18 */ 652 "vec 19", /* 19 */ 653 "vec 20", /* 20 */ 654 "vec 21", /* 21 */ 655 "vec 22", /* 22 */ 656 "vec 23", /* 23 */ 657 "vec 24", /* 24 */ 658 "vec 25", /* 25 */ 659 "vec 26", /* 26 */ 660 "vec 27", /* 27 */ 661 "vec 28", /* 28 */ 662 "vec 29", /* 29 */ 663 "vec 30", /* 30 */ 664 "vec 31", /* 31 */ 665 "vec 32", /* 32 */ 666 "vec 33", /* 33 */ 667 "vec 34", /* 34 */ 668 "vec 35", /* 35 */ 669 "vec 36", /* 36 */ 670 "vec 37", /* 37 */ 671 "vec 38", /* 38 */ 672 "vec 39", /* 39 */ 673 "vec 40", /* 40 */ 674 "vec 41", /* 41 */ 675 "vec 42", /* 42 */ 676 "vec 43", /* 43 */ 677 "vec 44", /* 44 */ 678 "vec 45", /* 45 */ 679 "vec 46", /* 46 */ 680 "vec 47", /* 47 */ 681 "vec 48", /* 48 */ 682 "vec 49", /* 49 */ 683 "vec 50", /* 50 */ 684 "vec 51", /* 51 */ 685 "vec 52", /* 52 */ 686 "vec 53", /* 53 */ 687 "vec 54", /* 54 */ 688 "vec 55", /* 55 */ 689 "vec 56", /* 56 */ 690 "vec 57", /* 57 */ 691 "vec 58", /* 58 */ 692 "vec 59", /* 59 */ 693 "vec 60", /* 60 */ 694 "vec 61", /* 61 */ 695 "vec 62", /* 63 */ 696 "vec 63", /* 63 */ 697 }; 698 699 /* 700 * mask of CPUs attached 701 * once they are attached, this var is read-only so mp safe 702 */ 703 static __cpuset_t cpu_present_mask; 704 705 kmutex_t *rmixl_ipi_lock; /* covers RMIXL_PIC_IPIBASE */ 706 kmutex_t *rmixl_intr_lock; /* covers rest of PIC, and rmixl_intrhand[] */ 707 rmixl_intrvecq_t rmixl_intrvec_lruq[_IPL_N] = { 708 [IPL_NONE] = TAILQ_HEAD_INITIALIZER(rmixl_intrvec_lruq[IPL_NONE]), 709 [IPL_SOFTCLOCK] = TAILQ_HEAD_INITIALIZER(rmixl_intrvec_lruq[IPL_SOFTCLOCK]), 710 [IPL_SOFTNET] = TAILQ_HEAD_INITIALIZER(rmixl_intrvec_lruq[IPL_SOFTNET]), 711 [IPL_VM] = TAILQ_HEAD_INITIALIZER(rmixl_intrvec_lruq[IPL_VM]), 712 [IPL_SCHED] = TAILQ_HEAD_INITIALIZER(rmixl_intrvec_lruq[IPL_SCHED]), 713 [IPL_DDB] = TAILQ_HEAD_INITIALIZER(rmixl_intrvec_lruq[IPL_DDB]), 714 [IPL_HIGH] = TAILQ_HEAD_INITIALIZER(rmixl_intrvec_lruq[IPL_HIGH]), 715 }; 716 rmixl_intrvec_t rmixl_intrvec[NINTRVECS]; 717 rmixl_intrhand_t rmixl_irt_intrhands[MAX(MAX(RMIXLR_NIRTS,RMIXLS_NIRTS), RMIXLP_NIRTS)]; 718 static u_int rmixl_nirts; 719 const char * const *rmixl_irtnames; 720 721 #ifdef DIAGNOSTIC 722 static int rmixl_pic_init_done; 723 #endif 724 725 726 static uint32_t rmixl_irt_thread_mask(__cpuset_t); 727 static void rmixl_irt_init(size_t); 728 static void rmixl_irt_disestablish(size_t); 729 static void rmixl_irt_establish(size_t, size_t, int); 730 static size_t rmixl_intr_get_vec(int); 731 732 #ifdef MULTIPROCESSOR 733 static int rmixl_send_ipi(struct cpu_info *, int); 734 static int rmixl_ipi_intr(void *); 735 #endif 736 737 #if defined(DIAGNOSTIC) || defined(IOINTR_DEBUG) || defined(DDB) 738 int rmixl_intrvec_print_subr(size_t); 739 int rmixl_intrhand_print(void); 740 int rmixl_irt_print(void); 741 void rmixl_ipl_eimr_map_print(void); 742 #endif 743 744 745 static inline u_int 746 dclz(uint64_t val) 747 { 748 u_int nlz; 749 750 __asm volatile("dclz %0, %1" : "=r"(nlz) : "r"(val)); 751 752 return nlz; 753 } 754 755 void 756 evbmips_intr_init(void) 757 { 758 const bool is_xlp_p = cpu_rmixlp(mips_options.mips_cpu); 759 const bool is_xlr_p = cpu_rmixlr(mips_options.mips_cpu); 760 const bool is_xls_p = cpu_rmixls(mips_options.mips_cpu); 761 762 KASSERT(is_xlp_p || is_xlr_p || is_xls_p); 763 764 /* 765 * The number of IRT entries is different for XLP .vs. XLR/XLS. 766 */ 767 if (is_xlp_p) { 768 #ifdef MIPS64_XLP 769 if (rmixl_xlp_variant >= RMIXLP_3XX) { 770 rmixl_irtnames = rmixl_irtnames_xlp3xx; 771 rmixl_nirts = __arraycount(rmixl_irtnames_xlp3xx); 772 } else { 773 rmixl_irtnames = rmixl_irtnames_xlp8xx; 774 rmixl_nirts = __arraycount(rmixl_irtnames_xlp8xx); 775 } 776 #endif 777 } else if (is_xlr_p) { 778 #ifdef MIPS64_XLR 779 rmixl_irtnames = rmixl_irtnames_xlrxxx; 780 rmixl_nirts = __arraycount(rmixl_irtnames_xlrxxx); 781 #endif 782 } else if (is_xls_p) { 783 #ifdef MIPS64_XLS 784 switch (MIPS_PRID_IMPL(mips_options.mips_cpu_id)) { 785 case MIPS_XLS104: 786 case MIPS_XLS108: 787 case MIPS_XLS404LITE: 788 case MIPS_XLS408LITE: 789 rmixl_irtnames = rmixl_irtnames_xls1xx; 790 rmixl_nirts = __arraycount(rmixl_irtnames_xls1xx); 791 break; 792 case MIPS_XLS204: 793 case MIPS_XLS208: 794 rmixl_irtnames = rmixl_irtnames_xls2xx; 795 rmixl_nirts = __arraycount(rmixl_irtnames_xls2xx); 796 break; 797 case MIPS_XLS404: 798 case MIPS_XLS408: 799 case MIPS_XLS416: 800 case MIPS_XLS608: 801 case MIPS_XLS616: 802 rmixl_irtnames = rmixl_irtnames_xls4xx; 803 rmixl_nirts = __arraycount(rmixl_irtnames_xls4xx); 804 break; 805 default: 806 rmixl_irtnames = rmixl_vecnames_common; 807 rmixl_nirts = __arraycount(rmixl_vecnames_common); 808 break; 809 } 810 #endif /* MIPS64_XLS */ 811 } 812 813 #ifdef DIAGNOSTIC 814 if (rmixl_pic_init_done != 0) 815 panic("%s: rmixl_pic_init_done %d", 816 __func__, rmixl_pic_init_done); 817 #endif 818 819 rmixl_ipi_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_HIGH); 820 rmixl_intr_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_HIGH); 821 822 mutex_enter(rmixl_intr_lock); 823 824 /* 825 * Insert all non-IPI non-normal MIPS vectors on lru queue. 826 */ 827 for (size_t i = RMIXL_INTRVEC_IPI; i < NINTRVECS; i++) { 828 TAILQ_INSERT_TAIL(&rmixl_intrvec_lruq[IPL_NONE], 829 &rmixl_intrvec[i], iv_lruq_link); 830 } 831 832 /* 833 * initialize (zero) all IRT Entries in the PIC 834 */ 835 for (size_t i = 0; i < rmixl_nirts; i++) { 836 rmixl_irt_init(i); 837 } 838 839 /* 840 * disable watchdog NMI, timers 841 */ 842 if (is_xlp_p) { 843 /* 844 * Reset the interrupt thread enables to disable all CPUs. 845 */ 846 for (size_t i = 0; i < 8; i++) { 847 RMIXLP_PICREG_WRITE(RMIXLP_PIC_INT_THREAD_ENABLE01(i), 0); 848 RMIXLP_PICREG_WRITE(RMIXLP_PIC_INT_THREAD_ENABLE23(i), 0); 849 } 850 851 /* 852 * Enable interrupts for node 0 core 0 thread 0. 853 */ 854 RMIXLP_PICREG_WRITE(RMIXLP_PIC_INT_THREAD_ENABLE01(0), 1); 855 856 /* 857 * Disable watchdogs and system timers. 858 */ 859 uint64_t r = RMIXLP_PICREG_READ(RMIXLP_PIC_CTRL); 860 r &= ~(RMIXLP_PIC_CTRL_WTE|RMIXLP_PIC_CTRL_STE); 861 RMIXLP_PICREG_WRITE(RMIXLP_PIC_CTRL, r); 862 } else { 863 /* 864 * XXX 865 * WATCHDOG_ENB is preserved because clearing it causes 866 * hang on the XLS616 (but not on the XLS408) 867 */ 868 uint32_t r = RMIXL_PICREG_READ(RMIXL_PIC_CONTROL); 869 r &= RMIXL_PIC_CONTROL_RESV|RMIXL_PIC_CONTROL_WATCHDOG_ENB; 870 RMIXL_PICREG_WRITE(RMIXL_PIC_CONTROL, r); 871 } 872 873 #ifdef DIAGNOSTIC 874 rmixl_pic_init_done = 1; 875 #endif 876 mutex_exit(rmixl_intr_lock); 877 } 878 879 /* 880 * establish vector for mips3 count/compare clock interrupt 881 * this ensures we enable in EIRR, 882 * even though cpu_intr() handles the interrupt 883 * note the 'mpsafe' arg here is a placeholder only 884 */ 885 void 886 rmixl_intr_init_clk(void) 887 { 888 const size_t vec = ffs(MIPS_INT_MASK_5 >> MIPS_INT_MASK_SHIFT) - 1; 889 890 mutex_enter(rmixl_intr_lock); 891 892 void *ih = rmixl_vec_establish(vec, NULL, IPL_SCHED, NULL, NULL, false); 893 if (ih == NULL) 894 panic("%s: establish vec %zu failed", __func__, vec); 895 896 mutex_exit(rmixl_intr_lock); 897 } 898 899 #ifdef MULTIPROCESSOR 900 /* 901 * establish IPI interrupt and send function 902 */ 903 void 904 rmixl_intr_init_ipi(void) 905 { 906 mutex_enter(rmixl_intr_lock); 907 908 for (size_t ipi = 0; ipi < NIPIS; ipi++) { 909 const size_t vec = RMIXL_INTRVEC_IPI + ipi; 910 void * const ih = rmixl_vec_establish(vec, NULL, IPL_SCHED, 911 rmixl_ipi_intr, (void *)(uintptr_t)ipi, true); 912 if (ih == NULL) 913 panic("%s: establish ipi %zu at vec %zu failed", 914 __func__, ipi, vec); 915 } 916 917 mips_locoresw.lsw_send_ipi = rmixl_send_ipi; 918 919 mutex_exit(rmixl_intr_lock); 920 } 921 #endif /* MULTIPROCESSOR */ 922 923 /* 924 * initialize per-cpu interrupt stuff in softc 925 * accumulate per-cpu bits in 'cpu_present_mask' 926 */ 927 void 928 rmixl_intr_init_cpu(struct cpu_info *ci) 929 { 930 struct rmixl_cpu_softc * const sc = (void *)ci->ci_softc; 931 const char * xname = device_xname(sc->sc_dev); 932 933 KASSERT(sc != NULL); 934 KASSERT(NINTRVECS <= __arraycount(sc->sc_vec_evcnts)); 935 KASSERT(rmixl_nirts <= __arraycount(sc->sc_irt_evcnts)); 936 937 for (size_t vec = 0; vec < NINTRVECS; vec++) { 938 evcnt_attach_dynamic(&sc->sc_vec_evcnts[vec], 939 EVCNT_TYPE_INTR, NULL, xname, rmixl_intr_string(vec)); 940 } 941 942 for (size_t irt = 0; irt < rmixl_nirts; irt++) { 943 evcnt_attach_dynamic(&sc->sc_irt_evcnts[irt], 944 EVCNT_TYPE_INTR, NULL, xname, rmixl_irtnames[irt]); 945 } 946 947 KASSERT(cpu_index(ci) < (sizeof(cpu_present_mask) * 8)); 948 atomic_or_32((volatile uint32_t *)&cpu_present_mask, 1 << cpu_index(ci)); 949 } 950 951 const char * 952 rmixl_irt_string(size_t irt) 953 { 954 KASSERT(irt < rmixl_nirts); 955 956 return rmixl_irtnames[irt]; 957 } 958 959 /* 960 * rmixl_intr_string - return pointer to display name of a PIC-based interrupt 961 */ 962 const char * 963 rmixl_intr_string(size_t vec) 964 { 965 966 if (vec >= NINTRVECS) 967 panic("%s: vec index %zu out of range, max %d", 968 __func__, vec, NINTRVECS - 1); 969 970 return rmixl_vecnames_common[vec]; 971 } 972 973 size_t 974 rmixl_intr_get_vec(int ipl) 975 { 976 KASSERT(mutex_owned(rmixl_intr_lock)); 977 KASSERT(IPL_VM <= ipl && ipl <= IPL_HIGH); 978 979 /* 980 * In reality higer ipls should have higher vec numbers, 981 * but for now don't worry about it. 982 */ 983 struct rmixl_intrvecq * freeq = &rmixl_intrvec_lruq[IPL_NONE]; 984 struct rmixl_intrvecq * iplq = &rmixl_intrvec_lruq[ipl]; 985 rmixl_intrvec_t *iv; 986 987 /* 988 * If there's a free vector, grab it otherwise choose the least 989 * recently assigned vector sharing this IPL. 990 */ 991 if ((iv = TAILQ_FIRST(freeq)) == NULL) { 992 iv = TAILQ_FIRST(iplq); 993 KASSERT(iv != NULL); 994 } 995 996 return iv - rmixl_intrvec; 997 } 998 999 /* 1000 * rmixl_irt_thread_mask 1001 * 1002 * given a bitmask of cpus, return a, IRT thread mask 1003 */ 1004 static uint32_t 1005 rmixl_irt_thread_mask(__cpuset_t cpumask) 1006 { 1007 uint32_t irtc0; 1008 1009 #if defined(MULTIPROCESSOR) 1010 #ifndef NOTYET 1011 if (cpumask == -1) 1012 return 1; /* XXX TMP FIXME */ 1013 #endif 1014 1015 /* 1016 * discount cpus not present 1017 */ 1018 cpumask &= cpu_present_mask; 1019 1020 switch (MIPS_PRID_IMPL(mips_options.mips_cpu_id)) { 1021 case MIPS_XLS104: 1022 case MIPS_XLS204: 1023 case MIPS_XLS404: 1024 case MIPS_XLS404LITE: 1025 irtc0 = ((cpumask >> 2) << 4) | (cpumask & __BITS(1,0)); 1026 irtc0 &= (__BITS(5,4) | __BITS(1,0)); 1027 break; 1028 case MIPS_XLS108: 1029 case MIPS_XLS208: 1030 case MIPS_XLS408: 1031 case MIPS_XLS408LITE: 1032 case MIPS_XLS608: 1033 irtc0 = cpumask & __BITS(7,0); 1034 break; 1035 case MIPS_XLS416: 1036 case MIPS_XLS616: 1037 irtc0 = cpumask & __BITS(15,0); 1038 break; 1039 default: 1040 panic("%s: unknown cpu ID %#x\n", __func__, 1041 mips_options.mips_cpu_id); 1042 } 1043 #else 1044 irtc0 = 1; 1045 #endif /* MULTIPROCESSOR */ 1046 1047 return irtc0; 1048 } 1049 1050 /* 1051 * rmixl_irt_init 1052 * - initialize IRT Entry for given index 1053 * - unmask Thread#0 in low word (assume we only have 1 thread) 1054 */ 1055 static void 1056 rmixl_irt_init(size_t irt) 1057 { 1058 KASSERT(irt < rmixl_nirts); 1059 if (cpu_rmixlp(mips_options.mips_cpu)) { 1060 RMIXLP_PICREG_WRITE(RMIXLP_PIC_IRTENTRY(irt), 0); 1061 } else { 1062 RMIXL_PICREG_WRITE(RMIXL_PIC_IRTENTRYC1(irt), 0); /* high word */ 1063 RMIXL_PICREG_WRITE(RMIXL_PIC_IRTENTRYC0(irt), 0); /* low word */ 1064 } 1065 } 1066 1067 /* 1068 * rmixl_irt_disestablish 1069 * - invalidate IRT Entry for given index 1070 */ 1071 static void 1072 rmixl_irt_disestablish(size_t irt) 1073 { 1074 KASSERT(mutex_owned(rmixl_intr_lock)); 1075 DPRINTF(("%s: irt %zu, irtc1 %#x\n", __func__, irt, 0)); 1076 rmixl_irt_init(irt); 1077 } 1078 1079 /* 1080 * rmixl_irt_establish 1081 * - construct an IRT Entry for irt and write to PIC 1082 */ 1083 static void 1084 rmixl_irt_establish(size_t irt, size_t vec, int ist) 1085 { 1086 const bool is_xlp_p = cpu_rmixlp(mips_options.mips_cpu); 1087 1088 KASSERT(mutex_owned(rmixl_intr_lock)); 1089 1090 if (irt >= rmixl_nirts) 1091 panic("%s: bad irt %zu\n", __func__, irt); 1092 1093 /* 1094 * All XLP interrupt are level (high). 1095 */ 1096 if (ist != IST_LEVEL && ist != IST_LEVEL_HIGH 1097 && (is_xlp_p 1098 || (ist != IST_EDGE 1099 && ist != IST_EDGE_FALLING 1100 && ist != IST_EDGE_RISING))) { 1101 panic("%s: bad ist %d\n", __func__, ist); 1102 } 1103 1104 /* 1105 * XXX IRT entries are not shared 1106 */ 1107 if (is_xlp_p) { 1108 KASSERT(RMIXLP_PICREG_READ(RMIXLP_PIC_IRTENTRY(irt)) == 0); 1109 uint64_t irtc0 = RMIXLP_PIC_IRTENTRY_EN 1110 | RMIXLP_PIC_IRTENTRY_LOCAL 1111 | RMIXLP_PIC_IRTENTRY_DT_ITE 1112 | RMIXLP_PIC_IRTENTRY_ITE(0) 1113 | __SHIFTIN(vec, RMIXLP_PIC_IRTENTRY_INTVEC) 1114 1115 /* 1116 * write IRT Entry to PIC 1117 */ 1118 DPRINTF(("%s: vec %zu (%#x), irt %zu (%s), irtc0 %#"PRIx64"\n", 1119 __func__, vec, vec, irt, rmixl_irtnames[irt], irtc0)); 1120 1121 RMIXLP_PICREG_WRITE(RMIXLP_PIC_IRTENTRY(irt), irtc0); 1122 } else { 1123 KASSERT(RMIXL_PICREG_READ(RMIXL_PIC_IRTENTRYC0(irt)) == 0); 1124 KASSERT(RMIXL_PICREG_READ(RMIXL_PIC_IRTENTRYC1(irt)) == 0); 1125 1126 __cpuset_t cpumask = 1; /* XXX */ 1127 uint32_t irtc0 = rmixl_irt_thread_mask(cpumask); 1128 1129 uint32_t irtc1 = RMIXL_PIC_IRTENTRYC1_VALID; 1130 irtc1 |= RMIXL_PIC_IRTENTRYC1_GL; /* local */ 1131 KASSERT((irtc1 & RMIXL_PIC_IRTENTRYC1_NMI) == 0); 1132 1133 if (ist == IST_LEVEL 1134 || ist == IST_LEVEL_LOW 1135 || ist == IST_LEVEL_HIGH) 1136 irtc1 |= RMIXL_PIC_IRTENTRYC1_TRG; 1137 KASSERT((irtc1 & RMIXL_PIC_IRTENTRYC1_NMI) == 0); 1138 1139 if (ist == IST_LEVEL_LOW || ist == IST_EDGE_FALLING) 1140 irtc1 |= RMIXL_PIC_IRTENTRYC1_P; 1141 KASSERT((irtc1 & RMIXL_PIC_IRTENTRYC1_NMI) == 0); 1142 1143 irtc1 |= vec; /* vector in EIRR */ 1144 KASSERT((irtc1 & RMIXL_PIC_IRTENTRYC1_NMI) == 0); 1145 1146 /* 1147 * write IRT Entry to PIC 1148 */ 1149 DPRINTF(("%s: vec %zu (%#x), irt %zu, irtc0 %#x, irtc1 %#x\n", 1150 __func__, vec, vec, irt, irtc0, irtc1)); 1151 RMIXL_PICREG_WRITE(RMIXL_PIC_IRTENTRYC0(irt), irtc0); /* low word */ 1152 RMIXL_PICREG_WRITE(RMIXL_PIC_IRTENTRYC1(irt), irtc1); /* high word */ 1153 } 1154 } 1155 1156 void * 1157 rmixl_vec_establish(size_t vec, rmixl_intrhand_t *ih, int ipl, 1158 int (*func)(void *), void *arg, bool mpsafe) 1159 { 1160 1161 KASSERT(mutex_owned(rmixl_intr_lock)); 1162 1163 DPRINTF(("%s: vec %zu ih %p ipl %d func %p arg %p mpsafe %d\n", 1164 __func__, vec, ih, ipl, func, arg, mpsafe)); 1165 1166 #ifdef DIAGNOSTIC 1167 if (rmixl_pic_init_done == 0) 1168 panic("%s: called before evbmips_intr_init", __func__); 1169 #endif 1170 1171 /* 1172 * check args 1173 */ 1174 if (vec >= NINTRVECS) 1175 panic("%s: vec %zu out of range, max %d", 1176 __func__, vec, NINTRVECS - 1); 1177 if (ipl < IPL_VM || ipl > IPL_HIGH) 1178 panic("%s: ipl %d out of range, min %d, max %d", 1179 __func__, ipl, IPL_VM, IPL_HIGH); 1180 1181 const int s = splhigh(); 1182 1183 rmixl_intrvec_t * const iv = &rmixl_intrvec[vec]; 1184 if (ih == NULL) { 1185 ih = &iv->iv_intrhand; 1186 } 1187 1188 if (vec >= 8) { 1189 TAILQ_REMOVE(&rmixl_intrvec_lruq[iv->iv_ipl], iv, iv_lruq_link); 1190 } 1191 1192 if (LIST_EMPTY(&iv->iv_hands)) { 1193 KASSERT(iv->iv_ipl == IPL_NONE); 1194 iv->iv_ipl = ipl; 1195 } else { 1196 KASSERT(iv->iv_ipl == ipl); 1197 } 1198 1199 if (vec >= 8) { 1200 TAILQ_INSERT_TAIL(&rmixl_intrvec_lruq[iv->iv_ipl], 1201 iv, iv_lruq_link); 1202 } 1203 1204 if (ih->ih_func != NULL) { 1205 #ifdef DIAGNOSTIC 1206 printf("%s: intrhand[%zu] busy\n", __func__, vec); 1207 #endif 1208 splx(s); 1209 return NULL; 1210 } 1211 1212 ih->ih_arg = arg; 1213 ih->ih_mpsafe = mpsafe; 1214 ih->ih_vec = vec; 1215 1216 LIST_INSERT_HEAD(&iv->iv_hands, ih, ih_link); 1217 1218 const uint64_t eimr_bit = (uint64_t)1 << vec; 1219 for (int i = ipl; --i >= 0; ) { 1220 KASSERT((ipl_eimr_map[i] & eimr_bit) == 0); 1221 ipl_eimr_map[i] |= eimr_bit; 1222 } 1223 1224 ih->ih_func = func; /* do this last */ 1225 1226 splx(s); 1227 1228 return ih; 1229 } 1230 1231 /* 1232 * rmixl_intr_establish 1233 * - used to establish an IRT-based interrupt only 1234 */ 1235 void * 1236 rmixl_intr_establish(size_t irt, int ipl, int ist, 1237 int (*func)(void *), void *arg, bool mpsafe) 1238 { 1239 #ifdef DIAGNOSTIC 1240 if (rmixl_pic_init_done == 0) 1241 panic("%s: called before rmixl_pic_init_done", __func__); 1242 #endif 1243 1244 /* 1245 * check args 1246 */ 1247 if (irt >= rmixl_nirts) 1248 panic("%s: irt %zu out of range, max %d", 1249 __func__, irt, rmixl_nirts - 1); 1250 if (ipl < IPL_VM || ipl > IPL_HIGH) 1251 panic("%s: ipl %d out of range, min %d, max %d", 1252 __func__, ipl, IPL_VM, IPL_HIGH); 1253 1254 mutex_enter(rmixl_intr_lock); 1255 1256 rmixl_intrhand_t *ih = &rmixl_irt_intrhands[irt]; 1257 1258 KASSERT(ih->ih_func == NULL); 1259 1260 const size_t vec = rmixl_intr_get_vec(ipl); 1261 1262 DPRINTF(("%s: irt %zu, ih %p vec %zu, ipl %d\n", 1263 __func__, irt, ih, vec, ipl)); 1264 1265 /* 1266 * establish vector 1267 */ 1268 ih = rmixl_vec_establish(vec, ih, ipl, func, arg, mpsafe); 1269 1270 /* 1271 * establish IRT Entry 1272 */ 1273 rmixl_irt_establish(irt, vec, ist); 1274 1275 mutex_exit(rmixl_intr_lock); 1276 1277 return ih; 1278 } 1279 1280 void 1281 rmixl_vec_disestablish(void *cookie) 1282 { 1283 rmixl_intrhand_t * const ih = cookie; 1284 const size_t vec = ih->ih_vec; 1285 rmixl_intrvec_t * const iv = &rmixl_intrvec[vec]; 1286 1287 KASSERT(mutex_owned(rmixl_intr_lock)); 1288 KASSERT(vec < NINTRVECS); 1289 KASSERT(ih->ih_func != NULL); 1290 KASSERT(IPL_VM <= iv->iv_ipl && iv->iv_ipl <= IPL_HIGH); 1291 1292 LIST_REMOVE(ih, ih_link); 1293 1294 ih->ih_func = NULL; /* do this first */ 1295 1296 const uint64_t eimr_bit = __BIT(ih->ih_vec); 1297 for (int i = iv->iv_ipl; --i >= 0; ) { 1298 KASSERT((ipl_eimr_map[i] & eimr_bit) != 0); 1299 ipl_eimr_map[i] ^= eimr_bit; 1300 } 1301 1302 ih->ih_vec = 0; 1303 ih->ih_mpsafe = false; 1304 ih->ih_arg = NULL; 1305 1306 /* 1307 * If this vector isn't servicing any interrupts, then check to 1308 * see if this IPL has other vectors using it. If it does, then 1309 * return this vector to the freeq (lruq for IPL_NONE). This makes 1310 * there will always be at least one vector per IPL. 1311 */ 1312 if (vec > 8 && LIST_EMPTY(&iv->iv_hands)) { 1313 rmixl_intrvecq_t * const freeq = &rmixl_intrvec_lruq[IPL_NONE]; 1314 rmixl_intrvecq_t * const iplq = &rmixl_intrvec_lruq[iv->iv_ipl]; 1315 1316 if (TAILQ_NEXT(iv, iv_lruq_link) != NULL 1317 || TAILQ_FIRST(iplq) != iv) { 1318 TAILQ_REMOVE(iplq, iv, iv_lruq_link); 1319 iv->iv_ipl = IPL_NONE; 1320 TAILQ_INSERT_TAIL(freeq, iv, iv_lruq_link); 1321 } 1322 } 1323 } 1324 1325 void 1326 rmixl_intr_disestablish(void *cookie) 1327 { 1328 rmixl_intrhand_t * const ih = cookie; 1329 const size_t vec = ih->ih_vec; 1330 rmixl_intrvec_t * const iv = &rmixl_intrvec[vec]; 1331 1332 KASSERT(vec < NINTRVECS); 1333 1334 mutex_enter(rmixl_intr_lock); 1335 1336 /* 1337 * disable/invalidate the IRT Entry if needed 1338 */ 1339 if (ih != &iv->iv_intrhand) { 1340 size_t irt = ih - rmixl_irt_intrhands; 1341 KASSERT(irt < rmixl_nirts); 1342 rmixl_irt_disestablish(irt); 1343 } 1344 1345 /* 1346 * disasociate from vector and free the handle 1347 */ 1348 rmixl_vec_disestablish(cookie); 1349 1350 mutex_exit(rmixl_intr_lock); 1351 } 1352 1353 void 1354 evbmips_iointr(int ipl, vaddr_t pc, uint32_t pending) 1355 { 1356 struct rmixl_cpu_softc * const sc = (void *)curcpu()->ci_softc; 1357 const bool is_xlp_p = cpu_rmixlp(mips_options.mips_cpu); 1358 1359 DPRINTF(("%s: cpu%u: ipl %d, pc %#"PRIxVADDR", pending %#x\n", 1360 __func__, cpu_number(), ipl, pc, pending)); 1361 1362 /* 1363 * 'pending' arg is a summary that there is something to do 1364 * the real pending status is obtained from EIRR 1365 */ 1366 KASSERT(pending == MIPS_INT_MASK_1); 1367 1368 for (;;) { 1369 rmixl_intrhand_t *ih; 1370 uint64_t eirr; 1371 uint64_t eimr; 1372 uint64_t vecbit; 1373 int vec; 1374 1375 __asm volatile("dmfc0 %0, $9, 6;" : "=r"(eirr)); 1376 __asm volatile("dmfc0 %0, $9, 7;" : "=r"(eimr)); 1377 1378 #ifdef IOINTR_DEBUG 1379 printf("%s: cpu%u: eirr %#"PRIx64", eimr %#"PRIx64", mask %#"PRIx64"\n", 1380 __func__, cpu_number(), eirr, eimr, ipl_eimr_map[ipl-1]); 1381 #endif /* IOINTR_DEBUG */ 1382 1383 /* 1384 * reduce eirr to 1385 * - ints that are enabled at or below this ipl 1386 * - exclude count/compare clock and soft ints 1387 * they are handled elsewhere 1388 */ 1389 eirr &= ipl_eimr_map[ipl-1]; 1390 eirr &= ~ipl_eimr_map[ipl]; 1391 eirr &= ~((MIPS_INT_MASK_5 | MIPS_SOFT_INT_MASK) >> 8); 1392 if (eirr == 0) 1393 break; 1394 1395 vec = 63 - dclz(eirr); 1396 rmixl_intrvec_t * const iv = &rmixl_intrvec[vec]; 1397 vecbit = 1ULL << vec; 1398 KASSERT (iv->iv_ipl == ipl); 1399 LIST_FOREACH(ih, &iv->iv_hands, ih_link) { 1400 KASSERT ((vecbit & eimr) == 0); 1401 KASSERT ((vecbit & RMIXL_EIRR_PRESERVE_MASK) == 0); 1402 1403 /* 1404 * ack in EIRR, and in PIC if needed, 1405 * the irq we are about to handle 1406 */ 1407 rmixl_eirr_ack(eimr, vecbit, RMIXL_EIRR_PRESERVE_MASK); 1408 if (ih != &iv->iv_intrhand) { 1409 size_t irt = ih - rmixl_irt_intrhands; 1410 KASSERT(irt < rmixl_nirts); 1411 if (is_xlp_p) { 1412 RMIXLP_PICREG_WRITE(RMIXLP_PIC_INT_ACK, 1413 irt); 1414 } else { 1415 RMIXL_PICREG_WRITE(RMIXL_PIC_INTRACK, 1416 1 << irt); 1417 } 1418 sc->sc_irt_evcnts[irt].ev_count++; 1419 } 1420 1421 if (ih->ih_func != NULL) { 1422 #ifdef MULTIPROCESSOR 1423 if (ih->ih_mpsafe) { 1424 (void)(*ih->ih_func)(ih->ih_arg); 1425 } else { 1426 KASSERTMSG(ipl == IPL_VM, 1427 ("%s: %s: ipl (%d) != IPL_VM for KERNEL_LOCK", 1428 __func__, sc->sc_vec_evcnts[vec].ev_name, 1429 ipl)); 1430 KERNEL_LOCK(1, NULL); 1431 (void)(*ih->ih_func)(ih->ih_arg); 1432 KERNEL_UNLOCK_ONE(NULL); 1433 } 1434 #else 1435 (void)(*ih->ih_func)(ih->ih_arg); 1436 #endif /* MULTIPROCESSOR */ 1437 } 1438 KASSERT(ipl == iv->iv_ipl); 1439 KASSERTMSG(curcpu()->ci_cpl >= ipl, 1440 ("%s: after %s: cpl (%d) < ipl %d", 1441 __func__, sc->sc_vec_evcnts[vec].ev_name, 1442 ipl, curcpu()->ci_cpl)); 1443 sc->sc_vec_evcnts[vec].ev_count++; 1444 } 1445 } 1446 } 1447 1448 #ifdef MULTIPROCESSOR 1449 static int 1450 rmixl_send_ipi(struct cpu_info *ci, int tag) 1451 { 1452 const cpuid_t cpuid = ci->ci_cpuid; 1453 const uint64_t req = 1 << tag; 1454 const bool is_xlp_p = cpu_rmixlp(mips_options.mips_cpu); 1455 uint32_t r; 1456 1457 if (! CPUSET_HAS_P(cpus_running, cpu_index(ci))) 1458 return -1; 1459 1460 KASSERT(tag >= 0 && tag < NIPIS); 1461 1462 if (is_xlp_p) { 1463 r = RMXLP_PIC_IPI_CTRL_MAKE(0, __BIT(cpuid & 15), 1464 RMIXL_INTERVEC_IPI + tag); 1465 } else { 1466 const uint32_t core = (uint32_t)(cpuid >> 2); 1467 const uint32_t thread = (uint32_t)(cpuid & __BITS(1,0)); 1468 r = RMXLP_PIC_IPI_CTRL_MAKE(0, core, thread, 1469 RMIXL_INTERVEC_IPI + tag); 1470 } 1471 1472 mutex_enter(rmixl_ipi_lock); 1473 atomic_or_64(&ci->ci_request_ipis, req); 1474 __asm __volatile("sync"); 1475 if (is_xlp_p) { 1476 RMIXLP_PICREG_WRITE(RMIXLP_PIC_IPI_CTRL, r); 1477 } else { 1478 RMIXL_PICREG_WRITE(RMIXL_PIC_IPIBASE, r); 1479 } 1480 mutex_exit(rmixl_ipi_lock); 1481 1482 return 0; 1483 } 1484 1485 static int 1486 rmixl_ipi_intr(void *arg) 1487 { 1488 struct cpu_info * const ci = curcpu(); 1489 const uint64_t ipi_mask = 1 << (uintptr_t)arg; 1490 1491 KASSERT(ci->ci_cpl >= IPL_SCHED); 1492 KASSERT((uintptr_t)arg < NIPIS); 1493 1494 /* if the request is clear, it was previously processed */ 1495 if ((ci->ci_request_ipis & ipi_mask) == 0) 1496 return 0; 1497 1498 atomic_or_64(&ci->ci_active_ipis, ipi_mask); 1499 atomic_and_64(&ci->ci_request_ipis, ~ipi_mask); 1500 1501 ipi_process(ci, ipi_mask); 1502 1503 atomic_and_64(&ci->ci_active_ipis, ~ipi_mask); 1504 1505 return 1; 1506 } 1507 #endif /* MULTIPROCESSOR */ 1508 1509 #if defined(DIAGNOSTIC) || defined(IOINTR_DEBUG) || defined(DDB) 1510 int 1511 rmixl_intrvec_print_subr(size_t vec) 1512 { 1513 rmixl_intrvec_t * const iv = &rmixl_intrvec[vec]; 1514 rmixl_intrhand_t *ih; 1515 1516 printf("vec %zu: ipl %u\n", vec, iv->iv_ipl); 1517 1518 LIST_FOREACH(ih, &iv->iv_hands, ih_link) { 1519 if (ih == &iv->iv_intrhand) { 1520 printf(" [%s]: func %p, arg %p\n", 1521 rmixl_vecnames_common[vec], 1522 ih->ih_func, ih->ih_arg); 1523 } else { 1524 const size_t irt = ih - rmixl_irt_intrhands; 1525 printf(" irt %zu [%s]: func %p, arg %p\n", 1526 irt, rmixl_irtnames[irt], 1527 ih->ih_func, ih->ih_arg); 1528 } 1529 } 1530 return 0; 1531 } 1532 int 1533 rmixl_intrhand_print(void) 1534 { 1535 for (size_t vec = 0; vec < NINTRVECS; vec++) 1536 rmixl_intrvec_print_subr(vec); 1537 return 0; 1538 } 1539 1540 static inline void 1541 rmixl_irt_entry_print(size_t irt) 1542 { 1543 if (irt >= rmixl_nirts) 1544 return; 1545 if (cpu_rmixlp(mips_options.mips_cpu)) { 1546 uint64_t c = RMIXLP_PICREG_READ(RMIXLP_PIC_IRTENTRY(irt)); 1547 printf("irt[%zu]: %#"PRIx64"\n", irt, c); 1548 } else { 1549 uint32_t c0 = RMIXL_PICREG_READ(RMIXL_PIC_IRTENTRYC0(irt)); 1550 uint32_t c1 = RMIXL_PICREG_READ(RMIXL_PIC_IRTENTRYC1(irt)); 1551 printf("irt[%zu]: %#x, %#x\n", irt, c0, c1); 1552 } 1553 } 1554 1555 int 1556 rmixl_irt_print(void) 1557 { 1558 printf("%s:\n", __func__); 1559 for (size_t irt = 0; irt < rmixl_nirts ; irt++) 1560 rmixl_irt_entry_print(irt); 1561 return 0; 1562 } 1563 1564 void 1565 rmixl_ipl_eimr_map_print(void) 1566 { 1567 printf("IPL_NONE=%d, mask %#"PRIx64"\n", 1568 IPL_NONE, ipl_eimr_map[IPL_NONE]); 1569 printf("IPL_SOFTCLOCK=%d, mask %#"PRIx64"\n", 1570 IPL_SOFTCLOCK, ipl_eimr_map[IPL_SOFTCLOCK]); 1571 printf("IPL_SOFTNET=%d, mask %#"PRIx64"\n", 1572 IPL_SOFTNET, ipl_eimr_map[IPL_SOFTNET]); 1573 printf("IPL_VM=%d, mask %#"PRIx64"\n", 1574 IPL_VM, ipl_eimr_map[IPL_VM]); 1575 printf("IPL_SCHED=%d, mask %#"PRIx64"\n", 1576 IPL_SCHED, ipl_eimr_map[IPL_SCHED]); 1577 printf("IPL_DDB=%d, mask %#"PRIx64"\n", 1578 IPL_DDB, ipl_eimr_map[IPL_DDB]); 1579 printf("IPL_HIGH=%d, mask %#"PRIx64"\n", 1580 IPL_HIGH, ipl_eimr_map[IPL_HIGH]); 1581 } 1582 1583 #endif 1584
Indexes created Fri Oct 17 23:09:53 GMT 2025