rmixl_intr.c revision 1.1.2.34
1 /* $NetBSD: rmixl_intr.c,v 1.1.2.34 2012/01/04 16:17:53 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or 8 * without modification, are permitted provided that the following 9 * conditions are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above 13 * copyright notice, this list of conditions and the following 14 * disclaimer in the documentation and/or other materials provided 15 * with the distribution. 16 * 3. The names of the authors may not be used to endorse or promote 17 * products derived from this software without specific prior 18 * written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY 21 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 23 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, 25 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 27 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 29 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 30 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 31 * OF SUCH DAMAGE. 32 */ 33 /*- 34 * Copyright (c) 2001 The NetBSD Foundation, Inc. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to The NetBSD Foundation 38 * by Jason R. Thorpe. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 49 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 50 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 51 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 52 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 53 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 54 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 55 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 56 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 57 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 58 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 59 * POSSIBILITY OF SUCH DAMAGE. 60 */ 61 62 /* 63 * Platform-specific interrupt support for the RMI XLP, XLR, XLS 64 */ 65 66 #include <sys/cdefs.h> 67 __KERNEL_RCSID(0, "$NetBSD: rmixl_intr.c,v 1.1.2.34 2012/01/04 16:17:53 matt Exp $"); 68 69 #include "opt_ddb.h" 70 #include "opt_multiprocessor.h" 71 #define __INTR_PRIVATE 72 73 #include <sys/param.h> 74 #include <sys/queue.h> 75 #include <sys/malloc.h> 76 #include <sys/systm.h> 77 #include <sys/device.h> 78 #include <sys/kernel.h> 79 #include <sys/atomic.h> 80 #include <sys/mutex.h> 81 #include <sys/cpu.h> 82 83 #include <machine/bus.h> 84 #include <machine/intr.h> 85 86 #include <mips/cpu.h> 87 #include <mips/cpuset.h> 88 #include <mips/locore.h> 89 90 #include <mips/rmi/rmixlreg.h> 91 #include <mips/rmi/rmixlvar.h> 92 93 #include <mips/rmi/rmixl_cpuvar.h> 94 #include <mips/rmi/rmixl_intr.h> 95 96 #include <dev/pci/pcireg.h> 97 #include <dev/pci/pcivar.h> 98 99 //#define IOINTR_DEBUG 1 100 #ifdef IOINTR_DEBUG 101 int iointr_debug = IOINTR_DEBUG; 102 # define DPRINTF(x) do { if (iointr_debug) printf x ; } while(0) 103 #else 104 # define DPRINTF(x) 105 #endif 106 107 static int 108 rmixl_stray_intr(void *v) 109 { 110 return 0; 111 } 112 113 #define RMIXL_PICREG_READ(off) \ 114 RMIXL_IOREG_READ(RMIXL_IO_DEV_PIC + (off)) 115 #define RMIXL_PICREG_WRITE(off, val) \ 116 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PIC + (off), (val)) 117 118 /* XXX this will need to deal with node */ 119 #define RMIXLP_PICREG_READ(off) \ 120 rmixlp_read_8(RMIXLP_PIC_PCITAG, (off)) 121 #define RMIXLP_PICREG_WRITE(off, val) \ 122 rmixlp_write_8(RMIXLP_PIC_PCITAG, (off), (val)); 123 124 /* 125 * do not clear these when acking EIRR 126 * (otherwise they get lost) 127 */ 128 #define RMIXL_EIRR_PRESERVE_MASK \ 129 ((MIPS_INT_MASK_5|MIPS_SOFT_INT_MASK) >> 8) 130 131 /* 132 * IRT assignments depends on the RMI chip family 133 * (XLS1xx vs. XLS2xx vs. XLS3xx vs. XLS6xx) 134 * use the right display string table for the CPU that's running. 135 */ 136 137 #ifdef MIPS64_XLR 138 /* 139 * rmixl_irtnames_xlrxxx 140 * - use for XLRxxx 141 */ 142 static const char * const rmixl_irtnames_xlrxxx[RMIXLR_NIRTS] = { 143 "pic int 0 (watchdog)", /* 0 */ 144 "pic int 1 (timer0)", /* 1 */ 145 "pic int 2 (timer1)", /* 2 */ 146 "pic int 3 (timer2)", /* 3 */ 147 "pic int 4 (timer3)", /* 4 */ 148 "pic int 5 (timer4)", /* 5 */ 149 "pic int 6 (timer5)", /* 6 */ 150 "pic int 7 (timer6)", /* 7 */ 151 "pic int 8 (timer7)", /* 8 */ 152 "pic int 9 (uart0)", /* 9 */ 153 "pic int 10 (uart1)", /* 10 */ 154 "pic int 11 (i2c0)", /* 11 */ 155 "pic int 12 (i2c1)", /* 12 */ 156 "pic int 13 (pcmcia)", /* 13 */ 157 "pic int 14 (gpio)", /* 14 */ 158 "pic int 15 (hyper)", /* 15 */ 159 "pic int 16 (pcix)", /* 16 */ 160 "pic int 17 (gmac0)", /* 17 */ 161 "pic int 18 (gmac1)", /* 18 */ 162 "pic int 19 (gmac2)", /* 19 */ 163 "pic int 20 (gmac3)", /* 20 */ 164 "pic int 21 (xgs0)", /* 21 */ 165 "pic int 22 (xgs1)", /* 22 */ 166 "pic int 23 (?)", /* 23 */ 167 "pic int 24 (hyper_fatal)", /* 24 */ 168 "pic int 25 (bridge_aerr)", /* 25 */ 169 "pic int 26 (bridge_berr)", /* 26 */ 170 "pic int 27 (bridge_tb)", /* 27 */ 171 "pic int 28 (bridge_nmi)", /* 28 */ 172 "pic int 29 (bridge_sram_derr)",/* 29 */ 173 "pic int 30 (gpio_fatal)", /* 30 */ 174 "pic int 31 (reserved)", /* 31 */ 175 }; 176 #endif /* MIPS64_XLR */ 177 178 #ifdef MIPS64_XLS 179 /* 180 * rmixl_irtnames_xls2xx 181 * - use for XLS2xx 182 */ 183 static const char * const rmixl_irtnames_xls2xx[RMIXLS_NIRTS] = { 184 "pic int 0 (watchdog)", /* 0 */ 185 "pic int 1 (timer0)", /* 1 */ 186 "pic int 2 (timer1)", /* 2 */ 187 "pic int 3 (timer2)", /* 3 */ 188 "pic int 4 (timer3)", /* 4 */ 189 "pic int 5 (timer4)", /* 5 */ 190 "pic int 6 (timer5)", /* 6 */ 191 "pic int 7 (timer6)", /* 7 */ 192 "pic int 8 (timer7)", /* 8 */ 193 "pic int 9 (uart0)", /* 9 */ 194 "pic int 10 (uart1)", /* 10 */ 195 "pic int 11 (i2c0)", /* 11 */ 196 "pic int 12 (i2c1)", /* 12 */ 197 "pic int 13 (pcmcia)", /* 13 */ 198 "pic int 14 (gpio_a)", /* 14 */ 199 "pic int 15 (?)", /* 15 */ 200 "pic int 16 (bridge_tb)", /* 16 */ 201 "pic int 17 (gmac0)", /* 17 */ 202 "pic int 18 (gmac1)", /* 18 */ 203 "pic int 19 (gmac2)", /* 19 */ 204 "pic int 20 (gmac3)", /* 20 */ 205 "pic int 21 (?)", /* 21 */ 206 "pic int 22 (?)", /* 22 */ 207 "pic int 23 (pcie_link2)", /* 23 */ 208 "pic int 24 (pcie_link3)", /* 24 */ 209 "pic int 25 (bridge_err)", /* 25 */ 210 "pic int 26 (pcie_link0)", /* 26 */ 211 "pic int 27 (pcie_link1)", /* 27 */ 212 "pic int 28 (?)", /* 28 */ 213 "pic int 29 (pcie_err)", /* 29 */ 214 "pic int 30 (gpio_b)", /* 30 */ 215 "pic int 31 (usb)", /* 31 */ 216 }; 217 218 /* 219 * rmixl_irtnames_xls1xx 220 * - use for XLS1xx, XLS4xx-Lite 221 */ 222 static const char * const rmixl_irtnames_xls1xx[RMIXLS_NIRTS] = { 223 "pic int 0 (watchdog)", /* 0 */ 224 "pic int 1 (timer0)", /* 1 */ 225 "pic int 2 (timer1)", /* 2 */ 226 "pic int 3 (timer2)", /* 3 */ 227 "pic int 4 (timer3)", /* 4 */ 228 "pic int 5 (timer4)", /* 5 */ 229 "pic int 6 (timer5)", /* 6 */ 230 "pic int 7 (timer6)", /* 7 */ 231 "pic int 8 (timer7)", /* 8 */ 232 "pic int 9 (uart0)", /* 9 */ 233 "pic int 10 (uart1)", /* 10 */ 234 "pic int 11 (i2c0)", /* 11 */ 235 "pic int 12 (i2c1)", /* 12 */ 236 "pic int 13 (pcmcia)", /* 13 */ 237 "pic int 14 (gpio_a)", /* 14 */ 238 "pic int 15 (?)", /* 15 */ 239 "pic int 16 (bridge_tb)", /* 16 */ 240 "pic int 17 (gmac0)", /* 17 */ 241 "pic int 18 (gmac1)", /* 18 */ 242 "pic int 19 (gmac2)", /* 19 */ 243 "pic int 20 (gmac3)", /* 20 */ 244 "pic int 21 (?)", /* 21 */ 245 "pic int 22 (?)", /* 22 */ 246 "pic int 23 (?)", /* 23 */ 247 "pic int 24 (?)", /* 24 */ 248 "pic int 25 (bridge_err)", /* 25 */ 249 "pic int 26 (pcie_link0)", /* 26 */ 250 "pic int 27 (pcie_link1)", /* 27 */ 251 "pic int 28 (?)", /* 28 */ 252 "pic int 29 (pcie_err)", /* 29 */ 253 "pic int 30 (gpio_b)", /* 30 */ 254 "pic int 31 (usb)", /* 31 */ 255 }; 256 257 /* 258 * rmixl_irtnames_xls4xx: 259 * - use for XLS4xx, XLS6xx 260 */ 261 static const char * const rmixl_irtnames_xls4xx[RMIXLS_NIRTS] = { 262 "pic int 0 (watchdog)", /* 0 */ 263 "pic int 1 (timer0)", /* 1 */ 264 "pic int 2 (timer1)", /* 2 */ 265 "pic int 3 (timer2)", /* 3 */ 266 "pic int 4 (timer3)", /* 4 */ 267 "pic int 5 (timer4)", /* 5 */ 268 "pic int 6 (timer5)", /* 6 */ 269 "pic int 7 (timer6)", /* 7 */ 270 "pic int 8 (timer7)", /* 8 */ 271 "pic int 9 (uart0)", /* 9 */ 272 "pic int 10 (uart1)", /* 10 */ 273 "pic int 11 (i2c0)", /* 11 */ 274 "pic int 12 (i2c1)", /* 12 */ 275 "pic int 13 (pcmcia)", /* 13 */ 276 "pic int 14 (gpio_a)", /* 14 */ 277 "pic int 15 (?)", /* 15 */ 278 "pic int 16 (bridge_tb)", /* 16 */ 279 "pic int 17 (gmac0)", /* 17 */ 280 "pic int 18 (gmac1)", /* 18 */ 281 "pic int 19 (gmac2)", /* 19 */ 282 "pic int 20 (gmac3)", /* 20 */ 283 "pic int 21 (?)", /* 21 */ 284 "pic int 22 (?)", /* 22 */ 285 "pic int 23 (?)", /* 23 */ 286 "pic int 24 (?)", /* 24 */ 287 "pic int 25 (bridge_err)", /* 25 */ 288 "pic int 26 (pcie_link0)", /* 26 */ 289 "pic int 27 (pcie_link1)", /* 27 */ 290 "pic int 28 (pcie_link2)", /* 28 */ 291 "pic int 29 (pcie_link3)", /* 29 */ 292 "pic int 30 (gpio_b)", /* 30 */ 293 "pic int 31 (usb)", /* 31 */ 294 }; 295 #endif /* MIPS64_XLS */ 296 297 #ifdef MIPS64_XLP 298 /* 299 * rmixl_irtnames_xlp: 300 * - use for XLP 301 */ 302 static const char * const rmixl_irtnames_xlp8xx[RMIXLP_NIRTS] = { 303 [ 0] = "pic int 0 (watchdog0)", 304 [ 1] = "pic int 1 (watchdog1)", 305 [ 2] = "pic int 2 (watchdogNMI0)", 306 [ 3] = "pic int 3 (watchdogNMI1)", 307 [ 4] = "pic int 4 (timer0)", 308 [ 5] = "pic int 5 (timer1)", 309 [ 6] = "pic int 6 (timer2)", 310 [ 7] = "pic int 7 (timer3)", 311 [ 8] = "pic int 8 (timer4)", 312 [ 9] = "pic int 9 (timer5)", 313 [ 10] = "pic int 10 (timer6)", 314 [ 11] = "pic int 11 (timer7)", 315 [ 12] = "pic int 12 (fmn0)", 316 [ 13] = "pic int 13 (fmn1)", 317 [ 14] = "pic int 14 (fmn2)", 318 [ 15] = "pic int 15 (fmn3)", 319 [ 16] = "pic int 16 (fmn4)", 320 [ 17] = "pic int 17 (fmn5)", 321 [ 18] = "pic int 18 (fmn6)", 322 [ 19] = "pic int 19 (fmn7)", 323 [ 20] = "pic int 20 (fmn8)", 324 [ 21] = "pic int 21 (fmn9)", 325 [ 22] = "pic int 22 (fmn10)", 326 [ 23] = "pic int 23 (fmn11)", 327 [ 24] = "pic int 24 (fmn12)", 328 [ 25] = "pic int 25 (fmn13)", 329 [ 26] = "pic int 26 (fmn14)", 330 [ 27] = "pic int 27 (fmn15)", 331 [ 28] = "pic int 28 (fmn16)", 332 [ 29] = "pic int 29 (fmn17)", 333 [ 30] = "pic int 30 (fmn18)", 334 [ 31] = "pic int 31 (fmn19)", 335 [ 32] = "pic int 22 (fmn20)", 336 [ 33] = "pic int 23 (fmn21)", 337 [ 34] = "pic int 24 (fmn22)", 338 [ 35] = "pic int 25 (fmn23)", 339 [ 36] = "pic int 26 (fmn24)", 340 [ 37] = "pic int 27 (fmn25)", 341 [ 38] = "pic int 28 (fmn26)", 342 [ 39] = "pic int 29 (fmn27)", 343 [ 40] = "pic int 30 (fmn28)", 344 [ 41] = "pic int 31 (fmn29)", 345 [ 42] = "pic int 42 (fmn30)", 346 [ 43] = "pic int 43 (fmn31)", 347 [ 44] = "pic int 44 (fmnerr0)", 348 [ 45] = "pic int 45 (fmnerr1)", 349 [ 46] = "pic int 46 (pcie_msix0)", 350 [ 47] = "pic int 47 (pcie_msix1)", 351 [ 48] = "pic int 48 (pcie_msix2)", 352 [ 49] = "pic int 49 (pcie_msix3)", 353 [ 50] = "pic int 50 (pcie_msix4)", 354 [ 51] = "pic int 51 (pcie_msix5)", 355 [ 52] = "pic int 52 (pcie_msix6)", 356 [ 53] = "pic int 53 (pcie_msix7)", 357 [ 54] = "pic int 54 (pcie_msix8)", 358 [ 55] = "pic int 55 (pcie_msix9)", 359 [ 56] = "pic int 56 (pcie_msix10)", 360 [ 57] = "pic int 57 (pcie_msix11)", 361 [ 58] = "pic int 58 (pcie_msix12)", 362 [ 59] = "pic int 59 (pcie_msix13)", 363 [ 60] = "pic int 60 (pcie_msix14)", 364 [ 61] = "pic int 61 (pcie_msix15)", 365 [ 62] = "pic int 62 (pcie_msix16)", 366 [ 63] = "pic int 63 (pcie_msix17)", 367 [ 64] = "pic int 64 (pcie_msix18)", 368 [ 65] = "pic int 65 (pcie_msix19)", 369 [ 66] = "pic int 66 (pcie_msix20)", 370 [ 67] = "pic int 67 (pcie_msix21)", 371 [ 68] = "pic int 68 (pcie_msix22)", 372 [ 69] = "pic int 69 (pcie_msix23)", 373 [ 70] = "pic int 70 (pcie_msix24)", 374 [ 71] = "pic int 71 (pcie_msix25)", 375 [ 72] = "pic int 72 (pcie_msix26)", 376 [ 73] = "pic int 73 (pcie_msix27)", 377 [ 74] = "pic int 74 (pcie_msix28)", 378 [ 75] = "pic int 75 (pcie_msix29)", 379 [ 76] = "pic int 76 (pcie_msix30)", 380 [ 77] = "pic int 77 (pcie_msix31)", 381 [ 78] = "pic int 78 (pcie_link0)", 382 [ 79] = "pic int 79 (pcie_link1)", 383 [ 80] = "pic int 80 (pcie_link2)", 384 [ 81] = "pic int 81 (pcie_link3)", 385 [ 82] = "pic int 82 (nae0)", 386 [ 83] = "pic int 83 (nae1)", 387 [ 84] = "pic int 84 (nae2)", 388 [ 85] = "pic int 85 (nae3)", 389 [ 86] = "pic int 86 (nae4)", 390 [ 87] = "pic int 87 (nae5)", 391 [ 88] = "pic int 88 (nae6)", 392 [ 89] = "pic int 89 (nae7)", 393 [ 90] = "pic int 90 (nae8)", 394 [ 91] = "pic int 91 (nae9)", 395 [ 92] = "pic int 92 (nae10)", 396 [ 93] = "pic int 93 (nae11)", 397 [ 94] = "pic int 94 (nae12)", 398 [ 95] = "pic int 95 (nae13)", 399 [ 96] = "pic int 96 (nae14)", 400 [ 97] = "pic int 97 (nae15)", 401 [ 98] = "pic int 98 (nae16)", 402 [ 99] = "pic int 99 (nae17)", 403 [100] = "pic int 100 (nae18)", 404 [101] = "pic int 101 (?)", 405 [102] = "pic int 102 (naecom0)", 406 [103] = "pic int 103 (naecom1)", 407 [104] = "pic int 104 (?)", 408 [105] = "pic int 105 (?)", 409 [106] = "pic int 106 (?)", 410 [107] = "pic int 107 (?)", 411 [108] = "pic int 108 (?)", 412 [109] = "pic int 109 (?)", 413 [110] = "pic int 100 (?)", 414 [111] = "pic int 111 (?)", 415 [112] = "pic int 112 (?)", 416 [113] = "pic int 113 (?)", 417 [114] = "pic int 114 (poe)", 418 [115] = "pic int 115 (ehci0)", 419 [116] = "pic int 116 (ohci0)", 420 [117] = "pic int 117 (ohci1)", 421 [118] = "pic int 118 (ehci1)", 422 [119] = "pic int 119 (ohci2)", 423 [120] = "pic int 120 (ohci3)", 424 [121] = "pic int 121 (dma)", 425 [122] = "pic int 122 (sae)", 426 [123] = "pic int 123 (pke)", 427 [124] = "pic int 124 (cde0)", 428 [125] = "pic int 125 (cde1)", 429 [126] = "pic int 126 (cde2)", 430 [127] = "pic int 127 (cde3)", 431 [128] = "pic int 128 (?)", 432 [129] = "pic int 129 (ici0)", 433 [130] = "pic int 130 (ici1)", 434 [131] = "pic int 131 (ici2)", 435 [132] = "pic int 132 (kbp)", 436 [133] = "pic int 133 (uart0)", 437 [134] = "pic int 134 (uart1)", 438 [135] = "pic int 135 (i2c0)", 439 [136] = "pic int 136 (i2c1)", 440 [137] = "pic int 137 (sysmgt0)", 441 [138] = "pic int 138 (sysmgt1)", 442 [139] = "pic int 139 (jtag)", 443 [140] = "pic int 140 (pic)", 444 [141] = "pic int 141 (?)", 445 [142] = "pic int 142 (?)", 446 [143] = "pic int 143 (?)", 447 [144] = "pic int 144 (?)", 448 [145] = "pic int 145 (?)", 449 [146] = "pic int 146 (gpio0)", 450 [147] = "pic int 147 (gpio1)", 451 [148] = "pic int 148 (gpio2)", 452 [149] = "pic int 149 (gpio3)", 453 [150] = "pic int 150 (norflash)", 454 [151] = "pic int 151 (nandflash)", 455 [152] = "pic int 152 (spi)", 456 [153] = "pic int 153 (mmc/sd)", 457 [154] = "pic int 154 (mem-io-bridge)", 458 [155] = "pic int 155 (l3)", 459 [156] = "pic int 156 (gcu)", 460 [157] = "pic int 157 (dram3_0)", 461 [158] = "pic int 158 (dram3_1)", 462 [159] = "pic int 159 (tracebuf)", 463 }; 464 465 /* 466 * rmixl_irtnames_xlp: 467 * - use for XLP 468 */ 469 static const char * const rmixl_irtnames_xlp3xx[RMIXLP_NIRTS] = { 470 [ 0] = "pic int 0 (watchdog0)", 471 [ 1] = "pic int 1 (watchdog1)", 472 [ 2] = "pic int 2 (watchdogNMI0)", 473 [ 3] = "pic int 3 (watchdogNMI1)", 474 [ 4] = "pic int 4 (timer0)", 475 [ 5] = "pic int 5 (timer1)", 476 [ 6] = "pic int 6 (timer2)", 477 [ 7] = "pic int 7 (timer3)", 478 [ 8] = "pic int 8 (timer4)", 479 [ 9] = "pic int 9 (timer5)", 480 [ 10] = "pic int 10 (timer6)", 481 [ 11] = "pic int 11 (timer7)", 482 [ 12] = "pic int 12 (gpio0)", 483 [ 13] = "pic int 13 (gpio1)", 484 [ 14] = "pic int 14 (gpio2)", 485 [ 15] = "pic int 15 (gpio3)", 486 [ 16] = "pic int 16 (gpio4)", 487 [ 17] = "pic int 17 (gpio5)", 488 [ 18] = "pic int 18 (gpio6)", 489 [ 19] = "pic int 19 (gpio7)", 490 [ 20] = "pic int 20 (gpio8)", 491 [ 21] = "pic int 21 (gpio0)", 492 [ 22] = "pic int 22 (gpio10)", 493 [ 23] = "pic int 23 (gpio11)", 494 [ 24] = "pic int 24 (?)", 495 [ 25] = "pic int 25 (?)", 496 [ 26] = "pic int 26 (?)", 497 [ 27] = "pic int 27 (?)", 498 [ 28] = "pic int 28 (fmn0)", 499 [ 29] = "pic int 29 (fmn1)", 500 [ 30] = "pic int 30 (fmn2)", 501 [ 31] = "pic int 31 (fmn3)", 502 [ 32] = "pic int 22 (fmn4)", 503 [ 33] = "pic int 23 (fmn5)", 504 [ 34] = "pic int 24 (fmn6)", 505 [ 35] = "pic int 25 (fmn7)", 506 [ 36] = "pic int 26 (fmn8)", 507 [ 37] = "pic int 27 (fmn9)", 508 [ 38] = "pic int 28 (fmn10)", 509 [ 39] = "pic int 29 (fmn11)", 510 [ 40] = "pic int 30 (fmn12)", 511 [ 41] = "pic int 31 (fmn13)", 512 [ 42] = "pic int 42 (fmn14)", 513 [ 43] = "pic int 43 (fmn15)", 514 [ 44] = "pic int 44 (fmnerr0)", 515 [ 45] = "pic int 45 (fmnerr1)", 516 [ 46] = "pic int 46 (pcie_msix0)", 517 [ 47] = "pic int 47 (pcie_msix1)", 518 [ 48] = "pic int 48 (pcie_msix2)", 519 [ 49] = "pic int 49 (pcie_msix3)", 520 [ 50] = "pic int 50 (pcie_msix4)", 521 [ 51] = "pic int 51 (pcie_msix5)", 522 [ 52] = "pic int 52 (pcie_msix6)", 523 [ 53] = "pic int 53 (pcie_msix7)", 524 [ 54] = "pic int 54 (pcie_msix8)", 525 [ 55] = "pic int 55 (pcie_msix9)", 526 [ 56] = "pic int 56 (pcie_msix10)", 527 [ 57] = "pic int 57 (pcie_msix11)", 528 [ 58] = "pic int 58 (pcie_msix12)", 529 [ 59] = "pic int 59 (pcie_msix13)", 530 [ 60] = "pic int 60 (pcie_msix14)", 531 [ 61] = "pic int 61 (pcie_msix15)", 532 [ 62] = "pic int 62 (pcie_msix16)", 533 [ 63] = "pic int 63 (pcie_msix17)", 534 [ 64] = "pic int 64 (pcie_msix18)", 535 [ 65] = "pic int 65 (pcie_msix19)", 536 [ 66] = "pic int 66 (pcie_msix20)", 537 [ 67] = "pic int 67 (pcie_msix21)", 538 [ 68] = "pic int 68 (pcie_msix22)", 539 [ 69] = "pic int 69 (pcie_msix23)", 540 [ 70] = "pic int 70 (pcie_msix24)", 541 [ 71] = "pic int 71 (pcie_msix25)", 542 [ 72] = "pic int 72 (pcie_msix26)", 543 [ 73] = "pic int 73 (pcie_msix27)", 544 [ 74] = "pic int 74 (pcie_msix28)", 545 [ 75] = "pic int 75 (pcie_msix29)", 546 [ 76] = "pic int 76 (pcie_msix30)", 547 [ 77] = "pic int 77 (pcie_msix31)", 548 [ 78] = "pic int 78 (pcie_link0)", 549 [ 79] = "pic int 79 (pcie_link1)", 550 [ 80] = "pic int 80 (pcie_link2)", 551 [ 81] = "pic int 81 (pcie_link3)", 552 [ 82] = "pic int 82 (?)", 553 [ 83] = "pic int 83 (?)", 554 [ 84] = "pic int 84 (?)", 555 [ 85] = "pic int 85 (?)", 556 [ 86] = "pic int 86 (?)", 557 [ 87] = "pic int 87 (?)", 558 [ 88] = "pic int 88 (?)", 559 [ 89] = "pic int 89 (?)", 560 [ 90] = "pic int 90 (?)", 561 [ 91] = "pic int 91 (?)", 562 [ 92] = "pic int 92 (?)", 563 [ 93] = "pic int 93 (?)", 564 [ 94] = "pic int 94 (?)", 565 [ 95] = "pic int 95 (?)", 566 [ 96] = "pic int 96 (?)", 567 [ 97] = "pic int 97 (?)", 568 [ 98] = "pic int 98 (nae0)", 569 [ 99] = "pic int 99 (nae1)", 570 [100] = "pic int 100 (nae2)", 571 [101] = "pic int 101 (nae3)", 572 [102] = "pic int 102 (nae4)", 573 [103] = "pic int 103 (nae5)", 574 [104] = "pic int 104 (nae6)", 575 [105] = "pic int 105 (nae7)", 576 [106] = "pic int 106 (nae8)", 577 [107] = "pic int 107 (?)", 578 [108] = "pic int 108 (?)", 579 [109] = "pic int 109 (?)", 580 [110] = "pic int 100 (naecom0)", 581 [111] = "pic int 111 (naecom1)", 582 [112] = "pic int 112 (?)", 583 [113] = "pic int 113 (?)", 584 [114] = "pic int 114 (poe)", 585 [115] = "pic int 115 (ehci0)", 586 [116] = "pic int 116 (ohci0)", 587 [117] = "pic int 117 (ohci1)", 588 [118] = "pic int 118 (ehci1)", 589 [119] = "pic int 119 (ohci2)", 590 [120] = "pic int 120 (ohci3)", 591 [121] = "pic int 121 (dma)", 592 [122] = "pic int 122 (sae)", 593 [123] = "pic int 123 (pke)", 594 [124] = "pic int 124 (?)", 595 [125] = "pic int 125 (?)", 596 [126] = "pic int 126 (?)", 597 [127] = "pic int 127 (?)", 598 [128] = "pic int 128 (?)", 599 [129] = "pic int 129 (?)", 600 [130] = "pic int 130 (?)", 601 [131] = "pic int 131 (?)", 602 [132] = "pic int 132 (?)", 603 [133] = "pic int 133 (uart0)", 604 [134] = "pic int 134 (uart1)", 605 [135] = "pic int 135 (i2c0)", 606 [136] = "pic int 136 (i2c1)", 607 [137] = "pic int 137 (sysmgt0)", 608 [138] = "pic int 138 (sysmgt1)", 609 [139] = "pic int 139 (jtag)", 610 [140] = "pic int 140 (pic)", 611 [141] = "pic int 141 (rxe0)", 612 [142] = "pic int 142 (rxe1)", 613 [143] = "pic int 143 (sata)", 614 [144] = "pic int 144 (srio0)", 615 [145] = "pic int 145 (srio1)", 616 [146] = "pic int 146 (srio2)", 617 [147] = "pic int 147 (srio3)", 618 [148] = "pic int 148 (srio4)", 619 [149] = "pic int 149 (?)", 620 [150] = "pic int 150 (norflash)", 621 [151] = "pic int 151 (nandflash)", 622 [152] = "pic int 152 (spi)", 623 [153] = "pic int 153 (mmc/sd)", 624 [154] = "pic int 154 (mem-io-bridge)", 625 [155] = "pic int 155 (l3)", 626 [156] = "pic int 156 (?)", 627 [157] = "pic int 157 (dram3_0)", 628 [158] = "pic int 158 (dram3_1)", 629 [159] = "pic int 159 (tracebuf)", 630 }; 631 #endif /* MIPS64_XLP */ 632 633 /* 634 * rmixl_vecnames_common: 635 * - use for unknown cpu implementation 636 * - covers all vectors, not just IRT intrs 637 */ 638 static const char * const rmixl_vecnames_common[NINTRVECS] = { 639 "vec 0 (sw0)", /* 0 */ 640 "vec 1 (sw1)", /* 1 */ 641 "vec 2 (hw2)", /* 2 */ 642 "vec 3 (hw3)", /* 3 */ 643 "vec 4 (hw4)", /* 4 */ 644 "vec 5 (hw5)", /* 5 */ 645 "vec 6 (hw6)", /* 6 */ 646 "vec 7 (hw7)", /* 7 */ 647 "vec 8", /* 8 */ 648 "vec 9", /* 9 */ 649 "vec 10", /* 10 */ 650 "vec 11", /* 11 */ 651 "vec 12", /* 12 */ 652 "vec 13", /* 13 */ 653 "vec 14", /* 14 */ 654 "vec 15", /* 15 */ 655 "vec 16", /* 16 */ 656 "vec 17", /* 17 */ 657 "vec 18", /* 18 */ 658 "vec 19", /* 19 */ 659 "vec 20", /* 20 */ 660 "vec 21", /* 21 */ 661 "vec 22", /* 22 */ 662 "vec 23", /* 23 */ 663 "vec 24", /* 24 */ 664 "vec 25", /* 25 */ 665 "vec 26", /* 26 */ 666 "vec 27", /* 27 */ 667 "vec 28", /* 28 */ 668 "vec 29", /* 29 */ 669 "vec 30", /* 30 */ 670 "vec 31", /* 31 */ 671 "vec 32", /* 32 */ 672 "vec 33", /* 33 */ 673 "vec 34", /* 34 */ 674 "vec 35", /* 35 */ 675 "vec 36", /* 36 */ 676 "vec 37", /* 37 */ 677 "vec 38", /* 38 */ 678 "vec 39", /* 39 */ 679 "vec 40", /* 40 */ 680 "vec 41", /* 41 */ 681 "vec 42", /* 42 */ 682 "vec 43", /* 43 */ 683 "vec 44", /* 44 */ 684 "vec 45", /* 45 */ 685 "vec 46", /* 46 */ 686 "vec 47", /* 47 */ 687 "vec 48", /* 48 */ 688 "vec 49", /* 49 */ 689 "vec 50", /* 50 */ 690 "vec 51", /* 51 */ 691 "vec 52", /* 52 */ 692 "vec 53", /* 53 */ 693 "vec 54", /* 54 */ 694 "vec 55", /* 55 */ 695 "vec 56", /* 56 */ 696 "vec 57", /* 57 */ 697 "vec 58", /* 58 */ 698 "vec 59", /* 59 */ 699 "vec 60", /* 60 */ 700 "vec 61", /* 61 */ 701 "vec 62", /* 63 */ 702 "vec 63", /* 63 */ 703 }; 704 705 /* 706 * mask of CPUs attached 707 * once they are attached, this var is read-only so mp safe 708 */ 709 static __cpuset_t cpu_present_mask; 710 711 kmutex_t *rmixl_ipi_lock; /* covers RMIXL_PIC_IPIBASE */ 712 kmutex_t *rmixl_intr_lock; /* covers rest of PIC, and rmixl_intrhand[] */ 713 rmixl_intrvecq_t rmixl_intrvec_lruq[_IPL_N] = { 714 [IPL_NONE] = TAILQ_HEAD_INITIALIZER(rmixl_intrvec_lruq[IPL_NONE]), 715 [IPL_SOFTCLOCK] = TAILQ_HEAD_INITIALIZER(rmixl_intrvec_lruq[IPL_SOFTCLOCK]), 716 [IPL_SOFTNET] = TAILQ_HEAD_INITIALIZER(rmixl_intrvec_lruq[IPL_SOFTNET]), 717 [IPL_VM] = TAILQ_HEAD_INITIALIZER(rmixl_intrvec_lruq[IPL_VM]), 718 [IPL_SCHED] = TAILQ_HEAD_INITIALIZER(rmixl_intrvec_lruq[IPL_SCHED]), 719 [IPL_DDB] = TAILQ_HEAD_INITIALIZER(rmixl_intrvec_lruq[IPL_DDB]), 720 [IPL_HIGH] = TAILQ_HEAD_INITIALIZER(rmixl_intrvec_lruq[IPL_HIGH]), 721 }; 722 723 rmixl_intrvec_t rmixl_intrvec[NINTRVECS] = { 724 [0 ... NINTRVECS-1] = { 725 .iv_intrhand = { 726 .ih_func = rmixl_stray_intr, 727 }, 728 }, 729 }; 730 #define RMIXL_NIRTS MAX(MAX(RMIXLR_NIRTS,RMIXLS_NIRTS), RMIXLP_NIRTS) 731 rmixl_intrhand_t rmixl_irt_intrhands[RMIXL_NIRTS] = { 732 [0 ... RMIXL_NIRTS-1] = { 733 .ih_func = rmixl_stray_intr, 734 }, 735 }; 736 static u_int rmixl_nirts; 737 const char * const *rmixl_irtnames; 738 739 #ifdef DIAGNOSTIC 740 static int rmixl_pic_init_done; 741 #endif 742 743 744 static uint32_t rmixl_irt_thread_mask(__cpuset_t); 745 static void rmixl_irt_init(size_t); 746 static void rmixl_irt_disestablish(size_t); 747 static void rmixl_irt_establish(size_t, size_t, int); 748 749 #ifdef MULTIPROCESSOR 750 static int rmixl_send_ipi(struct cpu_info *, int); 751 static int rmixl_ipi_intr(void *); 752 #endif 753 754 #if defined(DIAGNOSTIC) || defined(IOINTR_DEBUG) || defined(DDB) 755 int rmixl_intrvec_print_subr(size_t); 756 int rmixl_intrhand_print(void); 757 int rmixl_irt_print(void); 758 void rmixl_ipl_eimr_map_print(void); 759 #endif 760 761 762 static inline u_int 763 dclz(uint64_t val) 764 { 765 u_int nlz; 766 767 __asm volatile("dclz %0, %1" : "=r"(nlz) : "r"(val)); 768 769 return nlz; 770 } 771 772 void 773 evbmips_intr_init(void) 774 { 775 const bool is_xlp_p = cpu_rmixlp(mips_options.mips_cpu); 776 const bool is_xlr_p = cpu_rmixlr(mips_options.mips_cpu); 777 const bool is_xls_p = cpu_rmixls(mips_options.mips_cpu); 778 779 KASSERT(is_xlp_p || is_xlr_p || is_xls_p); 780 781 /* 782 * The number of IRT entries is different for XLP .vs. XLR/XLS. 783 */ 784 if (is_xlp_p) { 785 #ifdef MIPS64_XLP 786 if (RMIXLP_3XX_P) { 787 rmixl_irtnames = rmixl_irtnames_xlp3xx; 788 rmixl_nirts = __arraycount(rmixl_irtnames_xlp3xx); 789 } else { 790 rmixl_irtnames = rmixl_irtnames_xlp8xx; 791 rmixl_nirts = __arraycount(rmixl_irtnames_xlp8xx); 792 } 793 #endif 794 } else if (is_xlr_p) { 795 #ifdef MIPS64_XLR 796 rmixl_irtnames = rmixl_irtnames_xlrxxx; 797 rmixl_nirts = __arraycount(rmixl_irtnames_xlrxxx); 798 #endif 799 } else if (is_xls_p) { 800 #ifdef MIPS64_XLS 801 switch (MIPS_PRID_IMPL(mips_options.mips_cpu_id)) { 802 case MIPS_XLS104: 803 case MIPS_XLS108: 804 case MIPS_XLS404LITE: 805 case MIPS_XLS408LITE: 806 rmixl_irtnames = rmixl_irtnames_xls1xx; 807 rmixl_nirts = __arraycount(rmixl_irtnames_xls1xx); 808 break; 809 case MIPS_XLS204: 810 case MIPS_XLS208: 811 rmixl_irtnames = rmixl_irtnames_xls2xx; 812 rmixl_nirts = __arraycount(rmixl_irtnames_xls2xx); 813 break; 814 case MIPS_XLS404: 815 case MIPS_XLS408: 816 case MIPS_XLS416: 817 case MIPS_XLS608: 818 case MIPS_XLS616: 819 rmixl_irtnames = rmixl_irtnames_xls4xx; 820 rmixl_nirts = __arraycount(rmixl_irtnames_xls4xx); 821 break; 822 default: 823 rmixl_irtnames = rmixl_vecnames_common; 824 rmixl_nirts = __arraycount(rmixl_vecnames_common); 825 break; 826 } 827 #endif /* MIPS64_XLS */ 828 } 829 830 #ifdef DIAGNOSTIC 831 if (rmixl_pic_init_done != 0) 832 panic("%s: rmixl_pic_init_done %d", 833 __func__, rmixl_pic_init_done); 834 #endif 835 836 rmixl_ipi_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_HIGH); 837 rmixl_intr_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_HIGH); 838 839 mutex_enter(rmixl_intr_lock); 840 841 /* 842 * Insert all non-IPI non-normal MIPS vectors on lru queue. 843 */ 844 for (size_t i = RMIXL_INTRVEC_IPI; i < NINTRVECS; i++) { 845 TAILQ_INSERT_TAIL(&rmixl_intrvec_lruq[IPL_NONE], 846 &rmixl_intrvec[i], iv_lruq_link); 847 } 848 849 /* 850 * initialize (zero) all IRT Entries in the PIC 851 */ 852 for (size_t i = 0; i < rmixl_nirts; i++) { 853 rmixl_irt_init(i); 854 } 855 856 /* 857 * disable watchdog NMI, timers 858 */ 859 if (is_xlp_p) { 860 /* 861 * Reset the interrupt thread enables to disable all CPUs. 862 */ 863 for (size_t i = 0; i < 8; i++) { 864 RMIXLP_PICREG_WRITE(RMIXLP_PIC_INT_THREAD_ENABLE01(i), 0); 865 RMIXLP_PICREG_WRITE(RMIXLP_PIC_INT_THREAD_ENABLE23(i), 0); 866 } 867 868 /* 869 * Enable interrupts for node 0 core 0 thread 0. 870 */ 871 RMIXLP_PICREG_WRITE(RMIXLP_PIC_INT_THREAD_ENABLE01(0), 1); 872 873 /* 874 * Disable watchdogs and system timers. 875 */ 876 uint64_t r = RMIXLP_PICREG_READ(RMIXLP_PIC_CTRL); 877 r &= ~(RMIXLP_PIC_CTRL_WTE|RMIXLP_PIC_CTRL_STE); 878 RMIXLP_PICREG_WRITE(RMIXLP_PIC_CTRL, r); 879 } else { 880 /* 881 * XXX 882 * WATCHDOG_ENB is preserved because clearing it causes 883 * hang on the XLS616 (but not on the XLS408) 884 */ 885 uint32_t r = RMIXL_PICREG_READ(RMIXL_PIC_CONTROL); 886 r &= RMIXL_PIC_CONTROL_RESV|RMIXL_PIC_CONTROL_WATCHDOG_ENB; 887 RMIXL_PICREG_WRITE(RMIXL_PIC_CONTROL, r); 888 } 889 890 #ifdef DIAGNOSTIC 891 rmixl_pic_init_done = 1; 892 #endif 893 mutex_exit(rmixl_intr_lock); 894 } 895 896 /* 897 * establish vector for mips3 count/compare clock interrupt 898 * this ensures we enable in EIRR, 899 * even though cpu_intr() handles the interrupt 900 * note the 'mpsafe' arg here is a placeholder only 901 */ 902 void 903 rmixl_intr_init_clk(void) 904 { 905 const size_t vec = ffs(MIPS_INT_MASK_5 >> MIPS_INT_MASK_SHIFT) - 1; 906 907 mutex_enter(rmixl_intr_lock); 908 909 void *ih = rmixl_vec_establish(vec, NULL, IPL_SCHED, NULL, NULL, false); 910 if (ih == NULL) 911 panic("%s: establish vec %zu failed", __func__, vec); 912 913 mutex_exit(rmixl_intr_lock); 914 } 915 916 #ifdef MULTIPROCESSOR 917 /* 918 * establish IPI interrupt and send function 919 */ 920 void 921 rmixl_intr_init_ipi(void) 922 { 923 mutex_enter(rmixl_intr_lock); 924 925 for (size_t ipi = 0; ipi < NIPIS; ipi++) { 926 const size_t vec = RMIXL_INTRVEC_IPI + ipi; 927 void * const ih = rmixl_vec_establish(vec, NULL, IPL_SCHED, 928 rmixl_ipi_intr, (void *)(uintptr_t)ipi, true); 929 if (ih == NULL) 930 panic("%s: establish ipi %zu at vec %zu failed", 931 __func__, ipi, vec); 932 } 933 934 mips_locoresw.lsw_send_ipi = rmixl_send_ipi; 935 936 mutex_exit(rmixl_intr_lock); 937 } 938 #endif /* MULTIPROCESSOR */ 939 940 /* 941 * initialize per-cpu interrupt stuff in softc 942 * accumulate per-cpu bits in 'cpu_present_mask' 943 */ 944 void 945 rmixl_intr_init_cpu(struct cpu_info *ci) 946 { 947 struct rmixl_cpu_softc * const sc = (void *)ci->ci_softc; 948 const char * xname = device_xname(sc->sc_dev); 949 950 KASSERT(sc != NULL); 951 KASSERT(NINTRVECS <= __arraycount(sc->sc_vec_evcnts)); 952 KASSERT(rmixl_nirts <= __arraycount(sc->sc_irt_evcnts)); 953 954 for (size_t vec = 0; vec < NINTRVECS; vec++) { 955 evcnt_attach_dynamic(&sc->sc_vec_evcnts[vec], 956 EVCNT_TYPE_INTR, NULL, xname, rmixl_intr_string(vec)); 957 } 958 959 for (size_t irt = 0; irt < rmixl_nirts; irt++) { 960 evcnt_attach_dynamic(&sc->sc_irt_evcnts[irt], 961 EVCNT_TYPE_INTR, NULL, xname, rmixl_irtnames[irt]); 962 } 963 964 KASSERT(cpu_index(ci) < (sizeof(cpu_present_mask) * 8)); 965 atomic_or_32((volatile uint32_t *)&cpu_present_mask, 1 << cpu_index(ci)); 966 } 967 968 const char * 969 rmixl_irt_string(size_t irt) 970 { 971 KASSERT(irt < rmixl_nirts); 972 973 return rmixl_irtnames[irt]; 974 } 975 976 /* 977 * rmixl_intr_string - return pointer to display name of a PIC-based interrupt 978 */ 979 const char * 980 rmixl_intr_string(size_t vec) 981 { 982 983 if (vec >= NINTRVECS) 984 panic("%s: vec index %zu out of range, max %d", 985 __func__, vec, NINTRVECS - 1); 986 987 return rmixl_vecnames_common[vec]; 988 } 989 990 size_t 991 rmixl_intr_get_vec(int ipl) 992 { 993 KASSERT(mutex_owned(rmixl_intr_lock)); 994 KASSERT(IPL_VM <= ipl && ipl <= IPL_HIGH); 995 996 /* 997 * In reality higer ipls should have higher vec numbers, 998 * but for now don't worry about it. 999 */ 1000 struct rmixl_intrvecq * const freeq = &rmixl_intrvec_lruq[IPL_NONE]; 1001 struct rmixl_intrvecq * const iplq = &rmixl_intrvec_lruq[ipl]; 1002 rmixl_intrvec_t *iv; 1003 1004 /* 1005 * If there's a free vector, grab it otherwise choose the least 1006 * recently assigned vector sharing this IPL. 1007 */ 1008 if ((iv = TAILQ_FIRST(freeq)) == NULL) { 1009 iv = TAILQ_FIRST(iplq); 1010 KASSERT(iv != NULL); 1011 } 1012 1013 return iv - rmixl_intrvec; 1014 } 1015 1016 /* 1017 * rmixl_irt_thread_mask 1018 * 1019 * given a bitmask of cpus, return a, IRT thread mask 1020 */ 1021 static uint32_t 1022 rmixl_irt_thread_mask(__cpuset_t cpumask) 1023 { 1024 uint32_t irtc0; 1025 1026 #if defined(MULTIPROCESSOR) 1027 #ifndef NOTYET 1028 if (cpumask == -1) 1029 return 1; /* XXX TMP FIXME */ 1030 #endif 1031 1032 /* 1033 * discount cpus not present 1034 */ 1035 cpumask &= cpu_present_mask; 1036 1037 switch (MIPS_PRID_IMPL(mips_options.mips_cpu_id)) { 1038 case MIPS_XLS104: 1039 case MIPS_XLS204: 1040 case MIPS_XLS404: 1041 case MIPS_XLS404LITE: 1042 irtc0 = ((cpumask >> 2) << 4) | (cpumask & __BITS(1,0)); 1043 irtc0 &= (__BITS(5,4) | __BITS(1,0)); 1044 break; 1045 case MIPS_XLS108: 1046 case MIPS_XLS208: 1047 case MIPS_XLS408: 1048 case MIPS_XLS408LITE: 1049 case MIPS_XLS608: 1050 irtc0 = cpumask & __BITS(7,0); 1051 break; 1052 case MIPS_XLS416: 1053 case MIPS_XLS616: 1054 irtc0 = cpumask & __BITS(15,0); 1055 break; 1056 default: 1057 panic("%s: unknown cpu ID %#x\n", __func__, 1058 mips_options.mips_cpu_id); 1059 } 1060 #else 1061 irtc0 = 1; 1062 #endif /* MULTIPROCESSOR */ 1063 1064 return irtc0; 1065 } 1066 1067 /* 1068 * rmixl_irt_init 1069 * - initialize IRT Entry for given index 1070 * - unmask Thread#0 in low word (assume we only have 1 thread) 1071 */ 1072 static void 1073 rmixl_irt_init(size_t irt) 1074 { 1075 KASSERT(irt < rmixl_nirts); 1076 if (cpu_rmixlp(mips_options.mips_cpu)) { 1077 RMIXLP_PICREG_WRITE(RMIXLP_PIC_IRTENTRY(irt), 0); 1078 } else { 1079 RMIXL_PICREG_WRITE(RMIXL_PIC_IRTENTRYC1(irt), 0); /* high word */ 1080 RMIXL_PICREG_WRITE(RMIXL_PIC_IRTENTRYC0(irt), 0); /* low word */ 1081 } 1082 } 1083 1084 /* 1085 * rmixl_irt_disestablish 1086 * - invalidate IRT Entry for given index 1087 */ 1088 static void 1089 rmixl_irt_disestablish(size_t irt) 1090 { 1091 KASSERT(mutex_owned(rmixl_intr_lock)); 1092 DPRINTF(("%s: irt %zu, irtc1 %#x\n", __func__, irt, 0)); 1093 rmixl_irt_init(irt); 1094 } 1095 1096 /* 1097 * rmixl_irt_establish 1098 * - construct an IRT Entry for irt and write to PIC 1099 */ 1100 static void 1101 rmixl_irt_establish(size_t irt, size_t vec, int ist) 1102 { 1103 const bool is_xlp_p = cpu_rmixlp(mips_options.mips_cpu); 1104 1105 KASSERT(mutex_owned(rmixl_intr_lock)); 1106 1107 if (irt >= rmixl_nirts) 1108 panic("%s: bad irt %zu\n", __func__, irt); 1109 1110 /* 1111 * All XLP interrupt are level (high). 1112 */ 1113 if (ist != IST_LEVEL && ist != IST_LEVEL_HIGH 1114 && (is_xlp_p 1115 || (ist != IST_EDGE 1116 && ist != IST_EDGE_FALLING 1117 && ist != IST_EDGE_RISING))) { 1118 panic("%s: bad ist %d\n", __func__, ist); 1119 } 1120 1121 /* 1122 * XXX IRT entries are not shared 1123 */ 1124 if (is_xlp_p) { 1125 KASSERT(RMIXLP_PICREG_READ(RMIXLP_PIC_IRTENTRY(irt)) == 0); 1126 uint64_t irtc0 = RMIXLP_PIC_IRTENTRY_EN 1127 | RMIXLP_PIC_IRTENTRY_LOCAL 1128 | RMIXLP_PIC_IRTENTRY_DT_ITE 1129 | RMIXLP_PIC_IRTENTRY_ITE(0) 1130 | __SHIFTIN(vec, RMIXLP_PIC_IRTENTRY_INTVEC) 1131 1132 /* 1133 * write IRT Entry to PIC 1134 */ 1135 DPRINTF(("%s: vec %zu (%#x), irt %zu (%s), irtc0 %#"PRIx64"\n", 1136 __func__, vec, vec, irt, rmixl_irtnames[irt], irtc0)); 1137 1138 RMIXLP_PICREG_WRITE(RMIXLP_PIC_IRTENTRY(irt), irtc0); 1139 } else { 1140 KASSERT(RMIXL_PICREG_READ(RMIXL_PIC_IRTENTRYC0(irt)) == 0); 1141 KASSERT(RMIXL_PICREG_READ(RMIXL_PIC_IRTENTRYC1(irt)) == 0); 1142 1143 __cpuset_t cpumask = 1; /* XXX */ 1144 uint32_t irtc0 = rmixl_irt_thread_mask(cpumask); 1145 1146 uint32_t irtc1 = RMIXL_PIC_IRTENTRYC1_VALID; 1147 irtc1 |= RMIXL_PIC_IRTENTRYC1_GL; /* local */ 1148 KASSERT((irtc1 & RMIXL_PIC_IRTENTRYC1_NMI) == 0); 1149 1150 if (ist == IST_LEVEL 1151 || ist == IST_LEVEL_LOW 1152 || ist == IST_LEVEL_HIGH) 1153 irtc1 |= RMIXL_PIC_IRTENTRYC1_TRG; 1154 KASSERT((irtc1 & RMIXL_PIC_IRTENTRYC1_NMI) == 0); 1155 1156 if (ist == IST_LEVEL_LOW || ist == IST_EDGE_FALLING) 1157 irtc1 |= RMIXL_PIC_IRTENTRYC1_P; 1158 KASSERT((irtc1 & RMIXL_PIC_IRTENTRYC1_NMI) == 0); 1159 1160 irtc1 |= vec; /* vector in EIRR */ 1161 KASSERT((irtc1 & RMIXL_PIC_IRTENTRYC1_NMI) == 0); 1162 1163 /* 1164 * write IRT Entry to PIC 1165 */ 1166 DPRINTF(("%s: vec %zu (%#x), irt %zu, irtc0 %#x, irtc1 %#x\n", 1167 __func__, vec, vec, irt, irtc0, irtc1)); 1168 RMIXL_PICREG_WRITE(RMIXL_PIC_IRTENTRYC0(irt), irtc0); /* low word */ 1169 RMIXL_PICREG_WRITE(RMIXL_PIC_IRTENTRYC1(irt), irtc1); /* high word */ 1170 } 1171 } 1172 1173 void * 1174 rmixl_vec_establish(size_t vec, rmixl_intrhand_t *ih, int ipl, 1175 int (*func)(void *), void *arg, bool mpsafe) 1176 { 1177 1178 KASSERT(mutex_owned(rmixl_intr_lock)); 1179 1180 DPRINTF(("%s: vec %zu ih %p ipl %d func %p arg %p mpsafe %d\n", 1181 __func__, vec, ih, ipl, func, arg, mpsafe)); 1182 1183 #ifdef DIAGNOSTIC 1184 if (rmixl_pic_init_done == 0) 1185 panic("%s: called before evbmips_intr_init", __func__); 1186 #endif 1187 1188 /* 1189 * check args 1190 */ 1191 if (vec >= NINTRVECS) 1192 panic("%s: vec %zu out of range, max %d", 1193 __func__, vec, NINTRVECS - 1); 1194 if (ipl < IPL_VM || ipl > IPL_HIGH) 1195 panic("%s: ipl %d out of range, min %d, max %d", 1196 __func__, ipl, IPL_VM, IPL_HIGH); 1197 1198 const int s = splhigh(); 1199 1200 rmixl_intrvec_t * const iv = &rmixl_intrvec[vec]; 1201 if (ih == NULL) { 1202 ih = &iv->iv_intrhand; 1203 } 1204 1205 if (vec >= 8) { 1206 TAILQ_REMOVE(&rmixl_intrvec_lruq[iv->iv_ipl], iv, iv_lruq_link); 1207 } 1208 1209 if (LIST_EMPTY(&iv->iv_hands)) { 1210 KASSERT(iv->iv_ipl == IPL_NONE); 1211 iv->iv_ipl = ipl; 1212 } else { 1213 KASSERT(iv->iv_ipl == ipl); 1214 } 1215 1216 if (vec >= 8) { 1217 TAILQ_INSERT_TAIL(&rmixl_intrvec_lruq[iv->iv_ipl], 1218 iv, iv_lruq_link); 1219 } 1220 1221 if (ih->ih_func != rmixl_stray_intr) { 1222 #ifdef DIAGNOSTIC 1223 printf("%s: intrhand[%zu] busy\n", __func__, vec); 1224 #endif 1225 splx(s); 1226 return NULL; 1227 } 1228 1229 ih->ih_arg = arg; 1230 ih->ih_mpsafe = mpsafe; 1231 ih->ih_vec = vec; 1232 1233 LIST_INSERT_HEAD(&iv->iv_hands, ih, ih_link); 1234 1235 const uint64_t eimr_bit = (uint64_t)1 << vec; 1236 for (int i = ipl; --i >= 0; ) { 1237 KASSERT((ipl_eimr_map[i] & eimr_bit) == 0); 1238 ipl_eimr_map[i] |= eimr_bit; 1239 } 1240 1241 ih->ih_func = func; /* do this last */ 1242 1243 splx(s); 1244 1245 return ih; 1246 } 1247 1248 /* 1249 * rmixl_intr_establish 1250 * - used to establish an IRT-based interrupt only 1251 */ 1252 void * 1253 rmixl_intr_establish(size_t irt, int ipl, int ist, 1254 int (*func)(void *), void *arg, bool mpsafe) 1255 { 1256 #ifdef DIAGNOSTIC 1257 if (rmixl_pic_init_done == 0) 1258 panic("%s: called before rmixl_pic_init_done", __func__); 1259 #endif 1260 1261 /* 1262 * check args 1263 */ 1264 if (irt >= rmixl_nirts) 1265 panic("%s: irt %zu out of range, max %d", 1266 __func__, irt, rmixl_nirts - 1); 1267 if (ipl < IPL_VM || ipl > IPL_HIGH) 1268 panic("%s: ipl %d out of range, min %d, max %d", 1269 __func__, ipl, IPL_VM, IPL_HIGH); 1270 1271 mutex_enter(rmixl_intr_lock); 1272 1273 rmixl_intrhand_t *ih = &rmixl_irt_intrhands[irt]; 1274 1275 KASSERT(ih->ih_func == rmixl_stray_intr); 1276 1277 const size_t vec = rmixl_intr_get_vec(ipl); 1278 1279 DPRINTF(("%s: irt %zu, ih %p vec %zu, ipl %d\n", 1280 __func__, irt, ih, vec, ipl)); 1281 1282 /* 1283 * establish vector 1284 */ 1285 ih = rmixl_vec_establish(vec, ih, ipl, func, arg, mpsafe); 1286 1287 /* 1288 * establish IRT Entry 1289 */ 1290 rmixl_irt_establish(irt, vec, ist); 1291 1292 mutex_exit(rmixl_intr_lock); 1293 1294 return ih; 1295 } 1296 1297 void 1298 rmixl_vec_disestablish(void *cookie) 1299 { 1300 rmixl_intrhand_t * const ih = cookie; 1301 const size_t vec = ih->ih_vec; 1302 rmixl_intrvec_t * const iv = &rmixl_intrvec[vec]; 1303 1304 KASSERT(mutex_owned(rmixl_intr_lock)); 1305 KASSERT(vec < NINTRVECS); 1306 KASSERT(ih->ih_func != rmixl_stray_intr); 1307 KASSERT(IPL_VM <= iv->iv_ipl && iv->iv_ipl <= IPL_HIGH); 1308 1309 LIST_REMOVE(ih, ih_link); 1310 1311 ih->ih_func = rmixl_stray_intr; /* do this first */ 1312 1313 const uint64_t eimr_bit = __BIT(ih->ih_vec); 1314 for (int i = iv->iv_ipl; --i >= 0; ) { 1315 KASSERT((ipl_eimr_map[i] & eimr_bit) != 0); 1316 ipl_eimr_map[i] ^= eimr_bit; 1317 } 1318 1319 ih->ih_vec = 0; 1320 ih->ih_mpsafe = false; 1321 ih->ih_arg = NULL; 1322 1323 /* 1324 * If this vector isn't servicing any interrupts, then check to 1325 * see if this IPL has other vectors using it. If it does, then 1326 * return this vector to the freeq (lruq for IPL_NONE). This makes 1327 * there will always be at least one vector per IPL. 1328 */ 1329 if (vec > 8 && LIST_EMPTY(&iv->iv_hands)) { 1330 rmixl_intrvecq_t * const freeq = &rmixl_intrvec_lruq[IPL_NONE]; 1331 rmixl_intrvecq_t * const iplq = &rmixl_intrvec_lruq[iv->iv_ipl]; 1332 1333 if (TAILQ_NEXT(iv, iv_lruq_link) != NULL 1334 || TAILQ_FIRST(iplq) != iv) { 1335 TAILQ_REMOVE(iplq, iv, iv_lruq_link); 1336 iv->iv_ipl = IPL_NONE; 1337 TAILQ_INSERT_TAIL(freeq, iv, iv_lruq_link); 1338 } 1339 } 1340 } 1341 1342 void 1343 rmixl_intr_disestablish(void *cookie) 1344 { 1345 rmixl_intrhand_t * const ih = cookie; 1346 const size_t vec = ih->ih_vec; 1347 rmixl_intrvec_t * const iv = &rmixl_intrvec[vec]; 1348 1349 KASSERT(vec < NINTRVECS); 1350 1351 mutex_enter(rmixl_intr_lock); 1352 1353 /* 1354 * disable/invalidate the IRT Entry if needed 1355 */ 1356 if (ih != &iv->iv_intrhand) { 1357 size_t irt = ih - rmixl_irt_intrhands; 1358 KASSERT(irt < rmixl_nirts); 1359 rmixl_irt_disestablish(irt); 1360 } 1361 1362 /* 1363 * disasociate from vector and free the handle 1364 */ 1365 rmixl_vec_disestablish(cookie); 1366 1367 mutex_exit(rmixl_intr_lock); 1368 } 1369 1370 void 1371 evbmips_iointr(int ipl, vaddr_t pc, uint32_t pending) 1372 { 1373 struct rmixl_cpu_softc * const sc = (void *)curcpu()->ci_softc; 1374 const bool is_xlp_p = cpu_rmixlp(mips_options.mips_cpu); 1375 1376 DPRINTF(("%s: cpu%u: ipl %d, pc %#"PRIxVADDR", pending %#x\n", 1377 __func__, cpu_number(), ipl, pc, pending)); 1378 1379 /* 1380 * 'pending' arg is a summary that there is something to do 1381 * the real pending status is obtained from EIRR 1382 */ 1383 KASSERT(pending == MIPS_INT_MASK_1); 1384 1385 for (;;) { 1386 rmixl_intrhand_t *ih; 1387 uint64_t eirr; 1388 uint64_t eimr; 1389 uint64_t vecbit; 1390 int vec; 1391 1392 __asm volatile("dmfc0 %0, $9, 6;" : "=r"(eirr)); 1393 __asm volatile("dmfc0 %0, $9, 7;" : "=r"(eimr)); 1394 1395 #ifdef IOINTR_DEBUG 1396 printf("%s: cpu%u: eirr %#"PRIx64", eimr %#"PRIx64", mask %#"PRIx64"\n", 1397 __func__, cpu_number(), eirr, eimr, ipl_eimr_map[ipl-1]); 1398 #endif /* IOINTR_DEBUG */ 1399 1400 /* 1401 * reduce eirr to 1402 * - ints that are enabled at or below this ipl 1403 * - exclude count/compare clock and soft ints 1404 * they are handled elsewhere 1405 */ 1406 eirr &= ipl_eimr_map[ipl-1]; 1407 eirr &= ~ipl_eimr_map[ipl]; 1408 eirr &= ~((MIPS_INT_MASK_5 | MIPS_SOFT_INT_MASK) >> 8); 1409 if (eirr == 0) 1410 break; 1411 1412 vec = 63 - dclz(eirr); 1413 rmixl_intrvec_t * const iv = &rmixl_intrvec[vec]; 1414 vecbit = 1ULL << vec; 1415 KASSERT (iv->iv_ipl == ipl); 1416 LIST_FOREACH(ih, &iv->iv_hands, ih_link) { 1417 KASSERT ((vecbit & eimr) == 0); 1418 KASSERT ((vecbit & RMIXL_EIRR_PRESERVE_MASK) == 0); 1419 1420 /* 1421 * ack in EIRR, and in PIC if needed, 1422 * the irq we are about to handle 1423 */ 1424 rmixl_eirr_ack(eimr, vecbit, RMIXL_EIRR_PRESERVE_MASK); 1425 if (ih != &iv->iv_intrhand) { 1426 size_t irt = ih - rmixl_irt_intrhands; 1427 KASSERT(irt < rmixl_nirts); 1428 if (is_xlp_p) { 1429 RMIXLP_PICREG_WRITE(RMIXLP_PIC_INT_ACK, 1430 irt); 1431 } else { 1432 RMIXL_PICREG_WRITE(RMIXL_PIC_INTRACK, 1433 1 << irt); 1434 } 1435 sc->sc_irt_evcnts[irt].ev_count++; 1436 } 1437 1438 rmixl_intr_deliver(ih->ih_func, ih->ih_arg, 1439 ih->ih_mpsafe, &sc->sc_vec_evcnts[vec], ipl); 1440 1441 KASSERT(ipl == iv->iv_ipl); 1442 KASSERTMSG(curcpu()->ci_cpl >= ipl, 1443 ("%s: after %s: cpl (%d) < ipl %d", 1444 __func__, sc->sc_vec_evcnts[vec].ev_name, 1445 ipl, curcpu()->ci_cpl)); 1446 } 1447 } 1448 } 1449 1450 #ifdef MULTIPROCESSOR 1451 static int 1452 rmixl_send_ipi(struct cpu_info *ci, int tag) 1453 { 1454 const cpuid_t cpuid = ci->ci_cpuid; 1455 const uint64_t req = 1 << tag; 1456 const bool is_xlp_p = cpu_rmixlp(mips_options.mips_cpu); 1457 uint32_t r; 1458 1459 if (! CPUSET_HAS_P(cpus_running, cpu_index(ci))) 1460 return -1; 1461 1462 KASSERT(tag >= 0 && tag < NIPIS); 1463 1464 if (is_xlp_p) { 1465 r = RMXLP_PIC_IPI_CTRL_MAKE(0, __BIT(cpuid & 15), 1466 RMIXL_INTERVEC_IPI + tag); 1467 } else { 1468 const uint32_t core = (uint32_t)(cpuid >> 2); 1469 const uint32_t thread = (uint32_t)(cpuid & __BITS(1,0)); 1470 r = RMXLP_PIC_IPI_CTRL_MAKE(0, core, thread, 1471 RMIXL_INTERVEC_IPI + tag); 1472 } 1473 1474 mutex_enter(rmixl_ipi_lock); 1475 atomic_or_64(&ci->ci_request_ipis, req); 1476 __asm __volatile("sync"); 1477 if (is_xlp_p) { 1478 RMIXLP_PICREG_WRITE(RMIXLP_PIC_IPI_CTRL, r); 1479 } else { 1480 RMIXL_PICREG_WRITE(RMIXL_PIC_IPIBASE, r); 1481 } 1482 mutex_exit(rmixl_ipi_lock); 1483 1484 return 0; 1485 } 1486 1487 static int 1488 rmixl_ipi_intr(void *arg) 1489 { 1490 struct cpu_info * const ci = curcpu(); 1491 const uint64_t ipi_mask = 1 << (uintptr_t)arg; 1492 1493 KASSERT(ci->ci_cpl >= IPL_SCHED); 1494 KASSERT((uintptr_t)arg < NIPIS); 1495 1496 /* if the request is clear, it was previously processed */ 1497 if ((ci->ci_request_ipis & ipi_mask) == 0) 1498 return 0; 1499 1500 atomic_or_64(&ci->ci_active_ipis, ipi_mask); 1501 atomic_and_64(&ci->ci_request_ipis, ~ipi_mask); 1502 1503 ipi_process(ci, ipi_mask); 1504 1505 atomic_and_64(&ci->ci_active_ipis, ~ipi_mask); 1506 1507 return 1; 1508 } 1509 #endif /* MULTIPROCESSOR */ 1510 1511 #if defined(DIAGNOSTIC) || defined(IOINTR_DEBUG) || defined(DDB) 1512 int 1513 rmixl_intrvec_print_subr(size_t vec) 1514 { 1515 rmixl_intrvec_t * const iv = &rmixl_intrvec[vec]; 1516 rmixl_intrhand_t *ih; 1517 1518 printf("vec %zu: ipl %u\n", vec, iv->iv_ipl); 1519 1520 LIST_FOREACH(ih, &iv->iv_hands, ih_link) { 1521 if (ih == &iv->iv_intrhand) { 1522 printf(" [%s]: func %p, arg %p\n", 1523 rmixl_vecnames_common[vec], 1524 ih->ih_func, ih->ih_arg); 1525 } else { 1526 const size_t irt = ih - rmixl_irt_intrhands; 1527 printf(" irt %zu [%s]: func %p, arg %p\n", 1528 irt, rmixl_irtnames[irt], 1529 ih->ih_func, ih->ih_arg); 1530 } 1531 } 1532 return 0; 1533 } 1534 int 1535 rmixl_intrhand_print(void) 1536 { 1537 for (size_t vec = 0; vec < NINTRVECS; vec++) 1538 rmixl_intrvec_print_subr(vec); 1539 return 0; 1540 } 1541 1542 static inline void 1543 rmixl_irt_entry_print(size_t irt) 1544 { 1545 if (irt >= rmixl_nirts) 1546 return; 1547 if (cpu_rmixlp(mips_options.mips_cpu)) { 1548 uint64_t c = RMIXLP_PICREG_READ(RMIXLP_PIC_IRTENTRY(irt)); 1549 printf("irt[%zu]: %#"PRIx64"\n", irt, c); 1550 } else { 1551 uint32_t c0 = RMIXL_PICREG_READ(RMIXL_PIC_IRTENTRYC0(irt)); 1552 uint32_t c1 = RMIXL_PICREG_READ(RMIXL_PIC_IRTENTRYC1(irt)); 1553 printf("irt[%zu]: %#x, %#x\n", irt, c0, c1); 1554 } 1555 } 1556 1557 int 1558 rmixl_irt_print(void) 1559 { 1560 printf("%s:\n", __func__); 1561 for (size_t irt = 0; irt < rmixl_nirts ; irt++) 1562 rmixl_irt_entry_print(irt); 1563 return 0; 1564 } 1565 1566 void 1567 rmixl_ipl_eimr_map_print(void) 1568 { 1569 printf("IPL_NONE=%d, mask %#"PRIx64"\n", 1570 IPL_NONE, ipl_eimr_map[IPL_NONE]); 1571 printf("IPL_SOFTCLOCK=%d, mask %#"PRIx64"\n", 1572 IPL_SOFTCLOCK, ipl_eimr_map[IPL_SOFTCLOCK]); 1573 printf("IPL_SOFTNET=%d, mask %#"PRIx64"\n", 1574 IPL_SOFTNET, ipl_eimr_map[IPL_SOFTNET]); 1575 printf("IPL_VM=%d, mask %#"PRIx64"\n", 1576 IPL_VM, ipl_eimr_map[IPL_VM]); 1577 printf("IPL_SCHED=%d, mask %#"PRIx64"\n", 1578 IPL_SCHED, ipl_eimr_map[IPL_SCHED]); 1579 printf("IPL_DDB=%d, mask %#"PRIx64"\n", 1580 IPL_DDB, ipl_eimr_map[IPL_DDB]); 1581 printf("IPL_HIGH=%d, mask %#"PRIx64"\n", 1582 IPL_HIGH, ipl_eimr_map[IPL_HIGH]); 1583 } 1584 1585 #endif 1586
Indexes created Sat Oct 18 08:10:09 GMT 2025