rmixl_intr.h revision 1.1.2.2 1 /* $NetBSD: rmixl_intr.h,v 1.1.2.2 2010/04/12 22:40:55 cliff Exp $ */
2
3 #ifndef _MIPS_RMI_RMIXL_INTR_H_
4 #define _MIPS_RMI_RMIXL_INTR_H_
5
6 /*
7 * An 'irq' is an EIRR bit numbers or 'vector' as used in the PRM
8 * - PIC-based irqs are in the range 0..31 and index into the IRT
9 * - IRT entry <n> always routes to vector <n>
10 * - non-PIC-based irqs are in the range 32..63
11 * - only 1 intrhand_t per irq/vector
12 */
13 #define NINTRVECS 64 /* bit width of the EIRR */
14 #define NIRTS 32 /* #entries in the Interrupt Redirection Table */
15
16 /*
17 * reserved vectors >=32
18 */
19 #define RMIXL_INTRVEC_IPI 32
20 #define RMIXL_INTRVEC_FMN 33
21
22 typedef enum {
23 RMIXL_TRIG_NONE=0,
24 RMIXL_TRIG_EDGE,
25 RMIXL_TRIG_LEVEL,
26 } rmixl_intr_trigger_t;
27
28 typedef enum {
29 RMIXL_POLR_NONE=0,
30 RMIXL_POLR_RISING,
31 RMIXL_POLR_HIGH,
32 RMIXL_POLR_FALLING,
33 RMIXL_POLR_LOW,
34 } rmixl_intr_polarity_t;
35
36
37 /*
38 * iv_list and ref count manage sharing of each vector
39 */
40 typedef struct rmixl_intrhand {
41 int (*ih_func)(void *);
42 void *ih_arg;
43 int ih_mpsafe; /* true if does not need kernel lock */
44 int ih_irq; /* >=32 if not-PIC-based */
45 int ih_ipl; /* interrupt priority */
46 int ih_cpumask; /* CPUs which may handle this irpt */
47 } rmixl_intrhand_t;
48
49 /*
50 * stuff exported from rmixl_spl.S
51 */
52 extern const struct splsw rmixl_splsw;
53 extern uint64_t ipl_eimr_map[];
54
55 extern void *rmixl_intr_establish(int, int, int,
56 rmixl_intr_trigger_t, rmixl_intr_polarity_t,
57 int (*)(void *), void *, bool);
58 extern void rmixl_intr_disestablish(void *);
59 extern void *rmixl_vec_establish(int, int, int,
60 int (*)(void *), void *, bool);
61 extern void rmixl_vec_disestablish(void *);
62 extern const char *rmixl_intr_string(int);
63 extern void rmixl_intr_init_cpu(struct cpu_info *);
64 extern void *rmixl_intr_init_clk(void);
65 #ifdef MULTIPROCESSOR
66 extern void *rmixl_intr_init_ipi(void);
67 #endif
68
69 #endif /* _MIPS_RMI_RMIXL_INTR_H_ */
70