| History log of /src/sys/arch/mips/rmi/rmixl_intr.h |
| Revision | | Date | Author | Comments |
| 1.3 |
| 14-Apr-2011 |
cliff | - add compile time check in case NIPIS ever exceeds number of available vectors
|
| 1.2 |
| 20-Feb-2011 |
matt | branches: 1.2.2;
Merge forward from matt-nb5-mips64.
|
| 1.1 |
| 21-Mar-2010 |
cliff | branches: 1.1.2; 1.1.4; 1.1.6;
file rmixl_intr.h was initially added on branch matt-nb5-mips64.
|
| 1.1.6.1 |
| 05-Mar-2011 |
bouyer | Sync with HEAD
|
| 1.1.4.1 |
| 06-Jun-2011 |
jruoho | Sync with HEAD.
|
| 1.1.2.13 |
| 05-Nov-2013 |
matt | Add XLP2XX support.
|
| 1.1.2.12 |
| 04-Jan-2012 |
matt | Rework Fast Messaging Network support (it's now lockless).
Workaround a problem with bus 0 BAR sizing causing the registers behind
the BAR to become inaccessible.
Move much/most of the startup code from evbmips/rmixl/machdep to
mips/rmi/rmixl_machdep.c
Move the code to find the XLP variant to the early boot so it can be used
early.
8bit and 16bit accessed to PCI bus 0 cause cache errors so chagne the access
of pci mem to 32bits.
|
| 1.1.2.11 |
| 31-Dec-2011 |
matt | Switch to using IST_<foo> instead of private enums.
|
| 1.1.2.10 |
| 30-Dec-2011 |
matt | Add GPIO support for XLP.
Let NAND, MMC/SD, and SPI remove their pins from the GPIO available pin mask.
|
| 1.1.2.9 |
| 24-Dec-2011 |
matt | Add XLP support (i2c, console, pci, sdhc works).
|
| 1.1.2.8 |
| 29-Apr-2011 |
matt | Major merge to/from current.
Adds MIPS32/MIPS64 R2 support (24k, 74k, etc.) including COP0_USERLOCAL
Adds support for emulation of rdhwr $3,$29 instruction.
Major cleanup of SMP code. (stable on multi-core / single thread per core)
llsc locking code only used in MP capable kernels.
|
| 1.1.2.7 |
| 08-Feb-2011 |
cliff | - remove sc_ih_clk, sc_ih_fmn, sc_ih_ipi from struct rmixl_cpu_softc;
they were unused just taking up space
- rmixl_intr_init_clk() and rmixl_intr_init_ipi() are now type void
|
| 1.1.2.6 |
| 05-Feb-2011 |
cliff | - protect option includes ("opt_multiprocessor.h") with #ifdef _KERNEL_OPT
|
| 1.1.2.5 |
| 05-Feb-2011 |
cliff | - include opt_multiprocessor.h for MULTIPROCESSOR dependency
- move RMIXL_INTRVEC_FMN to RMIXL_INTRVEC_IPI + NIPIS
since each IPI tag now has own vector
|
| 1.1.2.4 |
| 21-May-2010 |
cliff | - rename IRT based interrupts to "pic int ..."
- rename rmixl_vecnames_common to "vec ..."
- move ipl_eimr_map table print into rmixl_ipl_eimr_map_print()
- consolidate debug print funcs at the end of the file
- 'irq' -- being somewhat ambiguous -- renamed to 'irt' throughout
to reflect use as IRT index
- IRT-based interrupts are moved to EIRR/EIMR vectors (bits) 32..63
to avoid all opverlap with EIRR/EIMR bits 0..7 which are CAUSE[8..15].
To date this has been a non-issue since we aren't using the
watchdog or timers there. non-IRT interrupts (FMN and IPI) are moved
to unused portion vectors 8, 9
- in rmixl_intr_init_cpu, instead of writing 0 to EIRR, ack with bits read
(excluding CAUSE[8..15] bits) as defense against possible stale
interrupts inherited from firmware (paranoid -- we aren't seeing any).
- rmixl_irt_establish gets a 'vec' arg for use in IRTENTRYC1 reg
(no longer assume vec = irt)
- set/clear irq bits in ipl_eimr_map[] during interrupt establish/disestablish
- in evbmips_iointr(), mask off ints enabled at higher ipl; we only
dispatch interrupts at highest enabling ipl.
|
| 1.1.2.3 |
| 13-Apr-2010 |
cliff | add TNF License and copyright.
|
| 1.1.2.2 |
| 12-Apr-2010 |
cliff | - establishing an ISR now takes 'mpsafe' arg
- obtain/release kernel lock around calls to non-mpsafe ISRs
|
| 1.1.2.1 |
| 21-Mar-2010 |
cliff | - added this file of RMI interrupt stuff
|
| 1.2.2.3 |
| 21-Apr-2011 |
rmind | sync with head
|
| 1.2.2.2 |
| 05-Mar-2011 |
rmind | sync with head
|
| 1.2.2.1 |
| 20-Feb-2011 |
rmind | file rmixl_intr.h was added on branch rmind-uvmplock on 2011-03-05 20:51:10 +0000
|
