rmixl_iobus.c revision 1.2.2.2 1 1.2.2.2 rmind /* $NetBSD: rmixl_iobus.c,v 1.2.2.2 2011/04/21 01:41:13 rmind Exp $ */
2 1.2.2.2 rmind
3 1.2.2.2 rmind /*-
4 1.2.2.2 rmind * Copyright (c) 2011 The NetBSD Foundation, Inc.
5 1.2.2.2 rmind * All rights reserved.
6 1.2.2.2 rmind *
7 1.2.2.2 rmind * This code is derived from software contributed to The NetBSD Foundation
8 1.2.2.2 rmind * by Cliff Neighbors
9 1.2.2.2 rmind *
10 1.2.2.2 rmind * Redistribution and use in source and binary forms, with or without
11 1.2.2.2 rmind * modification, are permitted provided that the following conditions
12 1.2.2.2 rmind * are met:
13 1.2.2.2 rmind * 1. Redistributions of source code must retain the above copyright
14 1.2.2.2 rmind * notice, this list of conditions and the following disclaimer.
15 1.2.2.2 rmind * 2. Redistributions in binary form must reproduce the above copyright
16 1.2.2.2 rmind * notice, this list of conditions and the following disclaimer in the
17 1.2.2.2 rmind * documentation and/or other materials provided with the distribution.
18 1.2.2.2 rmind *
19 1.2.2.2 rmind * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 1.2.2.2 rmind * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 1.2.2.2 rmind * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 1.2.2.2 rmind * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 1.2.2.2 rmind * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 1.2.2.2 rmind * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 1.2.2.2 rmind * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 1.2.2.2 rmind * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 1.2.2.2 rmind * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 1.2.2.2 rmind * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 1.2.2.2 rmind * POSSIBILITY OF SUCH DAMAGE.
30 1.2.2.2 rmind */
31 1.2.2.2 rmind
32 1.2.2.2 rmind /*
33 1.2.2.2 rmind * RMI Peripherals IO Bus support
34 1.2.2.2 rmind * - interface to NOR, NAND, PCMCIA Memory controlers, &etc.
35 1.2.2.2 rmind * - manages the 10 Chip Selects
36 1.2.2.2 rmind * - manages the "Flash" interrupts
37 1.2.2.2 rmind * - manages the "Flash" errors
38 1.2.2.2 rmind */
39 1.2.2.2 rmind
40 1.2.2.2 rmind /*
41 1.2.2.2 rmind * iobus control registers are accessed as 32 bits.
42 1.2.2.2 rmind * ALEn and CLEn NAND control registers are defined as 8 bits wide
43 1.2.2.2 rmind * but that seems to be a documentation error.
44 1.2.2.2 rmind *
45 1.2.2.2 rmind * iobus data access may be as 1 or 2 or 4 bytes, even if device is 1 byte wide;
46 1.2.2.2 rmind * the controller will sequence the bytes, in big-endian order.
47 1.2.2.2 rmind */
48 1.2.2.2 rmind
49 1.2.2.2 rmind #include <sys/cdefs.h>
50 1.2.2.2 rmind __KERNEL_RCSID(0, "$NetBSD: rmixl_iobus.c,v 1.2.2.2 2011/04/21 01:41:13 rmind Exp $");
51 1.2.2.2 rmind
52 1.2.2.2 rmind #include "locators.h"
53 1.2.2.2 rmind
54 1.2.2.2 rmind #include <sys/param.h>
55 1.2.2.2 rmind #include <sys/systm.h>
56 1.2.2.2 rmind #include <sys/device.h>
57 1.2.2.2 rmind
58 1.2.2.2 rmind #include <machine/bus.h>
59 1.2.2.2 rmind
60 1.2.2.2 rmind #include <mips/rmi/rmixlreg.h>
61 1.2.2.2 rmind #include <mips/rmi/rmixlvar.h>
62 1.2.2.2 rmind #include <mips/rmi/rmixl_intr.h>
63 1.2.2.2 rmind #include <mips/rmi/rmixl_obiovar.h>
64 1.2.2.2 rmind #include <mips/rmi/rmixl_iobusvar.h>
65 1.2.2.2 rmind // #include <mips/rmi/rmixl_gpiovar.h>
66 1.2.2.2 rmind
67 1.2.2.2 rmind typedef struct {
68 1.2.2.2 rmind bool cs_allocated;
69 1.2.2.2 rmind uint32_t cs_addr; /* base address on the Peripherals I/O Bus */
70 1.2.2.2 rmind uint32_t cs_mask; /* address mask on the Peripherals I/O Bus */
71 1.2.2.2 rmind uint32_t cs_dev_parm;
72 1.2.2.2 rmind } rmixl_iobus_csconfig_t;
73 1.2.2.2 rmind
74 1.2.2.2 rmind typedef struct rmixl_iobus_softc {
75 1.2.2.2 rmind device_t sc_dev;
76 1.2.2.2 rmind bus_space_tag_t sc_obio_bst; /* for iobus device controler access */
77 1.2.2.2 rmind bus_space_handle_t sc_obio_bsh; /* " " " " " */
78 1.2.2.2 rmind bus_addr_t sc_obio_addr;
79 1.2.2.2 rmind bus_size_t sc_obio_size;
80 1.2.2.2 rmind bus_space_tag_t sc_iobus_bst; /* for iobus access */
81 1.2.2.2 rmind rmixl_iobus_csconfig_t sc_csconfig[RMIXL_FLASH_NCS];
82 1.2.2.2 rmind } rmixl_iobus_softc_t;
83 1.2.2.2 rmind
84 1.2.2.2 rmind
85 1.2.2.2 rmind static int rmixl_iobus_match(device_t, cfdata_t, void *);
86 1.2.2.2 rmind static void rmixl_iobus_attach(device_t, device_t, void *);
87 1.2.2.2 rmind static void rmixl_iobus_csconfig_init(struct rmixl_iobus_softc *);
88 1.2.2.2 rmind static int rmixl_iobus_print(void *, const char *);
89 1.2.2.2 rmind static int rmixl_iobus_search(device_t, cfdata_t, const int *, void *);
90 1.2.2.2 rmind #ifdef NOTYET
91 1.2.2.2 rmind static int rmixl_iobus_intr(void *);
92 1.2.2.2 rmind #endif
93 1.2.2.2 rmind
94 1.2.2.2 rmind #ifdef RMIXL_IOBUS_DEBUG
95 1.2.2.2 rmind rmixl_iobus_softc_t *rmixl_iobus_sc;
96 1.2.2.2 rmind #endif
97 1.2.2.2 rmind
98 1.2.2.2 rmind
99 1.2.2.2 rmind CFATTACH_DECL_NEW(rmixl_iobus, sizeof (rmixl_iobus_softc_t),
100 1.2.2.2 rmind rmixl_iobus_match, rmixl_iobus_attach, NULL, NULL);
101 1.2.2.2 rmind
102 1.2.2.2 rmind int
103 1.2.2.2 rmind rmixl_iobus_match(device_t parent, cfdata_t match, void *aux)
104 1.2.2.2 rmind {
105 1.2.2.2 rmind struct obio_attach_args *obio = aux;
106 1.2.2.2 rmind
107 1.2.2.2 rmind if (obio->obio_addr == RMIXL_IO_DEV_FLASH)
108 1.2.2.2 rmind return rmixl_probe_4((volatile uint32_t *)
109 1.2.2.2 rmind RMIXL_IOREG_VADDR(obio->obio_addr));
110 1.2.2.2 rmind
111 1.2.2.2 rmind return 0;
112 1.2.2.2 rmind }
113 1.2.2.2 rmind
114 1.2.2.2 rmind void
115 1.2.2.2 rmind rmixl_iobus_attach(device_t parent, device_t self, void *aux)
116 1.2.2.2 rmind {
117 1.2.2.2 rmind rmixl_iobus_softc_t *sc = device_private(self);
118 1.2.2.2 rmind struct obio_attach_args *obio = aux;
119 1.2.2.2 rmind struct rmixl_config *rcp = &rmixl_configuration;
120 1.2.2.2 rmind uint64_t r;
121 1.2.2.2 rmind int err;
122 1.2.2.2 rmind
123 1.2.2.2 rmind #ifdef RMIXL_IOBUS_DEBUG
124 1.2.2.2 rmind rmixl_iobus_sc = sc;
125 1.2.2.2 rmind #endif
126 1.2.2.2 rmind sc->sc_dev = self;
127 1.2.2.2 rmind sc->sc_obio_bst = obio->obio_eb_bst;
128 1.2.2.2 rmind sc->sc_obio_addr = obio->obio_addr;
129 1.2.2.2 rmind sc->sc_obio_size = 0x1000;
130 1.2.2.2 rmind
131 1.2.2.2 rmind err = bus_space_map(sc->sc_obio_bst, sc->sc_obio_addr,
132 1.2.2.2 rmind sc->sc_obio_size, 0, &sc->sc_obio_bsh);
133 1.2.2.2 rmind if (err != 0) {
134 1.2.2.2 rmind aprint_error_dev(self,
135 1.2.2.2 rmind "bus space map err %d, iobus space\n", err);
136 1.2.2.2 rmind return;
137 1.2.2.2 rmind }
138 1.2.2.2 rmind
139 1.2.2.2 rmind r = RMIXL_IOREG_READ(RMIXL_SBC_FLASH_BAR);
140 1.2.2.2 rmind KASSERT((r & 1) != 0); /* BAR is enabled */
141 1.2.2.2 rmind rcp->rc_flash_pbase = RMIXL_FLASH_BAR_TO_BA(r);
142 1.2.2.2 rmind rcp->rc_flash_mask = RMIXL_FLASH_BAR_TO_MASK(r);
143 1.2.2.2 rmind
144 1.2.2.2 rmind aprint_normal("\n");
145 1.2.2.2 rmind aprint_debug_dev(self,
146 1.2.2.2 rmind "Flash BAR pbase %#" PRIx64 " mask %#" PRIx64 "\n",
147 1.2.2.2 rmind rcp->rc_flash_pbase, rcp->rc_flash_mask);
148 1.2.2.2 rmind
149 1.2.2.2 rmind /* initialize iobus bus space */
150 1.2.2.2 rmind rmixl_iobus_bus_mem_init(&rcp->rc_iobus_memt, rcp);
151 1.2.2.2 rmind sc->sc_iobus_bst = (bus_space_tag_t)&rcp->rc_iobus_memt;
152 1.2.2.2 rmind
153 1.2.2.2 rmind /* disable all Flsah interupts */
154 1.2.2.2 rmind bus_space_write_4(sc->sc_obio_bst, sc->sc_obio_bsh,
155 1.2.2.2 rmind RMIXL_FLASH_INT_MASK, 0);
156 1.2.2.2 rmind
157 1.2.2.2 rmind /* write-1-to-clear Flash interrupt status */
158 1.2.2.2 rmind bus_space_write_4(sc->sc_obio_bst, sc->sc_obio_bsh,
159 1.2.2.2 rmind RMIXL_FLASH_INT_STATUS, ~0);
160 1.2.2.2 rmind
161 1.2.2.2 rmind rmixl_iobus_csconfig_init(sc);
162 1.2.2.2 rmind
163 1.2.2.2 rmind /* attach any children */
164 1.2.2.2 rmind config_search_ia(rmixl_iobus_search, self, "rmixl_iobus", NULL);
165 1.2.2.2 rmind }
166 1.2.2.2 rmind
167 1.2.2.2 rmind static void
168 1.2.2.2 rmind rmixl_iobus_csconfig_init(struct rmixl_iobus_softc *sc)
169 1.2.2.2 rmind {
170 1.2.2.2 rmind rmixl_iobus_csconfig_t *cs = &sc->sc_csconfig[0];
171 1.2.2.2 rmind
172 1.2.2.2 rmind for (int i=0; i < RMIXL_FLASH_NCS; i++) {
173 1.2.2.2 rmind memset(cs, 0, sizeof(rmixl_iobus_csconfig_t));
174 1.2.2.2 rmind cs->cs_addr = bus_space_read_4(sc->sc_obio_bst, sc->sc_obio_bsh,
175 1.2.2.2 rmind RMIXL_FLASH_CSBASE_ADDRn(i)) << 16;
176 1.2.2.2 rmind cs->cs_mask = bus_space_read_4(sc->sc_obio_bst, sc->sc_obio_bsh,
177 1.2.2.2 rmind RMIXL_FLASH_CSADDR_MASKn(i)) << 16;
178 1.2.2.2 rmind cs->cs_mask |= __BITS(15,0);
179 1.2.2.2 rmind cs->cs_dev_parm = bus_space_read_4(sc->sc_obio_bst, sc->sc_obio_bsh,
180 1.2.2.2 rmind RMIXL_FLASH_CSDEV_PARMn(i));
181 1.2.2.2 rmind aprint_debug_dev(sc->sc_dev,
182 1.2.2.2 rmind "CS#%d: addr 0x%08x mask 0x%08x parm 0x%08x\n",
183 1.2.2.2 rmind i, cs->cs_addr, cs->cs_mask, cs->cs_dev_parm);
184 1.2.2.2 rmind cs++;
185 1.2.2.2 rmind }
186 1.2.2.2 rmind }
187 1.2.2.2 rmind
188 1.2.2.2 rmind
189 1.2.2.2 rmind static int
190 1.2.2.2 rmind rmixl_iobus_print(void *aux, const char *pnp)
191 1.2.2.2 rmind {
192 1.2.2.2 rmind struct rmixl_iobus_attach_args *ia = aux;
193 1.2.2.2 rmind
194 1.2.2.2 rmind if (ia->ia_cs != RMIXL_IOBUSCF_CS_DEFAULT)
195 1.2.2.2 rmind aprint_normal(" CS#%d", ia->ia_cs);
196 1.2.2.2 rmind if (ia->ia_iobus_addr != RMIXL_IOBUSCF_ADDR_DEFAULT) {
197 1.2.2.2 rmind aprint_normal(" addr %#" PRIxBUSADDR, ia->ia_iobus_addr);
198 1.2.2.2 rmind if (ia->ia_iobus_size != RMIXL_IOBUSCF_SIZE_DEFAULT)
199 1.2.2.2 rmind aprint_normal("-%#" PRIxBUSSIZE,
200 1.2.2.2 rmind ia->ia_iobus_addr + (ia->ia_iobus_size - 1));
201 1.2.2.2 rmind }
202 1.2.2.2 rmind if (ia->ia_iobus_intr != RMIXL_IOBUSCF_INTR_DEFAULT)
203 1.2.2.2 rmind aprint_normal(" intr %d", ia->ia_iobus_intr);
204 1.2.2.2 rmind
205 1.2.2.2 rmind return UNCONF;
206 1.2.2.2 rmind }
207 1.2.2.2 rmind
208 1.2.2.2 rmind static int
209 1.2.2.2 rmind rmixl_iobus_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux)
210 1.2.2.2 rmind {
211 1.2.2.2 rmind struct rmixl_iobus_softc *sc = device_private(parent);
212 1.2.2.2 rmind struct rmixl_iobus_attach_args ia;
213 1.2.2.2 rmind rmixl_iobus_csconfig_t *cs;
214 1.2.2.2 rmind
215 1.2.2.2 rmind ia.ia_obio_bst = sc->sc_obio_bst;
216 1.2.2.2 rmind ia.ia_obio_bsh = sc->sc_obio_bsh;
217 1.2.2.2 rmind ia.ia_iobus_bst = sc->sc_iobus_bst;
218 1.2.2.2 rmind ia.ia_iobus_addr = (bus_addr_t)cf->cf_loc[RMIXL_IOBUSCF_ADDR];
219 1.2.2.2 rmind ia.ia_iobus_size = (bus_size_t)cf->cf_loc[RMIXL_IOBUSCF_SIZE];
220 1.2.2.2 rmind ia.ia_iobus_intr = cf->cf_loc[RMIXL_IOBUSCF_INTR];
221 1.2.2.2 rmind ia.ia_cs = cf->cf_loc[RMIXL_IOBUSCF_CS];
222 1.2.2.2 rmind
223 1.2.2.2 rmind if (ia.ia_cs != RMIXL_IOBUSCF_CS_DEFAULT) {
224 1.2.2.2 rmind /* CS is configured */
225 1.2.2.2 rmind cs = &sc->sc_csconfig[ia.ia_cs];
226 1.2.2.2 rmind
227 1.2.2.2 rmind /* ensure exclusive use of chip select */
228 1.2.2.2 rmind if (cs->cs_allocated) {
229 1.2.2.2 rmind aprint_error_dev(parent, "CS#%d already allocated\n",
230 1.2.2.2 rmind ia.ia_cs);
231 1.2.2.2 rmind return 0;
232 1.2.2.2 rmind }
233 1.2.2.2 rmind if (ia.ia_iobus_addr != RMIXL_IOBUSCF_ADDR_DEFAULT) {
234 1.2.2.2 rmind if (ia.ia_iobus_addr != cs->cs_addr) {
235 1.2.2.2 rmind /*
236 1.2.2.2 rmind * both CS and addr are configured,
237 1.2.2.2 rmind * ensure they match
238 1.2.2.2 rmind */
239 1.2.2.2 rmind aprint_error_dev(parent,
240 1.2.2.2 rmind "CS#%d addr 0x%08x mismatch cf_loc "
241 1.2.2.2 rmind "addr 0x%08" PRIxBUSADDR "\n",
242 1.2.2.2 rmind ia.ia_cs, cs->cs_addr, ia.ia_iobus_addr);
243 1.2.2.2 rmind return 0;
244 1.2.2.2 rmind }
245 1.2.2.2 rmind } else {
246 1.2.2.2 rmind /* no addr configured, pull from CS */
247 1.2.2.2 rmind ia.ia_iobus_addr = cs->cs_addr;
248 1.2.2.2 rmind }
249 1.2.2.2 rmind } else {
250 1.2.2.2 rmind /* addr is configured, CS is not; search for matching CS */
251 1.2.2.2 rmind bool found = false;
252 1.2.2.2 rmind cs = &sc->sc_csconfig[0];
253 1.2.2.2 rmind for (int i=0; i < RMIXL_FLASH_NCS; i++) {
254 1.2.2.2 rmind if (cs->cs_allocated)
255 1.2.2.2 rmind continue;
256 1.2.2.2 rmind if (cs->cs_addr == ia.ia_iobus_addr) {
257 1.2.2.2 rmind ia.ia_cs = i;
258 1.2.2.2 rmind found = true;
259 1.2.2.2 rmind break;
260 1.2.2.2 rmind }
261 1.2.2.2 rmind cs++;
262 1.2.2.2 rmind }
263 1.2.2.2 rmind if (! found) {
264 1.2.2.2 rmind aprint_error_dev(parent, "no CS for addr 0x%08"
265 1.2.2.2 rmind PRIxBUSADDR "\n", ia.ia_iobus_addr);
266 1.2.2.2 rmind return 0;
267 1.2.2.2 rmind }
268 1.2.2.2 rmind }
269 1.2.2.2 rmind
270 1.2.2.2 rmind if (ia.ia_iobus_size != RMIXL_IOBUSCF_SIZE_DEFAULT) {
271 1.2.2.2 rmind /* ensure size fits w/ CS mask */
272 1.2.2.2 rmind if ((ia.ia_iobus_size - 1) > (bus_size_t)cs->cs_mask) {
273 1.2.2.2 rmind aprint_error_dev(parent, "size %#" PRIxBUSSIZE
274 1.2.2.2 rmind " exceeds CS#%d mask 0x%08x\n",
275 1.2.2.2 rmind ia.ia_iobus_size, ia.ia_cs, cs->cs_mask);
276 1.2.2.2 rmind }
277 1.2.2.2 rmind } else {
278 1.2.2.2 rmind /* size not configured, pull from CS */
279 1.2.2.2 rmind ia.ia_iobus_size = (bus_size_t)cs->cs_mask + 1;
280 1.2.2.2 rmind }
281 1.2.2.2 rmind
282 1.2.2.2 rmind ia.ia_dev_parm = cs->cs_dev_parm;
283 1.2.2.2 rmind
284 1.2.2.2 rmind if (config_match(parent, cf, &ia) > 0) {
285 1.2.2.2 rmind cs->cs_allocated = true;
286 1.2.2.2 rmind config_attach(parent, cf, &ia, rmixl_iobus_print);
287 1.2.2.2 rmind }
288 1.2.2.2 rmind
289 1.2.2.2 rmind return 0;
290 1.2.2.2 rmind }
291 1.2.2.2 rmind
292 1.2.2.2 rmind
293 1.2.2.2 rmind #ifdef NOTYET
294 1.2.2.2 rmind
295 1.2.2.2 rmind void
296 1.2.2.2 rmind rmixl_iobus_intr_disestablish(void *uh, void *ih)
297 1.2.2.2 rmind {
298 1.2.2.2 rmind rmixl_iobus_softc_t *sc = uh;
299 1.2.2.2 rmind u_int intr;
300 1.2.2.2 rmind
301 1.2.2.2 rmind for (intr=0; intr <= RMIXL_UB_INTERRUPT_MAX; intr++) {
302 1.2.2.2 rmind if (ih == &sc->sc_dispatch[intr]) {
303 1.2.2.2 rmind uint32_t r;
304 1.2.2.2 rmind
305 1.2.2.2 rmind /* disable this interrupt in the usb interface */
306 1.2.2.2 rmind r = bus_space_read_4(sc->sc_obio_bst, sc->sc_obio_bsh,
307 1.2.2.2 rmind RMIXL_USB_INTERRUPT_ENABLE);
308 1.2.2.2 rmind r &= 1 << intr;
309 1.2.2.2 rmind bus_space_write_4(sc->sc_obio_bst, sc->sc_obio_bsh,
310 1.2.2.2 rmind RMIXL_USB_INTERRUPT_ENABLE, r);
311 1.2.2.2 rmind
312 1.2.2.2 rmind /* free the dispatch slot */
313 1.2.2.2 rmind sc->sc_dispatch[intr].func = NULL;
314 1.2.2.2 rmind sc->sc_dispatch[intr].arg = NULL;
315 1.2.2.2 rmind
316 1.2.2.2 rmind break;
317 1.2.2.2 rmind }
318 1.2.2.2 rmind }
319 1.2.2.2 rmind }
320 1.2.2.2 rmind
321 1.2.2.2 rmind void *
322 1.2.2.2 rmind rmixl_iobus_intr_establish(void *uh, u_int intr, int (func)(void *), void *arg)
323 1.2.2.2 rmind {
324 1.2.2.2 rmind rmixl_iobus_softc_t *sc = uh;
325 1.2.2.2 rmind uint32_t r;
326 1.2.2.2 rmind void *ih = NULL;
327 1.2.2.2 rmind int s;
328 1.2.2.2 rmind
329 1.2.2.2 rmind s = splusb();
330 1.2.2.2 rmind
331 1.2.2.2 rmind if (intr > RMIXL_UB_INTERRUPT_MAX) {
332 1.2.2.2 rmind aprint_error_dev(sc->sc_dev, "invalid intr %d\n", intr);
333 1.2.2.2 rmind goto out;
334 1.2.2.2 rmind }
335 1.2.2.2 rmind
336 1.2.2.2 rmind if (sc->sc_dispatch[intr].func != NULL) {
337 1.2.2.2 rmind aprint_error_dev(sc->sc_dev, "intr %dq busy\n", intr);
338 1.2.2.2 rmind goto out;
339 1.2.2.2 rmind }
340 1.2.2.2 rmind
341 1.2.2.2 rmind sc->sc_dispatch[intr].func = func;
342 1.2.2.2 rmind sc->sc_dispatch[intr].arg = arg;
343 1.2.2.2 rmind ih = &sc->sc_dispatch[intr];
344 1.2.2.2 rmind
345 1.2.2.2 rmind /* enable this interrupt in the usb interface */
346 1.2.2.2 rmind r = bus_space_read_4(sc->sc_obio_bst, sc->sc_obio_bsh,
347 1.2.2.2 rmind RMIXL_USB_INTERRUPT_ENABLE);
348 1.2.2.2 rmind r |= 1 << intr;
349 1.2.2.2 rmind bus_space_write_4(sc->sc_obio_bst, sc->sc_obio_bsh,
350 1.2.2.2 rmind RMIXL_USB_INTERRUPT_ENABLE, r);
351 1.2.2.2 rmind
352 1.2.2.2 rmind out:
353 1.2.2.2 rmind splx(s);
354 1.2.2.2 rmind return ih;
355 1.2.2.2 rmind }
356 1.2.2.2 rmind
357 1.2.2.2 rmind static int
358 1.2.2.2 rmind rmixl_iobus_intr(void *arg)
359 1.2.2.2 rmind {
360 1.2.2.2 rmind rmixl_iobus_softc_t *sc = arg;
361 1.2.2.2 rmind uint32_t r;
362 1.2.2.2 rmind int intr;
363 1.2.2.2 rmind int rv = 0;
364 1.2.2.2 rmind
365 1.2.2.2 rmind r = bus_space_read_4(sc->sc_obio_bst, sc->sc_obio_bsh,
366 1.2.2.2 rmind RMIXL_USB_INTERRUPT_STATUS);
367 1.2.2.2 rmind if (r != 0) {
368 1.2.2.2 rmind for (intr=0; intr <= RMIXL_UB_INTERRUPT_MAX; intr++) {
369 1.2.2.2 rmind uint32_t bit = 1 << intr;
370 1.2.2.2 rmind if ((r & bit) != 0) {
371 1.2.2.2 rmind int (*f)(void *) = sc->sc_dispatch[intr].func;
372 1.2.2.2 rmind void *a = sc->sc_dispatch[intr].arg;
373 1.2.2.2 rmind if (f != NULL) {
374 1.2.2.2 rmind (void)(*f)(a);
375 1.2.2.2 rmind sc->sc_dispatch[intr].count.ev_count++;
376 1.2.2.2 rmind rv = 1;
377 1.2.2.2 rmind }
378 1.2.2.2 rmind }
379 1.2.2.2 rmind }
380 1.2.2.2 rmind }
381 1.2.2.2 rmind
382 1.2.2.2 rmind return rv;
383 1.2.2.2 rmind }
384 1.2.2.2 rmind
385 1.2.2.2 rmind #endif /* NOTYET */
386