rmixl_subr.S revision 1.1.2.4 1 /* $NetBSD: rmixl_subr.S,v 1.1.2.4 2010/02/10 19:45:48 cliff Exp $ */
2
3 #include "opt_cputype.h"
4
5 #include <sys/cdefs.h>
6
7 #include <mips/cpuregs.h>
8 #include <mips/asm.h>
9
10 #include "assym.h"
11
12 .set push
13 .set noreorder
14 .set mips64
15 .text
16
17 /*
18 * read XLS Processor Control register
19 *
20 * uint64_t rmixl_mfcr(u_int cr);
21 */
22 LEAF(rmixl_mfcr)
23 #if defined(__mips_o32)
24 #error O32 not supported
25 #endif
26 j ra
27 mfcr v0, a0
28 END(rmixl_mfcr)
29
30 /*
31 * write XLS Processor Control register
32 *
33 * void rmixl_mtcr(u_int cr, uint64_t val);
34 */
35 LEAF(rmixl_mtcr)
36 #if defined(__mips_o32)
37 #error O32 not supported
38 #endif
39 j ra
40 mtcr a1, a0
41 END(rmixl_mtcr)
42
43 /*
44 * rmixlfw_wakeup_cpu(func, args, mask, callback)
45 */
46 NESTED(rmixlfw_wakeup_cpu, CALLFRAME_SIZ+2*SZREG, ra)
47 PTR_ADDU sp, sp, -(CALLFRAME_SIZ+2*SZREG)
48 REG_S ra, CALLFRAME_RA(sp)
49 REG_S s0, CALLFRAME_S0(sp)
50 REG_S gp, CALLFRAME_SIZ+0*SZREG(sp)
51 REG_S t8, CALLFRAME_SIZ+1*SZREG(sp)
52
53 move s0, sp /* save sp */
54 srl t0, sp, 0 /* nuke upper half */
55 li t1, MIPS_KSEG0_START
56 jalr a3 /* callback to firmware */
57 or sp, t0, t1 /* delay slot */
58 move sp, s0 /* restore sp */
59
60 REG_L t8, CALLFRAME_SIZ+1*SZREG(sp)
61 REG_L gp, CALLFRAME_SIZ+0*SZREG(sp)
62 REG_L s0, CALLFRAME_S0(sp)
63 REG_L ra, CALLFRAME_RA(sp)
64 jr ra
65 PTR_ADDU sp, sp, (CALLFRAME_SIZ+2*SZREG) /* delay slot */
66 END(rmixlfw_wakeup_cpu)
67
68 /*
69 * cpu_wakeup_trampoline
70 */
71 NESTED(cpu_wakeup_trampoline, CALLFRAME_SIZ, ra)
72 j .
73 nop
74 END(cpu_wakeup_trampoline)
75
76 .set pop
77