1 /* ********************************************************************* 2 * BCM1280/BCM1480 Board Support Package 3 * 4 * Memory Controller constants File: bcm1480_mc.h 5 * 6 * This module contains constants and macros useful for 7 * programming the memory controller. 8 * 9 * BCM1400 specification level: 1280-UM100-D1 (11/14/03 Review Copy) 10 * 11 ********************************************************************* 12 * 13 * Copyright 2000,2001,2002,2003,2004 14 * Broadcom Corporation. All rights reserved. 15 * 16 * This software is furnished under license and may be used and 17 * copied only in accordance with the following terms and 18 * conditions. Subject to these conditions, you may download, 19 * copy, install, use, modify and distribute modified or unmodified 20 * copies of this software in source and/or binary form. No title 21 * or ownership is transferred hereby. 22 * 23 * 1) Any source code used, modified or distributed must reproduce 24 * and retain this copyright notice and list of conditions 25 * as they appear in the source file. 26 * 27 * 2) No right is granted to use any trade name, trademark, or 28 * logo of Broadcom Corporation. The "Broadcom Corporation" 29 * name may not be used to endorse or promote products derived 30 * from this software without the prior written permission of 31 * Broadcom Corporation. 32 * 33 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 34 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 35 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 36 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 37 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 38 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 39 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 40 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 41 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 42 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 43 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 44 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 45 * THE POSSIBILITY OF SUCH DAMAGE. 46 ********************************************************************* */ 47 48 49 #ifndef _BCM1480_MC_H 50 #define _BCM1480_MC_H 51 52 #include "sb1250_defs.h" 53 54 /* 55 * Memory Channel Configuration Register (Table 81) 56 */ 57 58 #define S_BCM1480_MC_INTLV0 0 59 #define M_BCM1480_MC_INTLV0 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV0) 60 #define V_BCM1480_MC_INTLV0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV0) 61 #define G_BCM1480_MC_INTLV0(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV0,M_BCM1480_MC_INTLV0) 62 #define V_BCM1480_MC_INTLV0_DEFAULT V_BCM1480_MC_INTLV0(0) 63 64 #define S_BCM1480_MC_INTLV1 8 65 #define M_BCM1480_MC_INTLV1 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV1) 66 #define V_BCM1480_MC_INTLV1(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV1) 67 #define G_BCM1480_MC_INTLV1(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV1,M_BCM1480_MC_INTLV1) 68 #define V_BCM1480_MC_INTLV1_DEFAULT V_BCM1480_MC_INTLV1(0) 69 70 #define S_BCM1480_MC_INTLV2 16 71 #define M_BCM1480_MC_INTLV2 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV2) 72 #define V_BCM1480_MC_INTLV2(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV2) 73 #define G_BCM1480_MC_INTLV2(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV2,M_BCM1480_MC_INTLV2) 74 #define V_BCM1480_MC_INTLV2_DEFAULT V_BCM1480_MC_INTLV2(0) 75 76 #define S_BCM1480_MC_CS_MODE 32 77 #define M_BCM1480_MC_CS_MODE _SB_MAKEMASK(8,S_BCM1480_MC_CS_MODE) 78 #define V_BCM1480_MC_CS_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS_MODE) 79 #define G_BCM1480_MC_CS_MODE(x) _SB_GETVALUE(x,S_BCM1480_MC_CS_MODE,M_BCM1480_MC_CS_MODE) 80 #define V_BCM1480_MC_CS_MODE_DEFAULT V_BCM1480_MC_CS_MODE(0) 81 82 #define V_BCM1480_MC_CONFIG_DEFAULT (V_BCM1480_MC_INTLV0_DEFAULT | \ 83 V_BCM1480_MC_INTLV1_DEFAULT | \ 84 V_BCM1480_MC_INTLV2_DEFAULT | \ 85 V_BCM1480_MC_CS_MODE_DEFAULT) 86 87 #define K_BCM1480_MC_CS01_MODE 0x03 88 #define K_BCM1480_MC_CS02_MODE 0x05 89 #define K_BCM1480_MC_CS0123_MODE 0x0F 90 #define K_BCM1480_MC_CS0246_MODE 0x55 91 #define K_BCM1480_MC_CS0145_MODE 0x33 92 #define K_BCM1480_MC_CS0167_MODE 0xC3 93 #define K_BCM1480_MC_CSFULL_MODE 0xFF 94 95 /* 96 * Chip Select Start Address Register (Table 82) 97 */ 98 99 #define S_BCM1480_MC_CS0_START 0 100 #define M_BCM1480_MC_CS0_START _SB_MAKEMASK(12,S_BCM1480_MC_CS0_START) 101 #define V_BCM1480_MC_CS0_START(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS0_START) 102 #define G_BCM1480_MC_CS0_START(x) _SB_GETVALUE(x,S_BCM1480_MC_CS0_START,M_BCM1480_MC_CS0_START) 103 104 #define S_BCM1480_MC_CS1_START 16 105 #define M_BCM1480_MC_CS1_START _SB_MAKEMASK(12,S_BCM1480_MC_CS1_START) 106 #define V_BCM1480_MC_CS1_START(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS1_START) 107 #define G_BCM1480_MC_CS1_START(x) _SB_GETVALUE(x,S_BCM1480_MC_CS1_START,M_BCM1480_MC_CS1_START) 108 109 #define S_BCM1480_MC_CS2_START 32 110 #define M_BCM1480_MC_CS2_START _SB_MAKEMASK(12,S_BCM1480_MC_CS2_START) 111 #define V_BCM1480_MC_CS2_START(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS2_START) 112 #define G_BCM1480_MC_CS2_START(x) _SB_GETVALUE(x,S_BCM1480_MC_CS2_START,M_BCM1480_MC_CS2_START) 113 114 #define S_BCM1480_MC_CS3_START 48 115 #define M_BCM1480_MC_CS3_START _SB_MAKEMASK(12,S_BCM1480_MC_CS3_START) 116 #define V_BCM1480_MC_CS3_START(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS3_START) 117 #define G_BCM1480_MC_CS3_START(x) _SB_GETVALUE(x,S_BCM1480_MC_CS3_START,M_BCM1480_MC_CS3_START) 118 119 /* 120 * Chip Select End Address Register (Table 83) 121 */ 122 123 #define S_BCM1480_MC_CS0_END 0 124 #define M_BCM1480_MC_CS0_END _SB_MAKEMASK(12,S_BCM1480_MC_CS0_END) 125 #define V_BCM1480_MC_CS0_END(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS0_END) 126 #define G_BCM1480_MC_CS0_END(x) _SB_GETVALUE(x,S_BCM1480_MC_CS0_END,M_BCM1480_MC_CS0_END) 127 128 #define S_BCM1480_MC_CS1_END 16 129 #define M_BCM1480_MC_CS1_END _SB_MAKEMASK(12,S_BCM1480_MC_CS1_END) 130 #define V_BCM1480_MC_CS1_END(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS1_END) 131 #define G_BCM1480_MC_CS1_END(x) _SB_GETVALUE(x,S_BCM1480_MC_CS1_END,M_BCM1480_MC_CS1_END) 132 133 #define S_BCM1480_MC_CS2_END 32 134 #define M_BCM1480_MC_CS2_END _SB_MAKEMASK(12,S_BCM1480_MC_CS2_END) 135 #define V_BCM1480_MC_CS2_END(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS2_END) 136 #define G_BCM1480_MC_CS2_END(x) _SB_GETVALUE(x,S_BCM1480_MC_CS2_END,M_BCM1480_MC_CS2_END) 137 138 #define S_BCM1480_MC_CS3_END 48 139 #define M_BCM1480_MC_CS3_END _SB_MAKEMASK(12,S_BCM1480_MC_CS3_END) 140 #define V_BCM1480_MC_CS3_END(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS3_END) 141 #define G_BCM1480_MC_CS3_END(x) _SB_GETVALUE(x,S_BCM1480_MC_CS3_END,M_BCM1480_MC_CS3_END) 142 143 /* 144 * Row Address Bit Select Register 0 (Table 84) 145 */ 146 147 #define S_BCM1480_MC_ROW00 0 148 #define M_BCM1480_MC_ROW00 _SB_MAKEMASK(6,S_BCM1480_MC_ROW00) 149 #define V_BCM1480_MC_ROW00(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW00) 150 #define G_BCM1480_MC_ROW00(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW00,M_BCM1480_MC_ROW00) 151 152 #define S_BCM1480_MC_ROW01 8 153 #define M_BCM1480_MC_ROW01 _SB_MAKEMASK(6,S_BCM1480_MC_ROW01) 154 #define V_BCM1480_MC_ROW01(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW01) 155 #define G_BCM1480_MC_ROW01(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW01,M_BCM1480_MC_ROW01) 156 157 #define S_BCM1480_MC_ROW02 16 158 #define M_BCM1480_MC_ROW02 _SB_MAKEMASK(6,S_BCM1480_MC_ROW02) 159 #define V_BCM1480_MC_ROW02(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW02) 160 #define G_BCM1480_MC_ROW02(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW02,M_BCM1480_MC_ROW02) 161 162 #define S_BCM1480_MC_ROW03 24 163 #define M_BCM1480_MC_ROW03 _SB_MAKEMASK(6,S_BCM1480_MC_ROW03) 164 #define V_BCM1480_MC_ROW03(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW03) 165 #define G_BCM1480_MC_ROW03(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW03,M_BCM1480_MC_ROW03) 166 167 #define S_BCM1480_MC_ROW04 32 168 #define M_BCM1480_MC_ROW04 _SB_MAKEMASK(6,S_BCM1480_MC_ROW04) 169 #define V_BCM1480_MC_ROW04(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW04) 170 #define G_BCM1480_MC_ROW04(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW04,M_BCM1480_MC_ROW04) 171 172 #define S_BCM1480_MC_ROW05 40 173 #define M_BCM1480_MC_ROW05 _SB_MAKEMASK(6,S_BCM1480_MC_ROW05) 174 #define V_BCM1480_MC_ROW05(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW05) 175 #define G_BCM1480_MC_ROW05(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW05,M_BCM1480_MC_ROW05) 176 177 #define S_BCM1480_MC_ROW06 48 178 #define M_BCM1480_MC_ROW06 _SB_MAKEMASK(6,S_BCM1480_MC_ROW06) 179 #define V_BCM1480_MC_ROW06(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW06) 180 #define G_BCM1480_MC_ROW06(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW06,M_BCM1480_MC_ROW06) 181 182 #define S_BCM1480_MC_ROW07 56 183 #define M_BCM1480_MC_ROW07 _SB_MAKEMASK(6,S_BCM1480_MC_ROW07) 184 #define V_BCM1480_MC_ROW07(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW07) 185 #define G_BCM1480_MC_ROW07(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW07,M_BCM1480_MC_ROW07) 186 187 /* 188 * Row Address Bit Select Register 1 (Table 85) 189 */ 190 191 #define S_BCM1480_MC_ROW08 0 192 #define M_BCM1480_MC_ROW08 _SB_MAKEMASK(6,S_BCM1480_MC_ROW08) 193 #define V_BCM1480_MC_ROW08(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW08) 194 #define G_BCM1480_MC_ROW08(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW08,M_BCM1480_MC_ROW08) 195 196 #define S_BCM1480_MC_ROW09 8 197 #define M_BCM1480_MC_ROW09 _SB_MAKEMASK(6,S_BCM1480_MC_ROW09) 198 #define V_BCM1480_MC_ROW09(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW09) 199 #define G_BCM1480_MC_ROW09(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW09,M_BCM1480_MC_ROW09) 200 201 #define S_BCM1480_MC_ROW10 16 202 #define M_BCM1480_MC_ROW10 _SB_MAKEMASK(6,S_BCM1480_MC_ROW10) 203 #define V_BCM1480_MC_ROW10(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW10) 204 #define G_BCM1480_MC_ROW10(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW10,M_BCM1480_MC_ROW10) 205 206 #define S_BCM1480_MC_ROW11 24 207 #define M_BCM1480_MC_ROW11 _SB_MAKEMASK(6,S_BCM1480_MC_ROW11) 208 #define V_BCM1480_MC_ROW11(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW11) 209 #define G_BCM1480_MC_ROW11(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW11,M_BCM1480_MC_ROW11) 210 211 #define S_BCM1480_MC_ROW12 32 212 #define M_BCM1480_MC_ROW12 _SB_MAKEMASK(6,S_BCM1480_MC_ROW12) 213 #define V_BCM1480_MC_ROW12(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW12) 214 #define G_BCM1480_MC_ROW12(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW12,M_BCM1480_MC_ROW12) 215 216 #define S_BCM1480_MC_ROW13 40 217 #define M_BCM1480_MC_ROW13 _SB_MAKEMASK(6,S_BCM1480_MC_ROW13) 218 #define V_BCM1480_MC_ROW13(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW13) 219 #define G_BCM1480_MC_ROW13(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW13,M_BCM1480_MC_ROW13) 220 221 #define S_BCM1480_MC_ROW14 48 222 #define M_BCM1480_MC_ROW14 _SB_MAKEMASK(6,S_BCM1480_MC_ROW14) 223 #define V_BCM1480_MC_ROW14(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW14) 224 #define G_BCM1480_MC_ROW14(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW14,M_BCM1480_MC_ROW14) 225 226 #define K_BCM1480_MC_ROWX_BIT_SPACING 8 227 228 /* 229 * Column Address Bit Select Register 0 (Table 86) 230 */ 231 232 #define S_BCM1480_MC_COL00 0 233 #define M_BCM1480_MC_COL00 _SB_MAKEMASK(6,S_BCM1480_MC_COL00) 234 #define V_BCM1480_MC_COL00(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL00) 235 #define G_BCM1480_MC_COL00(x) _SB_GETVALUE(x,S_BCM1480_MC_COL00,M_BCM1480_MC_COL00) 236 237 #define S_BCM1480_MC_COL01 8 238 #define M_BCM1480_MC_COL01 _SB_MAKEMASK(6,S_BCM1480_MC_COL01) 239 #define V_BCM1480_MC_COL01(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL01) 240 #define G_BCM1480_MC_COL01(x) _SB_GETVALUE(x,S_BCM1480_MC_COL01,M_BCM1480_MC_COL01) 241 242 #define S_BCM1480_MC_COL02 16 243 #define M_BCM1480_MC_COL02 _SB_MAKEMASK(6,S_BCM1480_MC_COL02) 244 #define V_BCM1480_MC_COL02(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL02) 245 #define G_BCM1480_MC_COL02(x) _SB_GETVALUE(x,S_BCM1480_MC_COL02,M_BCM1480_MC_COL02) 246 247 #define S_BCM1480_MC_COL03 24 248 #define M_BCM1480_MC_COL03 _SB_MAKEMASK(6,S_BCM1480_MC_COL03) 249 #define V_BCM1480_MC_COL03(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL03) 250 #define G_BCM1480_MC_COL03(x) _SB_GETVALUE(x,S_BCM1480_MC_COL03,M_BCM1480_MC_COL03) 251 252 #define S_BCM1480_MC_COL04 32 253 #define M_BCM1480_MC_COL04 _SB_MAKEMASK(6,S_BCM1480_MC_COL04) 254 #define V_BCM1480_MC_COL04(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL04) 255 #define G_BCM1480_MC_COL04(x) _SB_GETVALUE(x,S_BCM1480_MC_COL04,M_BCM1480_MC_COL04) 256 257 #define S_BCM1480_MC_COL05 40 258 #define M_BCM1480_MC_COL05 _SB_MAKEMASK(6,S_BCM1480_MC_COL05) 259 #define V_BCM1480_MC_COL05(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL05) 260 #define G_BCM1480_MC_COL05(x) _SB_GETVALUE(x,S_BCM1480_MC_COL05,M_BCM1480_MC_COL05) 261 262 #define S_BCM1480_MC_COL06 48 263 #define M_BCM1480_MC_COL06 _SB_MAKEMASK(6,S_BCM1480_MC_COL06) 264 #define V_BCM1480_MC_COL06(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL06) 265 #define G_BCM1480_MC_COL06(x) _SB_GETVALUE(x,S_BCM1480_MC_COL06,M_BCM1480_MC_COL06) 266 267 #define S_BCM1480_MC_COL07 56 268 #define M_BCM1480_MC_COL07 _SB_MAKEMASK(6,S_BCM1480_MC_COL07) 269 #define V_BCM1480_MC_COL07(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL07) 270 #define G_BCM1480_MC_COL07(x) _SB_GETVALUE(x,S_BCM1480_MC_COL07,M_BCM1480_MC_COL07) 271 272 /* 273 * Column Address Bit Select Register 1 (Table 87) 274 */ 275 276 #define S_BCM1480_MC_COL08 0 277 #define M_BCM1480_MC_COL08 _SB_MAKEMASK(6,S_BCM1480_MC_COL08) 278 #define V_BCM1480_MC_COL08(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL08) 279 #define G_BCM1480_MC_COL08(x) _SB_GETVALUE(x,S_BCM1480_MC_COL08,M_BCM1480_MC_COL08) 280 281 #define S_BCM1480_MC_COL09 8 282 #define M_BCM1480_MC_COL09 _SB_MAKEMASK(6,S_BCM1480_MC_COL09) 283 #define V_BCM1480_MC_COL09(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL09) 284 #define G_BCM1480_MC_COL09(x) _SB_GETVALUE(x,S_BCM1480_MC_COL09,M_BCM1480_MC_COL09) 285 286 #define S_BCM1480_MC_COL10 16 /* not a valid position, must be prog as 0 */ 287 288 #define S_BCM1480_MC_COL11 24 289 #define M_BCM1480_MC_COL11 _SB_MAKEMASK(6,S_BCM1480_MC_COL11) 290 #define V_BCM1480_MC_COL11(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL11) 291 #define G_BCM1480_MC_COL11(x) _SB_GETVALUE(x,S_BCM1480_MC_COL11,M_BCM1480_MC_COL11) 292 293 #define S_BCM1480_MC_COL12 32 294 #define M_BCM1480_MC_COL12 _SB_MAKEMASK(6,S_BCM1480_MC_COL12) 295 #define V_BCM1480_MC_COL12(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL12) 296 #define G_BCM1480_MC_COL12(x) _SB_GETVALUE(x,S_BCM1480_MC_COL12,M_BCM1480_MC_COL12) 297 298 #define S_BCM1480_MC_COL13 40 299 #define M_BCM1480_MC_COL13 _SB_MAKEMASK(6,S_BCM1480_MC_COL13) 300 #define V_BCM1480_MC_COL13(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL13) 301 #define G_BCM1480_MC_COL13(x) _SB_GETVALUE(x,S_BCM1480_MC_COL13,M_BCM1480_MC_COL13) 302 303 #define S_BCM1480_MC_COL14 48 304 #define M_BCM1480_MC_COL14 _SB_MAKEMASK(6,S_BCM1480_MC_COL14) 305 #define V_BCM1480_MC_COL14(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL14) 306 #define G_BCM1480_MC_COL14(x) _SB_GETVALUE(x,S_BCM1480_MC_COL14,M_BCM1480_MC_COL14) 307 308 #define K_BCM1480_MC_COLX_BIT_SPACING 8 309 310 /* 311 * CS0 and CS1 Bank Address Bit Select Register (Table 88) 312 */ 313 314 #define S_BCM1480_MC_CS01_BANK0 0 315 #define M_BCM1480_MC_CS01_BANK0 _SB_MAKEMASK(6,S_BCM1480_MC_CS01_BANK0) 316 #define V_BCM1480_MC_CS01_BANK0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS01_BANK0) 317 #define G_BCM1480_MC_CS01_BANK0(x) _SB_GETVALUE(x,S_BCM1480_MC_CS01_BANK0,M_BCM1480_MC_CS01_BANK0) 318 319 #define S_BCM1480_MC_CS01_BANK1 8 320 #define M_BCM1480_MC_CS01_BANK1 _SB_MAKEMASK(6,S_BCM1480_MC_CS01_BANK1) 321 #define V_BCM1480_MC_CS01_BANK1(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS01_BANK1) 322 #define G_BCM1480_MC_CS01_BANK1(x) _SB_GETVALUE(x,S_BCM1480_MC_CS01_BANK1,M_BCM1480_MC_CS01_BANK1) 323 324 #define S_BCM1480_MC_CS01_BANK2 16 325 #define M_BCM1480_MC_CS01_BANK2 _SB_MAKEMASK(6,S_BCM1480_MC_CS01_BANK2) 326 #define V_BCM1480_MC_CS01_BANK2(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS01_BANK2) 327 #define G_BCM1480_MC_CS01_BANK2(x) _SB_GETVALUE(x,S_BCM1480_MC_CS01_BANK2,M_BCM1480_MC_CS01_BANK2) 328 329 /* 330 * CS2 and CS3 Bank Address Bit Select Register (Table 89) 331 */ 332 333 #define S_BCM1480_MC_CS23_BANK0 0 334 #define M_BCM1480_MC_CS23_BANK0 _SB_MAKEMASK(6,S_BCM1480_MC_CS23_BANK0) 335 #define V_BCM1480_MC_CS23_BANK0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS23_BANK0) 336 #define G_BCM1480_MC_CS23_BANK0(x) _SB_GETVALUE(x,S_BCM1480_MC_CS23_BANK0,M_BCM1480_MC_CS23_BANK0) 337 338 #define S_BCM1480_MC_CS23_BANK1 8 339 #define M_BCM1480_MC_CS23_BANK1 _SB_MAKEMASK(6,S_BCM1480_MC_CS23_BANK1) 340 #define V_BCM1480_MC_CS23_BANK1(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS23_BANK1) 341 #define G_BCM1480_MC_CS23_BANK1(x) _SB_GETVALUE(x,S_BCM1480_MC_CS23_BANK1,M_BCM1480_MC_CS23_BANK1) 342 343 #define S_BCM1480_MC_CS23_BANK2 16 344 #define M_BCM1480_MC_CS23_BANK2 _SB_MAKEMASK(6,S_BCM1480_MC_CS23_BANK2) 345 #define V_BCM1480_MC_CS23_BANK2(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS23_BANK2) 346 #define G_BCM1480_MC_CS23_BANK2(x) _SB_GETVALUE(x,S_BCM1480_MC_CS23_BANK2,M_BCM1480_MC_CS23_BANK2) 347 348 #define K_BCM1480_MC_CSXX_BANKX_BIT_SPACING 8 349 350 /* 351 * DRAM Command Register (Table 90) 352 */ 353 354 #define S_BCM1480_MC_COMMAND 0 355 #define M_BCM1480_MC_COMMAND _SB_MAKEMASK(4,S_BCM1480_MC_COMMAND) 356 #define V_BCM1480_MC_COMMAND(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COMMAND) 357 #define G_BCM1480_MC_COMMAND(x) _SB_GETVALUE(x,S_BCM1480_MC_COMMAND,M_BCM1480_MC_COMMAND) 358 359 #define K_BCM1480_MC_COMMAND_EMRS 0 360 #define K_BCM1480_MC_COMMAND_MRS 1 361 #define K_BCM1480_MC_COMMAND_PRE 2 362 #define K_BCM1480_MC_COMMAND_AR 3 363 #define K_BCM1480_MC_COMMAND_SETRFSH 4 364 #define K_BCM1480_MC_COMMAND_CLRRFSH 5 365 #define K_BCM1480_MC_COMMAND_SETPWRDN 6 366 #define K_BCM1480_MC_COMMAND_CLRPWRDN 7 367 368 #if SIBYTE_HDR_FEATURE(1480, PASS2) 369 #define K_BCM1480_MC_COMMAND_EMRS2 8 370 #define K_BCM1480_MC_COMMAND_EMRS3 9 371 #define K_BCM1480_MC_COMMAND_ENABLE_MCLK 10 372 #define K_BCM1480_MC_COMMAND_DISABLE_MCLK 11 373 #endif 374 375 #define V_BCM1480_MC_COMMAND_EMRS V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS) 376 #define V_BCM1480_MC_COMMAND_MRS V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_MRS) 377 #define V_BCM1480_MC_COMMAND_PRE V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_PRE) 378 #define V_BCM1480_MC_COMMAND_AR V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_AR) 379 #define V_BCM1480_MC_COMMAND_SETRFSH V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_SETRFSH) 380 #define V_BCM1480_MC_COMMAND_CLRRFSH V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_CLRRFSH) 381 #define V_BCM1480_MC_COMMAND_SETPWRDN V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_SETPWRDN) 382 #define V_BCM1480_MC_COMMAND_CLRPWRDN V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_CLRPWRDN) 383 384 #if SIBYTE_HDR_FEATURE(1480, PASS2) 385 #define V_BCM1480_MC_COMMAND_EMRS2 V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS2) 386 #define V_BCM1480_MC_COMMAND_EMRS3 V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS3) 387 #define V_BCM1480_MC_COMMAND_ENABLE_MCLK V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_ENABLE_MCLK) 388 #define V_BCM1480_MC_COMMAND_DISABLE_MCLK V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_DISABLE_MCLK) 389 #endif 390 391 #define S_BCM1480_MC_CS0 4 392 #define M_BCM1480_MC_CS0 _SB_MAKEMASK1(4) 393 #define M_BCM1480_MC_CS1 _SB_MAKEMASK1(5) 394 #define M_BCM1480_MC_CS2 _SB_MAKEMASK1(6) 395 #define M_BCM1480_MC_CS3 _SB_MAKEMASK1(7) 396 #define M_BCM1480_MC_CS4 _SB_MAKEMASK1(8) 397 #define M_BCM1480_MC_CS5 _SB_MAKEMASK1(9) 398 #define M_BCM1480_MC_CS6 _SB_MAKEMASK1(10) 399 #define M_BCM1480_MC_CS7 _SB_MAKEMASK1(11) 400 401 #define M_BCM1480_MC_CS _SB_MAKEMASK(8,S_BCM1480_MC_CS0) 402 #define V_BCM1480_MC_CS(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS0) 403 #define G_BCM1480_MC_CS(x) _SB_GETVALUE(x,S_BCM1480_MC_CS0,M_BCM1480_MC_CS0) 404 405 #define M_BCM1480_MC_CMD_ACTIVE _SB_MAKEMASK1(16) 406 407 /* 408 * DRAM Mode Register (Table 91) 409 */ 410 411 #define S_BCM1480_MC_EMODE 0 412 #define M_BCM1480_MC_EMODE _SB_MAKEMASK(15,S_BCM1480_MC_EMODE) 413 #define V_BCM1480_MC_EMODE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_EMODE) 414 #define G_BCM1480_MC_EMODE(x) _SB_GETVALUE(x,S_BCM1480_MC_EMODE,M_BCM1480_MC_EMODE) 415 #define V_BCM1480_MC_EMODE_DEFAULT V_BCM1480_MC_EMODE(0) 416 417 #define S_BCM1480_MC_MODE 16 418 #define M_BCM1480_MC_MODE _SB_MAKEMASK(15,S_BCM1480_MC_MODE) 419 #define V_BCM1480_MC_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_MODE) 420 #define G_BCM1480_MC_MODE(x) _SB_GETVALUE(x,S_BCM1480_MC_MODE,M_BCM1480_MC_MODE) 421 #define V_BCM1480_MC_MODE_DEFAULT V_BCM1480_MC_MODE(0) 422 423 #define S_BCM1480_MC_DRAM_TYPE 32 424 #define M_BCM1480_MC_DRAM_TYPE _SB_MAKEMASK(4,S_BCM1480_MC_DRAM_TYPE) 425 #define V_BCM1480_MC_DRAM_TYPE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DRAM_TYPE) 426 #define G_BCM1480_MC_DRAM_TYPE(x) _SB_GETVALUE(x,S_BCM1480_MC_DRAM_TYPE,M_BCM1480_MC_DRAM_TYPE) 427 428 #define K_BCM1480_MC_DRAM_TYPE_JEDEC 0 429 #define K_BCM1480_MC_DRAM_TYPE_FCRAM 1 430 431 #if SIBYTE_HDR_FEATURE(1480, PASS2) 432 #define K_BCM1480_MC_DRAM_TYPE_DDR2 2 433 #endif 434 435 #define K_BCM1480_MC_DRAM_TYPE_DDR2_PASS1 0 436 437 #define V_BCM1480_MC_DRAM_TYPE_JEDEC V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_JEDEC) 438 #define V_BCM1480_MC_DRAM_TYPE_FCRAM V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_FCRAM) 439 440 #if SIBYTE_HDR_FEATURE(1480, PASS2) 441 #define V_BCM1480_MC_DRAM_TYPE_DDR2 V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_DDR2) 442 #endif 443 444 #define M_BCM1480_MC_GANGED _SB_MAKEMASK1(36) 445 #define M_BCM1480_MC_BY9_INTF _SB_MAKEMASK1(37) 446 #define M_BCM1480_MC_FORCE_ECC64 _SB_MAKEMASK1(38) 447 #define M_BCM1480_MC_ECC_DISABLE _SB_MAKEMASK1(39) 448 449 #define S_BCM1480_MC_PG_POLICY 40 450 #define M_BCM1480_MC_PG_POLICY _SB_MAKEMASK(2,S_BCM1480_MC_PG_POLICY) 451 #define V_BCM1480_MC_PG_POLICY(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PG_POLICY) 452 #define G_BCM1480_MC_PG_POLICY(x) _SB_GETVALUE(x,S_BCM1480_MC_PG_POLICY,M_BCM1480_MC_PG_POLICY) 453 454 #define K_BCM1480_MC_PG_POLICY_CLOSED 0 455 #define K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK 1 456 457 #define V_BCM1480_MC_PG_POLICY_CLOSED V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CLOSED) 458 #define V_BCM1480_MC_PG_POLICY_CAS_TIME_CHK V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK) 459 460 #if SIBYTE_HDR_FEATURE(1480, PASS2) 461 #define M_BCM1480_MC_2T_CMD _SB_MAKEMASK1(42) 462 #define M_BCM1480_MC_ECC_COR_DIS _SB_MAKEMASK1(43) 463 #endif 464 465 #define V_BCM1480_MC_DRAMMODE_DEFAULT V_BCM1480_MC_EMODE_DEFAULT | V_BCM1480_MC_MODE_DEFAULT | V_BCM1480_MC_DRAM_TYPE_JEDEC | \ 466 V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK) 467 468 /* 469 * Memory Clock Configuration Register (Table 92) 470 */ 471 472 #define S_BCM1480_MC_CLK_RATIO 0 473 #define M_BCM1480_MC_CLK_RATIO _SB_MAKEMASK(6,S_BCM1480_MC_CLK_RATIO) 474 #define V_BCM1480_MC_CLK_RATIO(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CLK_RATIO) 475 #define G_BCM1480_MC_CLK_RATIO(x) _SB_GETVALUE(x,S_BCM1480_MC_CLK_RATIO,M_BCM1480_MC_CLK_RATIO) 476 477 #define V_BCM1480_MC_CLK_RATIO_DEFAULT V_BCM1480_MC_CLK_RATIO(10) 478 479 #define S_BCM1480_MC_REF_RATE 8 480 #define M_BCM1480_MC_REF_RATE _SB_MAKEMASK(8,S_BCM1480_MC_REF_RATE) 481 #define V_BCM1480_MC_REF_RATE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_REF_RATE) 482 #define G_BCM1480_MC_REF_RATE(x) _SB_GETVALUE(x,S_BCM1480_MC_REF_RATE,M_BCM1480_MC_REF_RATE) 483 484 #define K_BCM1480_MC_REF_RATE_100MHz 0x31 485 #define K_BCM1480_MC_REF_RATE_200MHz 0x62 486 #define K_BCM1480_MC_REF_RATE_400MHz 0xC4 487 488 #define V_BCM1480_MC_REF_RATE_100MHz V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_100MHz) 489 #define V_BCM1480_MC_REF_RATE_200MHz V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_200MHz) 490 #define V_BCM1480_MC_REF_RATE_400MHz V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_400MHz) 491 #define V_BCM1480_MC_REF_RATE_DEFAULT V_BCM1480_MC_REF_RATE_400MHz 492 493 #if SIBYTE_HDR_FEATURE(1480, PASS2) 494 #define M_BCM1480_MC_AUTO_REF_DIS _SB_MAKEMASK1(16) 495 #endif 496 497 /* 498 * ODT Register (Table 99) 499 */ 500 501 #if SIBYTE_HDR_FEATURE(1480, PASS2) 502 #define M_BCM1480_MC_RD_ODT0_CS0 _SB_MAKEMASK1(0) 503 #define M_BCM1480_MC_RD_ODT0_CS2 _SB_MAKEMASK1(1) 504 #define M_BCM1480_MC_RD_ODT0_CS4 _SB_MAKEMASK1(2) 505 #define M_BCM1480_MC_RD_ODT0_CS6 _SB_MAKEMASK1(3) 506 #define M_BCM1480_MC_WR_ODT0_CS0 _SB_MAKEMASK1(4) 507 #define M_BCM1480_MC_WR_ODT0_CS2 _SB_MAKEMASK1(5) 508 #define M_BCM1480_MC_WR_ODT0_CS4 _SB_MAKEMASK1(6) 509 #define M_BCM1480_MC_WR_ODT0_CS6 _SB_MAKEMASK1(7) 510 #define M_BCM1480_MC_RD_ODT2_CS0 _SB_MAKEMASK1(8) 511 #define M_BCM1480_MC_RD_ODT2_CS2 _SB_MAKEMASK1(9) 512 #define M_BCM1480_MC_RD_ODT2_CS4 _SB_MAKEMASK1(10) 513 #define M_BCM1480_MC_RD_ODT2_CS6 _SB_MAKEMASK1(11) 514 #define M_BCM1480_MC_WR_ODT2_CS0 _SB_MAKEMASK1(12) 515 #define M_BCM1480_MC_WR_ODT2_CS2 _SB_MAKEMASK1(13) 516 #define M_BCM1480_MC_WR_ODT2_CS4 _SB_MAKEMASK1(14) 517 #define M_BCM1480_MC_WR_ODT2_CS6 _SB_MAKEMASK1(15) 518 #define M_BCM1480_MC_RD_ODT4_CS0 _SB_MAKEMASK1(16) 519 #define M_BCM1480_MC_RD_ODT4_CS2 _SB_MAKEMASK1(17) 520 #define M_BCM1480_MC_RD_ODT4_CS4 _SB_MAKEMASK1(18) 521 #define M_BCM1480_MC_RD_ODT4_CS6 _SB_MAKEMASK1(19) 522 #define M_BCM1480_MC_WR_ODT4_CS0 _SB_MAKEMASK1(20) 523 #define M_BCM1480_MC_WR_ODT4_CS2 _SB_MAKEMASK1(21) 524 #define M_BCM1480_MC_WR_ODT4_CS4 _SB_MAKEMASK1(22) 525 #define M_BCM1480_MC_WR_ODT4_CS6 _SB_MAKEMASK1(23) 526 #define M_BCM1480_MC_RD_ODT6_CS0 _SB_MAKEMASK1(24) 527 #define M_BCM1480_MC_RD_ODT6_CS2 _SB_MAKEMASK1(25) 528 #define M_BCM1480_MC_RD_ODT6_CS4 _SB_MAKEMASK1(26) 529 #define M_BCM1480_MC_RD_ODT6_CS6 _SB_MAKEMASK1(27) 530 #define M_BCM1480_MC_WR_ODT6_CS0 _SB_MAKEMASK1(28) 531 #define M_BCM1480_MC_WR_ODT6_CS2 _SB_MAKEMASK1(29) 532 #define M_BCM1480_MC_WR_ODT6_CS4 _SB_MAKEMASK1(30) 533 #define M_BCM1480_MC_WR_ODT6_CS6 _SB_MAKEMASK1(31) 534 535 #define M_BCM1480_MC_CS_ODD_ODT_EN _SB_MAKEMASK1(32) 536 537 #define S_BCM1480_MC_ODT0 0 538 #define M_BCM1480_MC_ODT0 _SB_MAKEMASK(8,S_BCM1480_MC_ODT0) 539 #define V_BCM1480_MC_ODT0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ODT0) 540 541 #define S_BCM1480_MC_ODT2 8 542 #define M_BCM1480_MC_ODT2 _SB_MAKEMASK(8,S_BCM1480_MC_ODT2) 543 #define V_BCM1480_MC_ODT2(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ODT2) 544 545 #define S_BCM1480_MC_ODT4 16 546 #define M_BCM1480_MC_ODT4 _SB_MAKEMASK(8,S_BCM1480_MC_ODT4) 547 #define V_BCM1480_MC_ODT4(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ODT4) 548 549 #define S_BCM1480_MC_ODT6 24 550 #define M_BCM1480_MC_ODT6 _SB_MAKEMASK(8,S_BCM1480_MC_ODT6) 551 #define V_BCM1480_MC_ODT6(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ODT6) 552 #endif 553 554 /* 555 * Memory DLL Configuration Register (Table 93) 556 */ 557 558 #define S_BCM1480_MC_ADDR_COARSE_ADJ 0 559 #define M_BCM1480_MC_ADDR_COARSE_ADJ _SB_MAKEMASK(6,S_BCM1480_MC_ADDR_COARSE_ADJ) 560 #define V_BCM1480_MC_ADDR_COARSE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ADDR_COARSE_ADJ) 561 #define G_BCM1480_MC_ADDR_COARSE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_ADDR_COARSE_ADJ,M_BCM1480_MC_ADDR_COARSE_ADJ) 562 #define V_BCM1480_MC_ADDR_COARSE_ADJ_DEFAULT V_BCM1480_MC_ADDR_COARSE_ADJ(0x0) 563 564 #if SIBYTE_HDR_FEATURE(1480, PASS2) 565 #define S_BCM1480_MC_ADDR_FREQ_RANGE 8 566 #define M_BCM1480_MC_ADDR_FREQ_RANGE _SB_MAKEMASK(4,S_BCM1480_MC_ADDR_FREQ_RANGE) 567 #define V_BCM1480_MC_ADDR_FREQ_RANGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ADDR_FREQ_RANGE) 568 #define G_BCM1480_MC_ADDR_FREQ_RANGE(x) _SB_GETVALUE(x,S_BCM1480_MC_ADDR_FREQ_RANGE,M_BCM1480_MC_ADDR_FREQ_RANGE) 569 #define V_BCM1480_MC_ADDR_FREQ_RANGE_DEFAULT V_BCM1480_MC_ADDR_FREQ_RANGE(0x4) 570 #endif 571 572 #define S_BCM1480_MC_ADDR_FINE_ADJ 8 573 #define M_BCM1480_MC_ADDR_FINE_ADJ _SB_MAKEMASK(4,S_BCM1480_MC_ADDR_FINE_ADJ) 574 #define V_BCM1480_MC_ADDR_FINE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ADDR_FINE_ADJ) 575 #define G_BCM1480_MC_ADDR_FINE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_ADDR_FINE_ADJ,M_BCM1480_MC_ADDR_FINE_ADJ) 576 #define V_BCM1480_MC_ADDR_FINE_ADJ_DEFAULT V_BCM1480_MC_ADDR_FINE_ADJ(0x8) 577 578 #define S_BCM1480_MC_DQI_COARSE_ADJ 16 579 #define M_BCM1480_MC_DQI_COARSE_ADJ _SB_MAKEMASK(6,S_BCM1480_MC_DQI_COARSE_ADJ) 580 #define V_BCM1480_MC_DQI_COARSE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQI_COARSE_ADJ) 581 #define G_BCM1480_MC_DQI_COARSE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_DQI_COARSE_ADJ,M_BCM1480_MC_DQI_COARSE_ADJ) 582 #define V_BCM1480_MC_DQI_COARSE_ADJ_DEFAULT V_BCM1480_MC_DQI_COARSE_ADJ(0x0) 583 584 #if SIBYTE_HDR_FEATURE(1480, PASS2) 585 #define S_BCM1480_MC_DQI_FREQ_RANGE 24 586 #define M_BCM1480_MC_DQI_FREQ_RANGE _SB_MAKEMASK(4,S_BCM1480_MC_DQI_FREQ_RANGE) 587 #define V_BCM1480_MC_DQI_FREQ_RANGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQI_FREQ_RANGE) 588 #define G_BCM1480_MC_DQI_FREQ_RANGE(x) _SB_GETVALUE(x,S_BCM1480_MC_DQI_FREQ_RANGE,M_BCM1480_MC_DQI_FREQ_RANGE) 589 #define V_BCM1480_MC_DQI_FREQ_RANGE_DEFAULT V_BCM1480_MC_DQI_FREQ_RANGE(0x4) 590 #endif 591 592 #define S_BCM1480_MC_DQI_FINE_ADJ 24 593 #define M_BCM1480_MC_DQI_FINE_ADJ _SB_MAKEMASK(4,S_BCM1480_MC_DQI_FINE_ADJ) 594 #define V_BCM1480_MC_DQI_FINE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQI_FINE_ADJ) 595 #define G_BCM1480_MC_DQI_FINE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_DQI_FINE_ADJ,M_BCM1480_MC_DQI_FINE_ADJ) 596 #define V_BCM1480_MC_DQI_FINE_ADJ_DEFAULT V_BCM1480_MC_DQI_FINE_ADJ(0x8) 597 598 #define S_BCM1480_MC_DQO_COARSE_ADJ 32 599 #define M_BCM1480_MC_DQO_COARSE_ADJ _SB_MAKEMASK(6,S_BCM1480_MC_DQO_COARSE_ADJ) 600 #define V_BCM1480_MC_DQO_COARSE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQO_COARSE_ADJ) 601 #define G_BCM1480_MC_DQO_COARSE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_DQO_COARSE_ADJ,M_BCM1480_MC_DQO_COARSE_ADJ) 602 #define V_BCM1480_MC_DQO_COARSE_ADJ_DEFAULT V_BCM1480_MC_DQO_COARSE_ADJ(0x0) 603 604 #if SIBYTE_HDR_FEATURE(1480, PASS2) 605 #define S_BCM1480_MC_DQO_FREQ_RANGE 40 606 #define M_BCM1480_MC_DQO_FREQ_RANGE _SB_MAKEMASK(4,S_BCM1480_MC_DQO_FREQ_RANGE) 607 #define V_BCM1480_MC_DQO_FREQ_RANGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQO_FREQ_RANGE) 608 #define G_BCM1480_MC_DQO_FREQ_RANGE(x) _SB_GETVALUE(x,S_BCM1480_MC_DQO_FREQ_RANGE,M_BCM1480_MC_DQO_FREQ_RANGE) 609 #define V_BCM1480_MC_DQO_FREQ_RANGE_DEFAULT V_BCM1480_MC_DQO_FREQ_RANGE(0x4) 610 #endif 611 612 #define S_BCM1480_MC_DQO_FINE_ADJ 40 613 #define M_BCM1480_MC_DQO_FINE_ADJ _SB_MAKEMASK(4,S_BCM1480_MC_DQO_FINE_ADJ) 614 #define V_BCM1480_MC_DQO_FINE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQO_FINE_ADJ) 615 #define G_BCM1480_MC_DQO_FINE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_DQO_FINE_ADJ,M_BCM1480_MC_DQO_FINE_ADJ) 616 #define V_BCM1480_MC_DQO_FINE_ADJ_DEFAULT V_BCM1480_MC_DQO_FINE_ADJ(0x8) 617 618 #if SIBYTE_HDR_FEATURE(1480, PASS2) 619 #define S_BCM1480_MC_DLL_PDSEL 44 620 #define M_BCM1480_MC_DLL_PDSEL _SB_MAKEMASK(2,S_BCM1480_MC_DLL_PDSEL) 621 #define V_BCM1480_MC_DLL_PDSEL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_PDSEL) 622 #define G_BCM1480_MC_DLL_PDSEL(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_PDSEL,M_BCM1480_MC_DLL_PDSEL) 623 #define V_BCM1480_MC_DLL_DEFAULT_PDSEL V_BCM1480_MC_DLL_PDSEL(0x0) 624 625 #define M_BCM1480_MC_DLL_REGBYPASS _SB_MAKEMASK1(46) 626 #define M_BCM1480_MC_DQO_SHIFT _SB_MAKEMASK1(47) 627 #endif 628 629 #define S_BCM1480_MC_DLL_DEFAULT 48 630 #define M_BCM1480_MC_DLL_DEFAULT _SB_MAKEMASK(6,S_BCM1480_MC_DLL_DEFAULT) 631 #define V_BCM1480_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_DEFAULT) 632 #define G_BCM1480_MC_DLL_DEFAULT(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_DEFAULT,M_BCM1480_MC_DLL_DEFAULT) 633 #define V_BCM1480_MC_DLL_DEFAULT_DEFAULT V_BCM1480_MC_DLL_DEFAULT(0x10) 634 635 #if SIBYTE_HDR_FEATURE(1480, PASS2) 636 #define S_BCM1480_MC_DLL_REGCTRL 54 637 #define M_BCM1480_MC_DLL_REGCTRL _SB_MAKEMASK(2,S_BCM1480_MC_DLL_REGCTRL) 638 #define V_BCM1480_MC_DLL_REGCTRL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_REGCTRL) 639 #define G_BCM1480_MC_DLL_REGCTRL(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_REGCTRL,M_BCM1480_MC_DLL_REGCTRL) 640 #define V_BCM1480_MC_DLL_DEFAULT_REGCTRL V_BCM1480_MC_DLL_REGCTRL(0x0) 641 #endif 642 643 #if SIBYTE_HDR_FEATURE(1480, PASS2) 644 #define S_BCM1480_MC_DLL_FREQ_RANGE 56 645 #define M_BCM1480_MC_DLL_FREQ_RANGE _SB_MAKEMASK(4,S_BCM1480_MC_DLL_FREQ_RANGE) 646 #define V_BCM1480_MC_DLL_FREQ_RANGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_FREQ_RANGE) 647 #define G_BCM1480_MC_DLL_FREQ_RANGE(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_FREQ_RANGE,M_BCM1480_MC_DLL_FREQ_RANGE) 648 #define V_BCM1480_MC_DLL_FREQ_RANGE_DEFAULT V_BCM1480_MC_DLL_FREQ_RANGE(0x4) 649 #endif 650 651 #define S_BCM1480_MC_DLL_STEP_SIZE 56 652 #define M_BCM1480_MC_DLL_STEP_SIZE _SB_MAKEMASK(4,S_BCM1480_MC_DLL_STEP_SIZE) 653 #define V_BCM1480_MC_DLL_STEP_SIZE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_STEP_SIZE) 654 #define G_BCM1480_MC_DLL_STEP_SIZE(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_STEP_SIZE,M_BCM1480_MC_DLL_STEP_SIZE) 655 #define V_BCM1480_MC_DLL_STEP_SIZE_DEFAULT V_BCM1480_MC_DLL_STEP_SIZE(0x8) 656 657 #if SIBYTE_HDR_FEATURE(1480, PASS2) 658 #define S_BCM1480_MC_DLL_BGCTRL 60 659 #define M_BCM1480_MC_DLL_BGCTRL _SB_MAKEMASK(2,S_BCM1480_MC_DLL_BGCTRL) 660 #define V_BCM1480_MC_DLL_BGCTRL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_BGCTRL) 661 #define G_BCM1480_MC_DLL_BGCTRL(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_BGCTRL,M_BCM1480_MC_DLL_BGCTRL) 662 #define V_BCM1480_MC_DLL_DEFAULT_BGCTRL V_BCM1480_MC_DLL_BGCTRL(0x0) 663 #endif 664 665 #define M_BCM1480_MC_DLL_BYPASS _SB_MAKEMASK1(63) 666 667 /* 668 * Memory Drive Configuration Register (Table 94) 669 */ 670 671 #define S_BCM1480_MC_RTT_BYP_PULLDOWN 0 672 #define M_BCM1480_MC_RTT_BYP_PULLDOWN _SB_MAKEMASK(3,S_BCM1480_MC_RTT_BYP_PULLDOWN) 673 #define V_BCM1480_MC_RTT_BYP_PULLDOWN(x) _SB_MAKEVALUE(x,S_BCM1480_MC_RTT_BYP_PULLDOWN) 674 #define G_BCM1480_MC_RTT_BYP_PULLDOWN(x) _SB_GETVALUE(x,S_BCM1480_MC_RTT_BYP_PULLDOWN,M_BCM1480_MC_RTT_BYP_PULLDOWN) 675 676 #define S_BCM1480_MC_RTT_BYP_PULLUP 6 677 #define M_BCM1480_MC_RTT_BYP_PULLUP _SB_MAKEMASK(3,S_BCM1480_MC_RTT_BYP_PULLUP) 678 #define V_BCM1480_MC_RTT_BYP_PULLUP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_RTT_BYP_PULLUP) 679 #define G_BCM1480_MC_RTT_BYP_PULLUP(x) _SB_GETVALUE(x,S_BCM1480_MC_RTT_BYP_PULLUP,M_BCM1480_MC_RTT_BYP_PULLUP) 680 681 #define M_BCM1480_MC_RTT_BYPASS _SB_MAKEMASK1(8) 682 #define M_BCM1480_MC_RTT_COMP_MOV_AVG _SB_MAKEMASK1(9) 683 684 #define S_BCM1480_MC_PVT_BYP_C1_PULLDOWN 10 685 #define M_BCM1480_MC_PVT_BYP_C1_PULLDOWN _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C1_PULLDOWN) 686 #define V_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLDOWN) 687 #define G_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLDOWN,M_BCM1480_MC_PVT_BYP_C1_PULLDOWN) 688 689 #define S_BCM1480_MC_PVT_BYP_C1_PULLUP 15 690 #define M_BCM1480_MC_PVT_BYP_C1_PULLUP _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C1_PULLUP) 691 #define V_BCM1480_MC_PVT_BYP_C1_PULLUP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLUP) 692 #define G_BCM1480_MC_PVT_BYP_C1_PULLUP(x) _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLUP,M_BCM1480_MC_PVT_BYP_C1_PULLUP) 693 694 #define S_BCM1480_MC_PVT_BYP_C2_PULLDOWN 20 695 #define M_BCM1480_MC_PVT_BYP_C2_PULLDOWN _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C2_PULLDOWN) 696 #define V_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLDOWN) 697 #define G_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLDOWN,M_BCM1480_MC_PVT_BYP_C2_PULLDOWN) 698 699 #define S_BCM1480_MC_PVT_BYP_C2_PULLUP 25 700 #define M_BCM1480_MC_PVT_BYP_C2_PULLUP _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C2_PULLUP) 701 #define V_BCM1480_MC_PVT_BYP_C2_PULLUP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLUP) 702 #define G_BCM1480_MC_PVT_BYP_C2_PULLUP(x) _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLUP,M_BCM1480_MC_PVT_BYP_C2_PULLUP) 703 704 #define M_BCM1480_MC_PVT_BYPASS _SB_MAKEMASK1(30) 705 #define M_BCM1480_MC_PVT_COMP_MOV_AVG _SB_MAKEMASK1(31) 706 707 #define M_BCM1480_MC_CLK_CLASS _SB_MAKEMASK1(34) 708 #define M_BCM1480_MC_DATA_CLASS _SB_MAKEMASK1(35) 709 #define M_BCM1480_MC_ADDR_CLASS _SB_MAKEMASK1(36) 710 711 #define M_BCM1480_MC_DQ_ODT_75 _SB_MAKEMASK1(37) 712 #define M_BCM1480_MC_DQ_ODT_150 _SB_MAKEMASK1(38) 713 #define M_BCM1480_MC_DQS_ODT_75 _SB_MAKEMASK1(39) 714 #define M_BCM1480_MC_DQS_ODT_150 _SB_MAKEMASK1(40) 715 #define M_BCM1480_MC_DQS_DIFF _SB_MAKEMASK1(41) 716 717 /* 718 * ECC Test Data Register (Table 95) 719 */ 720 721 #define S_BCM1480_MC_DATA_INVERT 0 722 #define M_DATA_ECC_INVERT _SB_MAKEMASK(64,S_BCM1480_MC_ECC_INVERT) 723 724 /* 725 * ECC Test ECC Register (Table 96) 726 */ 727 728 #define S_BCM1480_MC_ECC_INVERT 0 729 #define M_BCM1480_MC_ECC_INVERT _SB_MAKEMASK(8,S_BCM1480_MC_ECC_INVERT) 730 731 /* 732 * SDRAM Timing Register (Table 97) 733 */ 734 735 #define S_BCM1480_MC_tRCD 0 736 #define M_BCM1480_MC_tRCD _SB_MAKEMASK(4,S_BCM1480_MC_tRCD) 737 #define V_BCM1480_MC_tRCD(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRCD) 738 #define G_BCM1480_MC_tRCD(x) _SB_GETVALUE(x,S_BCM1480_MC_tRCD,M_BCM1480_MC_tRCD) 739 #define K_BCM1480_MC_tRCD_DEFAULT 3 740 #define V_BCM1480_MC_tRCD_DEFAULT V_BCM1480_MC_tRCD(K_BCM1480_MC_tRCD_DEFAULT) 741 742 #define S_BCM1480_MC_tCL 4 743 #define M_BCM1480_MC_tCL _SB_MAKEMASK(4,S_BCM1480_MC_tCL) 744 #define V_BCM1480_MC_tCL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tCL) 745 #define G_BCM1480_MC_tCL(x) _SB_GETVALUE(x,S_BCM1480_MC_tCL,M_BCM1480_MC_tCL) 746 #define K_BCM1480_MC_tCL_DEFAULT 2 747 #define V_BCM1480_MC_tCL_DEFAULT V_BCM1480_MC_tCL(K_BCM1480_MC_tCL_DEFAULT) 748 749 #define M_BCM1480_MC_tCrDh _SB_MAKEMASK1(8) 750 751 #define S_BCM1480_MC_tWR 9 752 #define M_BCM1480_MC_tWR _SB_MAKEMASK(3,S_BCM1480_MC_tWR) 753 #define V_BCM1480_MC_tWR(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tWR) 754 #define G_BCM1480_MC_tWR(x) _SB_GETVALUE(x,S_BCM1480_MC_tWR,M_BCM1480_MC_tWR) 755 #define K_BCM1480_MC_tWR_DEFAULT 2 756 #define V_BCM1480_MC_tWR_DEFAULT V_BCM1480_MC_tWR(K_BCM1480_MC_tWR_DEFAULT) 757 758 #define S_BCM1480_MC_tCwD 12 759 #define M_BCM1480_MC_tCwD _SB_MAKEMASK(4,S_BCM1480_MC_tCwD) 760 #define V_BCM1480_MC_tCwD(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tCwD) 761 #define G_BCM1480_MC_tCwD(x) _SB_GETVALUE(x,S_BCM1480_MC_tCwD,M_BCM1480_MC_tCwD) 762 #define K_BCM1480_MC_tCwD_DEFAULT 1 763 #define V_BCM1480_MC_tCwD_DEFAULT V_BCM1480_MC_tCwD(K_BCM1480_MC_tCwD_DEFAULT) 764 765 #define S_BCM1480_MC_tRP 16 766 #define M_BCM1480_MC_tRP _SB_MAKEMASK(4,S_BCM1480_MC_tRP) 767 #define V_BCM1480_MC_tRP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRP) 768 #define G_BCM1480_MC_tRP(x) _SB_GETVALUE(x,S_BCM1480_MC_tRP,M_BCM1480_MC_tRP) 769 #define K_BCM1480_MC_tRP_DEFAULT 4 770 #define V_BCM1480_MC_tRP_DEFAULT V_BCM1480_MC_tRP(K_BCM1480_MC_tRP_DEFAULT) 771 772 #define S_BCM1480_MC_tRRD 20 773 #define M_BCM1480_MC_tRRD _SB_MAKEMASK(4,S_BCM1480_MC_tRRD) 774 #define V_BCM1480_MC_tRRD(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRRD) 775 #define G_BCM1480_MC_tRRD(x) _SB_GETVALUE(x,S_BCM1480_MC_tRRD,M_BCM1480_MC_tRRD) 776 #define K_BCM1480_MC_tRRD_DEFAULT 2 777 #define V_BCM1480_MC_tRRD_DEFAULT V_BCM1480_MC_tRRD(K_BCM1480_MC_tRRD_DEFAULT) 778 779 #define S_BCM1480_MC_tRCw 24 780 #define M_BCM1480_MC_tRCw _SB_MAKEMASK(5,S_BCM1480_MC_tRCw) 781 #define V_BCM1480_MC_tRCw(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRCw) 782 #define G_BCM1480_MC_tRCw(x) _SB_GETVALUE(x,S_BCM1480_MC_tRCw,M_BCM1480_MC_tRCw) 783 #define K_BCM1480_MC_tRCw_DEFAULT 10 784 #define V_BCM1480_MC_tRCw_DEFAULT V_BCM1480_MC_tRCw(K_BCM1480_MC_tRCw_DEFAULT) 785 786 #define S_BCM1480_MC_tRCr 32 787 #define M_BCM1480_MC_tRCr _SB_MAKEMASK(5,S_BCM1480_MC_tRCr) 788 #define V_BCM1480_MC_tRCr(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRCr) 789 #define G_BCM1480_MC_tRCr(x) _SB_GETVALUE(x,S_BCM1480_MC_tRCr,M_BCM1480_MC_tRCr) 790 #define K_BCM1480_MC_tRCr_DEFAULT 9 791 #define V_BCM1480_MC_tRCr_DEFAULT V_BCM1480_MC_tRCr(K_BCM1480_MC_tRCr_DEFAULT) 792 793 #if SIBYTE_HDR_FEATURE(1480, PASS2) 794 #define S_BCM1480_MC_tFAW 40 795 #define M_BCM1480_MC_tFAW _SB_MAKEMASK(6,S_BCM1480_MC_tFAW) 796 #define V_BCM1480_MC_tFAW(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tFAW) 797 #define G_BCM1480_MC_tFAW(x) _SB_GETVALUE(x,S_BCM1480_MC_tFAW,M_BCM1480_MC_tFAW) 798 #define K_BCM1480_MC_tFAW_DEFAULT 0 799 #define V_BCM1480_MC_tFAW_DEFAULT V_BCM1480_MC_tFAW(K_BCM1480_MC_tFAW_DEFAULT) 800 #endif 801 802 #define S_BCM1480_MC_tRFC 48 803 #define M_BCM1480_MC_tRFC _SB_MAKEMASK(7,S_BCM1480_MC_tRFC) 804 #define V_BCM1480_MC_tRFC(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRFC) 805 #define G_BCM1480_MC_tRFC(x) _SB_GETVALUE(x,S_BCM1480_MC_tRFC,M_BCM1480_MC_tRFC) 806 #define K_BCM1480_MC_tRFC_DEFAULT 12 807 #define V_BCM1480_MC_tRFC_DEFAULT V_BCM1480_MC_tRFC(K_BCM1480_MC_tRFC_DEFAULT) 808 809 #define S_BCM1480_MC_tFIFO 56 810 #define M_BCM1480_MC_tFIFO _SB_MAKEMASK(2,S_BCM1480_MC_tFIFO) 811 #define V_BCM1480_MC_tFIFO(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tFIFO) 812 #define G_BCM1480_MC_tFIFO(x) _SB_GETVALUE(x,S_BCM1480_MC_tFIFO,M_BCM1480_MC_tFIFO) 813 #define K_BCM1480_MC_tFIFO_DEFAULT 0 814 #define V_BCM1480_MC_tFIFO_DEFAULT V_BCM1480_MC_tFIFO(K_BCM1480_MC_tFIFO_DEFAULT) 815 816 #define S_BCM1480_MC_tW2R 58 817 #define M_BCM1480_MC_tW2R _SB_MAKEMASK(2,S_BCM1480_MC_tW2R) 818 #define V_BCM1480_MC_tW2R(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tW2R) 819 #define G_BCM1480_MC_tW2R(x) _SB_GETVALUE(x,S_BCM1480_MC_tW2R,M_BCM1480_MC_tW2R) 820 #define K_BCM1480_MC_tW2R_DEFAULT 1 821 #define V_BCM1480_MC_tW2R_DEFAULT V_BCM1480_MC_tW2R(K_BCM1480_MC_tW2R_DEFAULT) 822 823 #define S_BCM1480_MC_tR2W 60 824 #define M_BCM1480_MC_tR2W _SB_MAKEMASK(2,S_BCM1480_MC_tR2W) 825 #define V_BCM1480_MC_tR2W(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tR2W) 826 #define G_BCM1480_MC_tR2W(x) _SB_GETVALUE(x,S_BCM1480_MC_tR2W,M_BCM1480_MC_tR2W) 827 #define K_BCM1480_MC_tR2W_DEFAULT 0 828 #define V_BCM1480_MC_tR2W_DEFAULT V_BCM1480_MC_tR2W(K_BCM1480_MC_tR2W_DEFAULT) 829 830 #define M_BCM1480_MC_tR2R _SB_MAKEMASK1(62) 831 832 #define V_BCM1480_MC_TIMING_DEFAULT (M_BCM1480_MC_tR2R | \ 833 V_BCM1480_MC_tFIFO_DEFAULT | \ 834 V_BCM1480_MC_tR2W_DEFAULT | \ 835 V_BCM1480_MC_tW2R_DEFAULT | \ 836 V_BCM1480_MC_tRFC_DEFAULT | \ 837 V_BCM1480_MC_tRCr_DEFAULT | \ 838 V_BCM1480_MC_tRCw_DEFAULT | \ 839 V_BCM1480_MC_tRRD_DEFAULT | \ 840 V_BCM1480_MC_tRP_DEFAULT | \ 841 V_BCM1480_MC_tCwD_DEFAULT | \ 842 V_BCM1480_MC_tWR_DEFAULT | \ 843 M_BCM1480_MC_tCrDh | \ 844 V_BCM1480_MC_tCL_DEFAULT | \ 845 V_BCM1480_MC_tRCD_DEFAULT) 846 847 /* 848 * SDRAM Timing Register 2 849 */ 850 851 #if SIBYTE_HDR_FEATURE(1480, PASS2) 852 853 #define S_BCM1480_MC_tAL 0 854 #define M_BCM1480_MC_tAL _SB_MAKEMASK(4,S_BCM1480_MC_tAL) 855 #define V_BCM1480_MC_tAL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tAL) 856 #define G_BCM1480_MC_tAL(x) _SB_GETVALUE(x,S_BCM1480_MC_tAL,M_BCM1480_MC_tAL) 857 #define K_BCM1480_MC_tAL_DEFAULT 0 858 #define V_BCM1480_MC_tAL_DEFAULT V_BCM1480_MC_tAL(K_BCM1480_MC_tAL_DEFAULT) 859 860 #define S_BCM1480_MC_tRTP 4 861 #define M_BCM1480_MC_tRTP _SB_MAKEMASK(3,S_BCM1480_MC_tRTP) 862 #define V_BCM1480_MC_tRTP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRTP) 863 #define G_BCM1480_MC_tRTP(x) _SB_GETVALUE(x,S_BCM1480_MC_tRTP,M_BCM1480_MC_tRTP) 864 #define K_BCM1480_MC_tRTP_DEFAULT 2 865 #define V_BCM1480_MC_tRTP_DEFAULT V_BCM1480_MC_tRTP(K_BCM1480_MC_tRTP_DEFAULT) 866 867 #define S_BCM1480_MC_tW2W 8 868 #define M_BCM1480_MC_tW2W _SB_MAKEMASK(2,S_BCM1480_MC_tW2W) 869 #define V_BCM1480_MC_tW2W(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tW2W) 870 #define G_BCM1480_MC_tW2W(x) _SB_GETVALUE(x,S_BCM1480_MC_tW2W,M_BCM1480_MC_tW2W) 871 #define K_BCM1480_MC_tW2W_DEFAULT 0 872 #define V_BCM1480_MC_tW2W_DEFAULT V_BCM1480_MC_tW2W(K_BCM1480_MC_tW2W_DEFAULT) 873 874 #define S_BCM1480_MC_tRAP 12 875 #define M_BCM1480_MC_tRAP _SB_MAKEMASK(4,S_BCM1480_MC_tRAP) 876 #define V_BCM1480_MC_tRAP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRAP) 877 #define G_BCM1480_MC_tRAP(x) _SB_GETVALUE(x,S_BCM1480_MC_tRAP,M_BCM1480_MC_tRAP) 878 #define K_BCM1480_MC_tRAP_DEFAULT 0 879 #define V_BCM1480_MC_tRAP_DEFAULT V_BCM1480_MC_tRAP(K_BCM1480_MC_tRAP_DEFAULT) 880 881 #endif 882 883 884 885 /* 886 * Global Registers: single instances per BCM1480 887 */ 888 889 /* 890 * Global Configuration Register (Table 99) 891 */ 892 893 #define S_BCM1480_MC_BLK_SET_MARK 8 894 #define M_BCM1480_MC_BLK_SET_MARK _SB_MAKEMASK(4,S_BCM1480_MC_BLK_SET_MARK) 895 #define V_BCM1480_MC_BLK_SET_MARK(x) _SB_MAKEVALUE(x,S_BCM1480_MC_BLK_SET_MARK) 896 #define G_BCM1480_MC_BLK_SET_MARK(x) _SB_GETVALUE(x,S_BCM1480_MC_BLK_SET_MARK,M_BCM1480_MC_BLK_SET_MARK) 897 898 #define S_BCM1480_MC_BLK_CLR_MARK 12 899 #define M_BCM1480_MC_BLK_CLR_MARK _SB_MAKEMASK(4,S_BCM1480_MC_BLK_CLR_MARK) 900 #define V_BCM1480_MC_BLK_CLR_MARK(x) _SB_MAKEVALUE(x,S_BCM1480_MC_BLK_CLR_MARK) 901 #define G_BCM1480_MC_BLK_CLR_MARK(x) _SB_GETVALUE(x,S_BCM1480_MC_BLK_CLR_MARK,M_BCM1480_MC_BLK_CLR_MARK) 902 903 #define M_BCM1480_MC_PKT_PRIORITY _SB_MAKEMASK1(16) 904 905 #define S_BCM1480_MC_MAX_AGE 20 906 #define M_BCM1480_MC_MAX_AGE _SB_MAKEMASK(4,S_BCM1480_MC_MAX_AGE) 907 #define V_BCM1480_MC_MAX_AGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_MAX_AGE) 908 #define G_BCM1480_MC_MAX_AGE(x) _SB_GETVALUE(x,S_BCM1480_MC_MAX_AGE,M_BCM1480_MC_MAX_AGE) 909 910 #define M_BCM1480_MC_BERR_DISABLE _SB_MAKEMASK1(29) 911 #define M_BCM1480_MC_FORCE_SEQ _SB_MAKEMASK1(30) 912 #define M_BCM1480_MC_VGEN _SB_MAKEMASK1(32) 913 914 #define S_BCM1480_MC_SLEW 33 915 #define M_BCM1480_MC_SLEW _SB_MAKEMASK(2,S_BCM1480_MC_SLEW) 916 #define V_BCM1480_MC_SLEW(x) _SB_MAKEVALUE(x,S_BCM1480_MC_SLEW) 917 #define G_BCM1480_MC_SLEW(x) _SB_GETVALUE(x,S_BCM1480_MC_SLEW,M_BCM1480_MC_SLEW) 918 919 #define M_BCM1480_MC_SSTL_VOLTAGE _SB_MAKEMASK1(35) 920 921 /* 922 * Global Channel Interleave Register (Table 100) 923 */ 924 925 #define S_BCM1480_MC_INTLV0 0 926 #define M_BCM1480_MC_INTLV0 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV0) 927 #define V_BCM1480_MC_INTLV0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV0) 928 #define G_BCM1480_MC_INTLV0(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV0,M_BCM1480_MC_INTLV0) 929 930 #define S_BCM1480_MC_INTLV1 8 931 #define M_BCM1480_MC_INTLV1 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV1) 932 #define V_BCM1480_MC_INTLV1(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV1) 933 #define G_BCM1480_MC_INTLV1(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV1,M_BCM1480_MC_INTLV1) 934 935 #define S_BCM1480_MC_INTLV_MODE 16 936 #define M_BCM1480_MC_INTLV_MODE _SB_MAKEMASK(3,S_BCM1480_MC_INTLV_MODE) 937 #define V_BCM1480_MC_INTLV_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV_MODE) 938 #define G_BCM1480_MC_INTLV_MODE(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV_MODE,M_BCM1480_MC_INTLV_MODE) 939 940 #define K_BCM1480_MC_INTLV_MODE_NONE 0x0 941 #define K_BCM1480_MC_INTLV_MODE_01 0x1 942 #define K_BCM1480_MC_INTLV_MODE_23 0x2 943 #define K_BCM1480_MC_INTLV_MODE_01_23 0x3 944 #define K_BCM1480_MC_INTLV_MODE_0123 0x4 945 946 #define V_BCM1480_MC_INTLV_MODE_NONE V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_NONE) 947 #define V_BCM1480_MC_INTLV_MODE_01 V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_01) 948 #define V_BCM1480_MC_INTLV_MODE_23 V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_23) 949 #define V_BCM1480_MC_INTLV_MODE_01_23 V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_01_23) 950 #define V_BCM1480_MC_INTLV_MODE_0123 V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_0123) 951 952 /* 953 * ECC Status Register 954 */ 955 956 #define S_BCM1480_MC_ECC_ERR_ADDR 0 957 #define M_BCM1480_MC_ECC_ERR_ADDR _SB_MAKEMASK(37,S_BCM1480_MC_ECC_ERR_ADDR) 958 #define V_BCM1480_MC_ECC_ERR_ADDR(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ECC_ERR_ADDR) 959 #define G_BCM1480_MC_ECC_ERR_ADDR(x) _SB_GETVALUE(x,S_BCM1480_MC_ECC_ERR_ADDR,M_BCM1480_MC_ECC_ERR_ADDR) 960 961 #if SIBYTE_HDR_FEATURE(1480, PASS2) 962 #define M_BCM1480_MC_ECC_ERR_RMW _SB_MAKEMASK1(60) 963 #endif 964 965 #define M_BCM1480_MC_ECC_MULT_ERR_DET _SB_MAKEMASK1(61) 966 #define M_BCM1480_MC_ECC_UERR_DET _SB_MAKEMASK1(62) 967 #define M_BCM1480_MC_ECC_CERR_DET _SB_MAKEMASK1(63) 968 969 /* 970 * Global ECC Address Register (Table 102) 971 */ 972 973 #define S_BCM1480_MC_ECC_CORR_ADDR 0 974 #define M_BCM1480_MC_ECC_CORR_ADDR _SB_MAKEMASK(37,S_BCM1480_MC_ECC_CORR_ADDR) 975 #define V_BCM1480_MC_ECC_CORR_ADDR(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ECC_CORR_ADDR) 976 #define G_BCM1480_MC_ECC_CORR_ADDR(x) _SB_GETVALUE(x,S_BCM1480_MC_ECC_CORR_ADDR,M_BCM1480_MC_ECC_CORR_ADDR) 977 978 /* 979 * Global ECC Correction Register (Table 103) 980 */ 981 982 #define S_BCM1480_MC_ECC_CORRECT 0 983 #define M_BCM1480_MC_ECC_CORRECT _SB_MAKEMASK(64,S_BCM1480_MC_ECC_CORRECT) 984 #define V_BCM1480_MC_ECC_CORRECT(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ECC_CORRECT) 985 #define G_BCM1480_MC_ECC_CORRECT(x) _SB_GETVALUE(x,S_BCM1480_MC_ECC_CORRECT,M_BCM1480_MC_ECC_CORRECT) 986 987 /* 988 * Global ECC Performance Counters Control Register (Table 104) 989 */ 990 991 #define S_BCM1480_MC_CHANNEL_SELECT 0 992 #define M_BCM1480_MC_CHANNEL_SELECT _SB_MAKEMASK(4,S_BCM1480_MC_CHANNEL_SELECT) 993 #define V_BCM1480_MC_CHANNEL_SELECT(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CHANNEL_SELECT) 994 #define G_BCM1480_MC_CHANNEL_SELECT(x) _SB_GETVALUE(x,S_BCM1480_MC_CHANNEL_SELECT,M_BCM1480_MC_CHANNEL_SELECT) 995 #define K_BCM1480_MC_CHANNEL_SELECT_0 0x1 996 #define K_BCM1480_MC_CHANNEL_SELECT_1 0x2 997 #define K_BCM1480_MC_CHANNEL_SELECT_2 0x4 998 #define K_BCM1480_MC_CHANNEL_SELECT_3 0x8 999 1000 #endif /* _BCM1480_MC_H */ 1001
Indexes created Mon Sep 29 03:10:08 GMT 2025