sb1250_scd.h revision 1.3.2.3
1 1.3.2.2 nathanw /* ********************************************************************* 2 1.3.2.2 nathanw * SB1250 Board Support Package 3 1.3.2.2 nathanw * 4 1.3.2.2 nathanw * SCD Constants and Macros File: sb1250_scd.h 5 1.3.2.2 nathanw * 6 1.3.2.2 nathanw * This module contains constants and macros useful for 7 1.3.2.2 nathanw * manipulating the System Control and Debug module on the 1250. 8 1.3.2.2 nathanw * 9 1.3.2.2 nathanw * SB1250 specification level: User's manual 1/02/02 10 1.3.2.2 nathanw * 11 1.3.2.2 nathanw * Author: Mitch Lichtenberg (mpl (at) broadcom.com) 12 1.3.2.2 nathanw * 13 1.3.2.2 nathanw ********************************************************************* 14 1.3.2.2 nathanw * 15 1.3.2.2 nathanw * Copyright 2000,2001 16 1.3.2.2 nathanw * Broadcom Corporation. All rights reserved. 17 1.3.2.2 nathanw * 18 1.3.2.2 nathanw * This software is furnished under license and may be used and 19 1.3.2.2 nathanw * copied only in accordance with the following terms and 20 1.3.2.2 nathanw * conditions. Subject to these conditions, you may download, 21 1.3.2.2 nathanw * copy, install, use, modify and distribute modified or unmodified 22 1.3.2.2 nathanw * copies of this software in source and/or binary form. No title 23 1.3.2.2 nathanw * or ownership is transferred hereby. 24 1.3.2.2 nathanw * 25 1.3.2.2 nathanw * 1) Any source code used, modified or distributed must reproduce 26 1.3.2.2 nathanw * and retain this copyright notice and list of conditions as 27 1.3.2.2 nathanw * they appear in the source file. 28 1.3.2.2 nathanw * 29 1.3.2.2 nathanw * 2) No right is granted to use any trade name, trademark, or 30 1.3.2.2 nathanw * logo of Broadcom Corporation. Neither the "Broadcom 31 1.3.2.2 nathanw * Corporation" name nor any trademark or logo of Broadcom 32 1.3.2.2 nathanw * Corporation may be used to endorse or promote products 33 1.3.2.2 nathanw * derived from this software without the prior written 34 1.3.2.2 nathanw * permission of Broadcom Corporation. 35 1.3.2.2 nathanw * 36 1.3.2.2 nathanw * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 37 1.3.2.2 nathanw * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 38 1.3.2.2 nathanw * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 39 1.3.2.2 nathanw * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 40 1.3.2.2 nathanw * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 41 1.3.2.2 nathanw * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 42 1.3.2.2 nathanw * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 43 1.3.2.2 nathanw * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 44 1.3.2.2 nathanw * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 45 1.3.2.2 nathanw * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 46 1.3.2.2 nathanw * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 47 1.3.2.2 nathanw * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 48 1.3.2.2 nathanw * THE POSSIBILITY OF SUCH DAMAGE. 49 1.3.2.2 nathanw ********************************************************************* */ 50 1.3.2.2 nathanw 51 1.3.2.2 nathanw #ifndef _SB1250_SCD_H 52 1.3.2.2 nathanw #define _SB1250_SCD_H 53 1.3.2.2 nathanw 54 1.3.2.2 nathanw #include "sb1250_defs.h" 55 1.3.2.2 nathanw 56 1.3.2.2 nathanw /* ********************************************************************* 57 1.3.2.2 nathanw * System control/debug registers 58 1.3.2.2 nathanw ********************************************************************* */ 59 1.3.2.2 nathanw 60 1.3.2.2 nathanw /* 61 1.3.2.2 nathanw * System Revision Register (Table 4-1) 62 1.3.2.2 nathanw */ 63 1.3.2.2 nathanw 64 1.3.2.2 nathanw #define M_SYS_RESERVED _SB_MAKEMASK(8,0) 65 1.3.2.2 nathanw 66 1.3.2.2 nathanw #define S_SYS_REVISION _SB_MAKE64(8) 67 1.3.2.2 nathanw #define M_SYS_REVISION _SB_MAKEMASK(8,S_SYS_REVISION) 68 1.3.2.2 nathanw #define V_SYS_REVISION(x) _SB_MAKEVALUE(x,S_SYS_REVISION) 69 1.3.2.2 nathanw #define G_SYS_REVISION(x) _SB_GETVALUE(x,S_SYS_REVISION,M_SYS_REVISION) 70 1.3.2.2 nathanw 71 1.3.2.2 nathanw #if SIBYTE_HDR_FEATURE_CHIP(1250) 72 1.3.2.2 nathanw #define K_SYS_REVISION_BCM1250_PASS1 1 73 1.3.2.2 nathanw #define K_SYS_REVISION_BCM1250_PASS2 3 74 1.3.2.2 nathanw #define K_SYS_REVISION_BCM1250_PASS2_2 16 75 1.3.2.2 nathanw #define K_SYS_REVISION_BCM1250_PASS3 32 76 1.3.2.2 nathanw 77 1.3.2.2 nathanw /* XXX: discourage people from using these constants. */ 78 1.3.2.2 nathanw #define K_SYS_REVISION_PASS1 K_SYS_REVISION_BCM1250_PASS1 79 1.3.2.2 nathanw #define K_SYS_REVISION_PASS2 K_SYS_REVISION_BCM1250_PASS2 80 1.3.2.2 nathanw #define K_SYS_REVISION_PASS2_2 K_SYS_REVISION_BCM1250_PASS2_2 81 1.3.2.2 nathanw #define K_SYS_REVISION_PASS3 K_SYS_REVISION_BCM1250_PASS3 82 1.3.2.2 nathanw #endif /* 1250 */ 83 1.3.2.2 nathanw 84 1.3.2.2 nathanw #if SIBYTE_HDR_FEATURE_CHIP(112x) 85 1.3.2.2 nathanw #define K_SYS_REVISION_BCM112x_PASS1 32 86 1.3.2.2 nathanw #endif /* 112x */ 87 1.3.2.2 nathanw 88 1.3.2.2 nathanw /* XXX: discourage people from using these constants. */ 89 1.3.2.2 nathanw #define S_SYS_PART _SB_MAKE64(16) 90 1.3.2.2 nathanw #define M_SYS_PART _SB_MAKEMASK(16,S_SYS_PART) 91 1.3.2.2 nathanw #define V_SYS_PART(x) _SB_MAKEVALUE(x,S_SYS_PART) 92 1.3.2.2 nathanw #define G_SYS_PART(x) _SB_GETVALUE(x,S_SYS_PART,M_SYS_PART) 93 1.3.2.2 nathanw 94 1.3.2.2 nathanw /* XXX: discourage people from using these constants. */ 95 1.3.2.2 nathanw #define K_SYS_PART_SB1250 0x1250 96 1.3.2.2 nathanw #define K_SYS_PART_BCM1120 0x1121 97 1.3.2.2 nathanw #define K_SYS_PART_BCM1125 0x1123 98 1.3.2.2 nathanw #define K_SYS_PART_BCM1125H 0x1124 99 1.3.2.2 nathanw 100 1.3.2.2 nathanw /* The "peripheral set" (SOC type) is the low 4 bits of the "part" field. */ 101 1.3.2.2 nathanw #define S_SYS_SOC_TYPE _SB_MAKE64(16) 102 1.3.2.2 nathanw #define M_SYS_SOC_TYPE _SB_MAKEMASK(4,S_SYS_SOC_TYPE) 103 1.3.2.2 nathanw #define V_SYS_SOC_TYPE(x) _SB_MAKEVALUE(x,S_SYS_SOC_TYPE) 104 1.3.2.2 nathanw #define G_SYS_SOC_TYPE(x) _SB_GETVALUE(x,S_SYS_SOC_TYPE,M_SYS_SOC_TYPE) 105 1.3.2.2 nathanw 106 1.3.2.2 nathanw #define K_SYS_SOC_TYPE_BCM1250 0x0 107 1.3.2.2 nathanw #define K_SYS_SOC_TYPE_BCM1120 0x1 108 1.3.2.2 nathanw #define K_SYS_SOC_TYPE_BCM1250_ALT 0x2 /* 1250pass2 w/ 1/4 L2. */ 109 1.3.2.2 nathanw #define K_SYS_SOC_TYPE_BCM1125 0x3 110 1.3.2.2 nathanw #define K_SYS_SOC_TYPE_BCM1125H 0x4 111 1.3.2.2 nathanw #define K_SYS_SOC_TYPE_BCM1250_ALT2 0x5 /* 1250pass2 w/ 1/2 L2. */ 112 1.3.2.2 nathanw 113 1.3.2.2 nathanw /* 114 1.3.2.2 nathanw * Calculate correct SOC type given a copy of system revision register. 115 1.3.2.2 nathanw * 116 1.3.2.2 nathanw * (For the assembler version, sysrev and dest may be the same register. 117 1.3.2.2 nathanw * Also, it clobbers AT.) 118 1.3.2.2 nathanw */ 119 1.3.2.2 nathanw #ifdef __ASSEMBLER__ 120 1.3.2.2 nathanw #define SYS_SOC_TYPE(dest, sysrev) \ 121 1.3.2.2 nathanw .set push ; \ 122 1.3.2.2 nathanw .set reorder ; \ 123 1.3.2.2 nathanw dsrl dest, sysrev, S_SYS_SOC_TYPE ; \ 124 1.3.2.2 nathanw andi dest, dest, (M_SYS_SOC_TYPE >> S_SYS_SOC_TYPE); \ 125 1.3.2.2 nathanw beq dest, K_SYS_SOC_TYPE_BCM1250_ALT, 991f ; \ 126 1.3.2.2 nathanw beq dest, K_SYS_SOC_TYPE_BCM1250_ALT2, 991f ; \ 127 1.3.2.2 nathanw b 992f ; \ 128 1.3.2.2 nathanw 991: li dest, K_SYS_SOC_TYPE_BCM1250 ; \ 129 1.3.2.2 nathanw 992: \ 130 1.3.2.2 nathanw .set pop 131 1.3.2.2 nathanw #else 132 1.3.2.2 nathanw #define SYS_SOC_TYPE(sysrev) \ 133 1.3.2.2 nathanw ((G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT \ 134 1.3.2.2 nathanw || G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT2) \ 135 1.3.2.2 nathanw ? K_SYS_SOC_TYPE_BCM1250 : G_SYS_SOC_TYPE(sysrev)) 136 1.3.2.2 nathanw #endif 137 1.3.2.2 nathanw 138 1.3.2.2 nathanw #define S_SYS_WID _SB_MAKE64(32) 139 1.3.2.2 nathanw #define M_SYS_WID _SB_MAKEMASK(32,S_SYS_WID) 140 1.3.2.2 nathanw #define V_SYS_WID(x) _SB_MAKEVALUE(x,S_SYS_WID) 141 1.3.2.2 nathanw #define G_SYS_WID(x) _SB_GETVALUE(x,S_SYS_WID,M_SYS_WID) 142 1.3.2.2 nathanw 143 1.3.2.2 nathanw /* 144 1.3.2.2 nathanw * System Config Register (Table 4-2) 145 1.3.2.2 nathanw * Register: SCD_SYSTEM_CFG 146 1.3.2.2 nathanw */ 147 1.3.2.2 nathanw 148 1.3.2.2 nathanw #define M_SYS_LDT_PLL_BYP _SB_MAKEMASK1(3) 149 1.3.2.2 nathanw #define M_SYS_PCI_SYNC_TEST_MODE _SB_MAKEMASK1(4) 150 1.3.2.2 nathanw #define M_SYS_IOB0_DIV _SB_MAKEMASK1(5) 151 1.3.2.2 nathanw #define M_SYS_IOB1_DIV _SB_MAKEMASK1(6) 152 1.3.2.2 nathanw 153 1.3.2.2 nathanw #define S_SYS_PLL_DIV _SB_MAKE64(7) 154 1.3.2.2 nathanw #define M_SYS_PLL_DIV _SB_MAKEMASK(5,S_SYS_PLL_DIV) 155 1.3.2.2 nathanw #define V_SYS_PLL_DIV(x) _SB_MAKEVALUE(x,S_SYS_PLL_DIV) 156 1.3.2.2 nathanw #define G_SYS_PLL_DIV(x) _SB_GETVALUE(x,S_SYS_PLL_DIV,M_SYS_PLL_DIV) 157 1.3.2.2 nathanw 158 1.3.2.2 nathanw #define M_SYS_SER0_ENABLE _SB_MAKEMASK1(12) 159 1.3.2.2 nathanw #define M_SYS_SER0_RSTB_EN _SB_MAKEMASK1(13) 160 1.3.2.2 nathanw #define M_SYS_SER1_ENABLE _SB_MAKEMASK1(14) 161 1.3.2.2 nathanw #define M_SYS_SER1_RSTB_EN _SB_MAKEMASK1(15) 162 1.3.2.2 nathanw #define M_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16) 163 1.3.2.2 nathanw 164 1.3.2.2 nathanw #define S_SYS_BOOT_MODE _SB_MAKE64(17) 165 1.3.2.2 nathanw #define M_SYS_BOOT_MODE _SB_MAKEMASK(2,S_SYS_BOOT_MODE) 166 1.3.2.2 nathanw #define V_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x,S_SYS_BOOT_MODE) 167 1.3.2.2 nathanw #define G_SYS_BOOT_MODE(x) _SB_GETVALUE(x,S_SYS_BOOT_MODE,M_SYS_BOOT_MODE) 168 1.3.2.2 nathanw #define K_SYS_BOOT_MODE_ROM32 0 169 1.3.2.2 nathanw #define K_SYS_BOOT_MODE_ROM8 1 170 1.3.2.2 nathanw #define K_SYS_BOOT_MODE_SMBUS_SMALL 2 171 1.3.2.2 nathanw #define K_SYS_BOOT_MODE_SMBUS_BIG 3 172 1.3.2.2 nathanw 173 1.3.2.2 nathanw #define M_SYS_PCI_HOST _SB_MAKEMASK1(19) 174 1.3.2.2 nathanw #define M_SYS_PCI_ARBITER _SB_MAKEMASK1(20) 175 1.3.2.2 nathanw #define M_SYS_SOUTH_ON_LDT _SB_MAKEMASK1(21) 176 1.3.2.2 nathanw #define M_SYS_BIG_ENDIAN _SB_MAKEMASK1(22) 177 1.3.2.2 nathanw #define M_SYS_GENCLK_EN _SB_MAKEMASK1(23) 178 1.3.2.2 nathanw #define M_SYS_LDT_TEST_EN _SB_MAKEMASK1(24) 179 1.3.2.2 nathanw #define M_SYS_GEN_PARITY_EN _SB_MAKEMASK1(25) 180 1.3.2.2 nathanw 181 1.3.2.2 nathanw #define S_SYS_CONFIG 26 182 1.3.2.2 nathanw #define M_SYS_CONFIG _SB_MAKEMASK(6,S_SYS_CONFIG) 183 1.3.2.2 nathanw #define V_SYS_CONFIG(x) _SB_MAKEVALUE(x,S_SYS_CONFIG) 184 1.3.2.2 nathanw #define G_SYS_CONFIG(x) _SB_GETVALUE(x,S_SYS_CONFIG,M_SYS_CONFIG) 185 1.3.2.2 nathanw 186 1.3.2.3 thorpej /* The following bits are writable by JTAG only. */ 187 1.3.2.2 nathanw 188 1.3.2.2 nathanw #define M_SYS_CLKSTOP _SB_MAKEMASK1(32) 189 1.3.2.2 nathanw #define M_SYS_CLKSTEP _SB_MAKEMASK1(33) 190 1.3.2.2 nathanw 191 1.3.2.2 nathanw #define S_SYS_CLKCOUNT 34 192 1.3.2.2 nathanw #define M_SYS_CLKCOUNT _SB_MAKEMASK(8,S_SYS_CLKCOUNT) 193 1.3.2.2 nathanw #define V_SYS_CLKCOUNT(x) _SB_MAKEVALUE(x,S_SYS_CLKCOUNT) 194 1.3.2.2 nathanw #define G_SYS_CLKCOUNT(x) _SB_GETVALUE(x,S_SYS_CLKCOUNT,M_SYS_CLKCOUNT) 195 1.3.2.2 nathanw 196 1.3.2.2 nathanw #define M_SYS_PLL_BYPASS _SB_MAKEMASK1(42) 197 1.3.2.2 nathanw 198 1.3.2.2 nathanw #define S_SYS_PLL_IREF 43 199 1.3.2.2 nathanw #define M_SYS_PLL_IREF _SB_MAKEMASK(2,S_SYS_PLL_IREF) 200 1.3.2.2 nathanw 201 1.3.2.2 nathanw #define S_SYS_PLL_VCO 45 202 1.3.2.2 nathanw #define M_SYS_PLL_VCO _SB_MAKEMASK(2,S_SYS_PLL_VCO) 203 1.3.2.2 nathanw 204 1.3.2.2 nathanw #define S_SYS_PLL_VREG 47 205 1.3.2.2 nathanw #define M_SYS_PLL_VREG _SB_MAKEMASK(2,S_SYS_PLL_VREG) 206 1.3.2.2 nathanw 207 1.3.2.2 nathanw #define M_SYS_MEM_RESET _SB_MAKEMASK1(49) 208 1.3.2.2 nathanw #define M_SYS_L2C_RESET _SB_MAKEMASK1(50) 209 1.3.2.2 nathanw #define M_SYS_IO_RESET_0 _SB_MAKEMASK1(51) 210 1.3.2.2 nathanw #define M_SYS_IO_RESET_1 _SB_MAKEMASK1(52) 211 1.3.2.2 nathanw #define M_SYS_SCD_RESET _SB_MAKEMASK1(53) 212 1.3.2.2 nathanw 213 1.3.2.2 nathanw /* End of bits writable by JTAG only. */ 214 1.3.2.2 nathanw 215 1.3.2.2 nathanw #define M_SYS_CPU_RESET_0 _SB_MAKEMASK1(54) 216 1.3.2.2 nathanw #define M_SYS_CPU_RESET_1 _SB_MAKEMASK1(55) 217 1.3.2.2 nathanw 218 1.3.2.2 nathanw #define M_SYS_UNICPU0 _SB_MAKEMASK1(56) 219 1.3.2.2 nathanw #define M_SYS_UNICPU1 _SB_MAKEMASK1(57) 220 1.3.2.2 nathanw 221 1.3.2.2 nathanw #define M_SYS_SB_SOFTRES _SB_MAKEMASK1(58) 222 1.3.2.2 nathanw #define M_SYS_EXT_RESET _SB_MAKEMASK1(59) 223 1.3.2.2 nathanw #define M_SYS_SYSTEM_RESET _SB_MAKEMASK1(60) 224 1.3.2.2 nathanw 225 1.3.2.2 nathanw #define M_SYS_MISR_MODE _SB_MAKEMASK1(61) 226 1.3.2.2 nathanw #define M_SYS_MISR_RESET _SB_MAKEMASK1(62) 227 1.3.2.2 nathanw 228 1.3.2.2 nathanw #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 229 1.3.2.2 nathanw #define M_SYS_SW_FLAG _SB_MAKEMASK1(63) 230 1.3.2.2 nathanw #endif /* 1250 PASS2 || 112x PASS1 */ 231 1.3.2.2 nathanw 232 1.3.2.2 nathanw 233 1.3.2.2 nathanw /* 234 1.3.2.2 nathanw * Mailbox Registers (Table 4-3) 235 1.3.2.2 nathanw * Registers: SCD_MBOX_CPU_x 236 1.3.2.2 nathanw */ 237 1.3.2.2 nathanw 238 1.3.2.2 nathanw #define S_MBOX_INT_3 0 239 1.3.2.2 nathanw #define M_MBOX_INT_3 _SB_MAKEMASK(16,S_MBOX_INT_3) 240 1.3.2.2 nathanw #define S_MBOX_INT_2 16 241 1.3.2.2 nathanw #define M_MBOX_INT_2 _SB_MAKEMASK(16,S_MBOX_INT_2) 242 1.3.2.2 nathanw #define S_MBOX_INT_1 32 243 1.3.2.2 nathanw #define M_MBOX_INT_1 _SB_MAKEMASK(16,S_MBOX_INT_1) 244 1.3.2.2 nathanw #define S_MBOX_INT_0 48 245 1.3.2.2 nathanw #define M_MBOX_INT_0 _SB_MAKEMASK(16,S_MBOX_INT_0) 246 1.3.2.2 nathanw 247 1.3.2.2 nathanw /* 248 1.3.2.2 nathanw * Watchdog Registers (Table 4-8) (Table 4-9) (Table 4-10) 249 1.3.2.2 nathanw * Registers: SCD_WDOG_INIT_CNT_x 250 1.3.2.2 nathanw */ 251 1.3.2.2 nathanw 252 1.3.2.2 nathanw #define V_SCD_WDOG_FREQ 1000000 253 1.3.2.2 nathanw 254 1.3.2.2 nathanw #define S_SCD_WDOG_INIT 0 255 1.3.2.2 nathanw #define M_SCD_WDOG_INIT _SB_MAKEMASK(23,S_SCD_WDOG_INIT) 256 1.3.2.2 nathanw 257 1.3.2.2 nathanw #define S_SCD_WDOG_CNT 0 258 1.3.2.2 nathanw #define M_SCD_WDOG_CNT _SB_MAKEMASK(23,S_SCD_WDOG_CNT) 259 1.3.2.2 nathanw 260 1.3.2.2 nathanw #define M_SCD_WDOG_ENABLE _SB_MAKEMASK1(0) 261 1.3.2.2 nathanw 262 1.3.2.2 nathanw /* 263 1.3.2.2 nathanw * Timer Registers (Table 4-11) (Table 4-12) (Table 4-13) 264 1.3.2.2 nathanw */ 265 1.3.2.2 nathanw 266 1.3.2.2 nathanw #define V_SCD_TIMER_FREQ 1000000 267 1.3.2.2 nathanw 268 1.3.2.2 nathanw #define S_SCD_TIMER_INIT 0 269 1.3.2.2 nathanw #define M_SCD_TIMER_INIT _SB_MAKEMASK(20,S_SCD_TIMER_INIT) 270 1.3.2.2 nathanw #define V_SCD_TIMER_INIT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_INIT) 271 1.3.2.2 nathanw #define G_SCD_TIMER_INIT(x) _SB_GETVALUE(x,S_SCD_TIMER_INIT,M_SCD_TIMER_INIT) 272 1.3.2.2 nathanw 273 1.3.2.2 nathanw #define S_SCD_TIMER_CNT 0 274 1.3.2.2 nathanw #define M_SCD_TIMER_CNT _SB_MAKEMASK(20,S_SCD_TIMER_CNT) 275 1.3.2.2 nathanw #define V_SCD_TIMER_CNT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_CNT) 276 1.3.2.2 nathanw #define G_SCD_TIMER_CNT(x) _SB_GETVALUE(x,S_SCD_TIMER_CNT,M_SCD_TIMER_CNT) 277 1.3.2.2 nathanw 278 1.3.2.2 nathanw #define M_SCD_TIMER_ENABLE _SB_MAKEMASK1(0) 279 1.3.2.2 nathanw #define M_SCD_TIMER_MODE _SB_MAKEMASK1(1) 280 1.3.2.2 nathanw #define M_SCD_TIMER_MODE_CONTINUOUS M_SCD_TIMER_MODE 281 1.3.2.2 nathanw 282 1.3.2.2 nathanw /* 283 1.3.2.2 nathanw * System Performance Counters 284 1.3.2.2 nathanw */ 285 1.3.2.2 nathanw 286 1.3.2.2 nathanw #define S_SPC_CFG_SRC0 0 287 1.3.2.2 nathanw #define M_SPC_CFG_SRC0 _SB_MAKEMASK(8,S_SPC_CFG_SRC0) 288 1.3.2.2 nathanw #define V_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC0) 289 1.3.2.2 nathanw #define G_SPC_CFG_SRC0(x) _SB_GETVALUE(x,S_SPC_CFG_SRC0,M_SPC_CFG_SRC0) 290 1.3.2.2 nathanw 291 1.3.2.2 nathanw #define S_SPC_CFG_SRC1 8 292 1.3.2.2 nathanw #define M_SPC_CFG_SRC1 _SB_MAKEMASK(8,S_SPC_CFG_SRC1) 293 1.3.2.2 nathanw #define V_SPC_CFG_SRC1(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC1) 294 1.3.2.2 nathanw #define G_SPC_CFG_SRC1(x) _SB_GETVALUE(x,S_SPC_CFG_SRC1,M_SPC_CFG_SRC1) 295 1.3.2.2 nathanw 296 1.3.2.2 nathanw #define S_SPC_CFG_SRC2 16 297 1.3.2.2 nathanw #define M_SPC_CFG_SRC2 _SB_MAKEMASK(8,S_SPC_CFG_SRC2) 298 1.3.2.2 nathanw #define V_SPC_CFG_SRC2(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC2) 299 1.3.2.2 nathanw #define G_SPC_CFG_SRC2(x) _SB_GETVALUE(x,S_SPC_CFG_SRC2,M_SPC_CFG_SRC2) 300 1.3.2.2 nathanw 301 1.3.2.2 nathanw #define S_SPC_CFG_SRC3 24 302 1.3.2.2 nathanw #define M_SPC_CFG_SRC3 _SB_MAKEMASK(8,S_SPC_CFG_SRC3) 303 1.3.2.2 nathanw #define V_SPC_CFG_SRC3(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC3) 304 1.3.2.2 nathanw #define G_SPC_CFG_SRC3(x) _SB_GETVALUE(x,S_SPC_CFG_SRC3,M_SPC_CFG_SRC3) 305 1.3.2.2 nathanw 306 1.3.2.2 nathanw #define M_SPC_CFG_CLEAR _SB_MAKEMASK1(32) 307 1.3.2.2 nathanw #define M_SPC_CFG_ENABLE _SB_MAKEMASK1(33) 308 1.3.2.2 nathanw 309 1.3.2.2 nathanw 310 1.3.2.2 nathanw /* 311 1.3.2.2 nathanw * Bus Watcher 312 1.3.2.2 nathanw */ 313 1.3.2.2 nathanw 314 1.3.2.2 nathanw #define S_SCD_BERR_TID 8 315 1.3.2.2 nathanw #define M_SCD_BERR_TID _SB_MAKEMASK(10,S_SCD_BERR_TID) 316 1.3.2.2 nathanw #define V_SCD_BERR_TID(x) _SB_MAKEVALUE(x,S_SCD_BERR_TID) 317 1.3.2.2 nathanw #define G_SCD_BERR_TID(x) _SB_GETVALUE(x,S_SCD_BERR_TID,M_SCD_BERR_TID) 318 1.3.2.2 nathanw 319 1.3.2.2 nathanw #define S_SCD_BERR_RID 18 320 1.3.2.2 nathanw #define M_SCD_BERR_RID _SB_MAKEMASK(4,S_SCD_BERR_RID) 321 1.3.2.2 nathanw #define V_SCD_BERR_RID(x) _SB_MAKEVALUE(x,S_SCD_BERR_RID) 322 1.3.2.2 nathanw #define G_SCD_BERR_RID(x) _SB_GETVALUE(x,S_SCD_BERR_RID,M_SCD_BERR_RID) 323 1.3.2.2 nathanw 324 1.3.2.2 nathanw #define S_SCD_BERR_DCODE 22 325 1.3.2.2 nathanw #define M_SCD_BERR_DCODE _SB_MAKEMASK(3,S_SCD_BERR_DCODE) 326 1.3.2.2 nathanw #define V_SCD_BERR_DCODE(x) _SB_MAKEVALUE(x,S_SCD_BERR_DCODE) 327 1.3.2.2 nathanw #define G_SCD_BERR_DCODE(x) _SB_GETVALUE(x,S_SCD_BERR_DCODE,M_SCD_BERR_DCODE) 328 1.3.2.2 nathanw 329 1.3.2.2 nathanw #define M_SCD_BERR_MULTERRS _SB_MAKEMASK1(30) 330 1.3.2.2 nathanw 331 1.3.2.2 nathanw 332 1.3.2.2 nathanw #define S_SCD_L2ECC_CORR_D 0 333 1.3.2.2 nathanw #define M_SCD_L2ECC_CORR_D _SB_MAKEMASK(8,S_SCD_L2ECC_CORR_D) 334 1.3.2.2 nathanw #define V_SCD_L2ECC_CORR_D(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_CORR_D) 335 1.3.2.2 nathanw #define G_SCD_L2ECC_CORR_D(x) _SB_GETVALUE(x,S_SCD_L2ECC_CORR_D,M_SCD_L2ECC_CORR_D) 336 1.3.2.2 nathanw 337 1.3.2.2 nathanw #define S_SCD_L2ECC_BAD_D 8 338 1.3.2.2 nathanw #define M_SCD_L2ECC_BAD_D _SB_MAKEMASK(8,S_SCD_L2ECC_BAD_D) 339 1.3.2.2 nathanw #define V_SCD_L2ECC_BAD_D(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_BAD_D) 340 1.3.2.2 nathanw #define G_SCD_L2ECC_BAD_D(x) _SB_GETVALUE(x,S_SCD_L2ECC_BAD_D,M_SCD_L2ECC_BAD_D) 341 1.3.2.2 nathanw 342 1.3.2.2 nathanw #define S_SCD_L2ECC_CORR_T 16 343 1.3.2.2 nathanw #define M_SCD_L2ECC_CORR_T _SB_MAKEMASK(8,S_SCD_L2ECC_CORR_T) 344 1.3.2.2 nathanw #define V_SCD_L2ECC_CORR_T(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_CORR_T) 345 1.3.2.2 nathanw #define G_SCD_L2ECC_CORR_T(x) _SB_GETVALUE(x,S_SCD_L2ECC_CORR_T,M_SCD_L2ECC_CORR_T) 346 1.3.2.2 nathanw 347 1.3.2.2 nathanw #define S_SCD_L2ECC_BAD_T 24 348 1.3.2.2 nathanw #define M_SCD_L2ECC_BAD_T _SB_MAKEMASK(8,S_SCD_L2ECC_BAD_T) 349 1.3.2.2 nathanw #define V_SCD_L2ECC_BAD_T(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_BAD_T) 350 1.3.2.2 nathanw #define G_SCD_L2ECC_BAD_T(x) _SB_GETVALUE(x,S_SCD_L2ECC_BAD_T,M_SCD_L2ECC_BAD_T) 351 1.3.2.2 nathanw 352 1.3.2.2 nathanw #define S_SCD_MEM_ECC_CORR 0 353 1.3.2.2 nathanw #define M_SCD_MEM_ECC_CORR _SB_MAKEMASK(8,S_SCD_MEM_ECC_CORR) 354 1.3.2.2 nathanw #define V_SCD_MEM_ECC_CORR(x) _SB_MAKEVALUE(x,S_SCD_MEM_ECC_CORR) 355 1.3.2.2 nathanw #define G_SCD_MEM_ECC_CORR(x) _SB_GETVALUE(x,S_SCD_MEM_ECC_CORR,M_SCD_MEM_ECC_CORR) 356 1.3.2.2 nathanw 357 1.3.2.2 nathanw #define S_SCD_MEM_ECC_BAD 8 358 1.3.2.2 nathanw #define M_SCD_MEM_ECC_BAD _SB_MAKEMASK(8,S_SCD_MEM_ECC_BAD) 359 1.3.2.2 nathanw #define V_SCD_MEM_ECC_BAD(x) _SB_MAKEVALUE(x,S_SCD_MEM_ECC_BAD) 360 1.3.2.2 nathanw #define G_SCD_MEM_ECC_BAD(x) _SB_GETVALUE(x,S_SCD_MEM_ECC_BAD,M_SCD_MEM_ECC_BAD) 361 1.3.2.2 nathanw 362 1.3.2.2 nathanw #define S_SCD_MEM_BUSERR 16 363 1.3.2.2 nathanw #define M_SCD_MEM_BUSERR _SB_MAKEMASK(8,S_SCD_MEM_BUSERR) 364 1.3.2.2 nathanw #define V_SCD_MEM_BUSERR(x) _SB_MAKEVALUE(x,S_SCD_MEM_BUSERR) 365 1.3.2.2 nathanw #define G_SCD_MEM_BUSERR(x) _SB_GETVALUE(x,S_SCD_MEM_BUSERR,M_SCD_MEM_BUSERR) 366 1.3.2.2 nathanw 367 1.3.2.2 nathanw 368 1.3.2.2 nathanw /* 369 1.3.2.2 nathanw * Address Trap Registers 370 1.3.2.2 nathanw */ 371 1.3.2.2 nathanw 372 1.3.2.2 nathanw #define M_ATRAP_INDEX _SB_MAKEMASK(4,0) 373 1.3.2.2 nathanw #define M_ATRAP_ADDRESS _SB_MAKEMASK(40,0) 374 1.3.2.2 nathanw 375 1.3.2.2 nathanw #define S_ATRAP_CFG_CNT 0 376 1.3.2.2 nathanw #define M_ATRAP_CFG_CNT _SB_MAKEMASK(3,S_ATRAP_CFG_CNT) 377 1.3.2.2 nathanw #define V_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_CNT) 378 1.3.2.2 nathanw #define G_ATRAP_CFG_CNT(x) _SB_GETVALUE(x,S_ATRAP_CFG_CNT,M_ATRAP_CFG_CNT) 379 1.3.2.2 nathanw 380 1.3.2.2 nathanw #define M_ATRAP_CFG_WRITE _SB_MAKEMASK1(3) 381 1.3.2.2 nathanw #define M_ATRAP_CFG_ALL _SB_MAKEMASK1(4) 382 1.3.2.2 nathanw #define M_ATRAP_CFG_INV _SB_MAKEMASK1(5) 383 1.3.2.2 nathanw #define M_ATRAP_CFG_USESRC _SB_MAKEMASK1(6) 384 1.3.2.2 nathanw #define M_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7) 385 1.3.2.2 nathanw 386 1.3.2.2 nathanw #define S_ATRAP_CFG_AGENTID 8 387 1.3.2.2 nathanw #define M_ATRAP_CFG_AGENTID _SB_MAKEMASK(4,S_ATRAP_CFG_AGENTID) 388 1.3.2.2 nathanw #define V_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_AGENTID) 389 1.3.2.2 nathanw #define G_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x,S_ATRAP_CFG_AGENTID,M_ATRAP_CFG_AGENTID) 390 1.3.2.2 nathanw 391 1.3.2.2 nathanw #define K_BUS_AGENT_CPU0 0 392 1.3.2.2 nathanw #define K_BUS_AGENT_CPU1 1 393 1.3.2.2 nathanw #define K_BUS_AGENT_IOB0 2 394 1.3.2.2 nathanw #define K_BUS_AGENT_IOB1 3 395 1.3.2.2 nathanw #define K_BUS_AGENT_SCD 4 396 1.3.2.2 nathanw #define K_BUS_AGENT_RESERVED 5 397 1.3.2.2 nathanw #define K_BUS_AGENT_L2C 6 398 1.3.2.2 nathanw #define K_BUS_AGENT_MC 7 399 1.3.2.2 nathanw 400 1.3.2.2 nathanw #define S_ATRAP_CFG_CATTR 12 401 1.3.2.2 nathanw #define M_ATRAP_CFG_CATTR _SB_MAKEMASK(3,S_ATRAP_CFG_CATTR) 402 1.3.2.2 nathanw #define V_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_CATTR) 403 1.3.2.2 nathanw #define G_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x,S_ATRAP_CFG_CATTR,M_ATRAP_CFG_CATTR) 404 1.3.2.2 nathanw 405 1.3.2.2 nathanw #define K_ATRAP_CFG_CATTR_IGNORE 0 406 1.3.2.2 nathanw #define K_ATRAP_CFG_CATTR_UNC 1 407 1.3.2.2 nathanw #define K_ATRAP_CFG_CATTR_CACHEABLE 2 408 1.3.2.2 nathanw #define K_ATRAP_CFG_CATTR_NONCOH 3 409 1.3.2.2 nathanw #define K_ATRAP_CFG_CATTR_COHERENT 4 410 1.3.2.2 nathanw #define K_ATRAP_CFG_CATTR_NOTUNC 5 411 1.3.2.2 nathanw #define K_ATRAP_CFG_CATTR_NOTNONCOH 6 412 1.3.2.2 nathanw #define K_ATRAP_CFG_CATTR_NOTCOHERENT 7 413 1.3.2.2 nathanw 414 1.3.2.2 nathanw /* 415 1.3.2.2 nathanw * Trace Buffer Config register 416 1.3.2.2 nathanw */ 417 1.3.2.2 nathanw 418 1.3.2.2 nathanw #define M_SCD_TRACE_CFG_RESET _SB_MAKEMASK1(0) 419 1.3.2.2 nathanw #define M_SCD_TRACE_CFG_START_READ _SB_MAKEMASK1(1) 420 1.3.2.2 nathanw #define M_SCD_TRACE_CFG_START _SB_MAKEMASK1(2) 421 1.3.2.2 nathanw #define M_SCD_TRACE_CFG_STOP _SB_MAKEMASK1(3) 422 1.3.2.2 nathanw #define M_SCD_TRACE_CFG_FREEZE _SB_MAKEMASK1(4) 423 1.3.2.2 nathanw #define M_SCD_TRACE_CFG_FREEZE_FULL _SB_MAKEMASK1(5) 424 1.3.2.2 nathanw #define M_SCD_TRACE_CFG_DEBUG_FULL _SB_MAKEMASK1(6) 425 1.3.2.2 nathanw #define M_SCD_TRACE_CFG_FULL _SB_MAKEMASK1(7) 426 1.3.2.2 nathanw #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 427 1.3.2.2 nathanw #define M_SCD_TRACE_CFG_FORCECNT _SB_MAKEMASK1(8) 428 1.3.2.2 nathanw #endif /* 1250 PASS2 || 112x PASS1 */ 429 1.3.2.2 nathanw 430 1.3.2.2 nathanw #define S_SCD_TRACE_CFG_CUR_ADDR 10 431 1.3.2.2 nathanw #define M_SCD_TRACE_CFG_CUR_ADDR _SB_MAKEMASK(8,S_SCD_TRACE_CFG_CUR_ADDR) 432 1.3.2.2 nathanw #define V_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR) 433 1.3.2.2 nathanw #define G_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR,M_SCD_TRACE_CFG_CUR_ADDR) 434 1.3.2.2 nathanw 435 1.3.2.2 nathanw /* 436 1.3.2.2 nathanw * Trace Event registers 437 1.3.2.2 nathanw */ 438 1.3.2.2 nathanw 439 1.3.2.2 nathanw #define S_SCD_TREVT_ADDR_MATCH 0 440 1.3.2.2 nathanw #define M_SCD_TREVT_ADDR_MATCH _SB_MAKEMASK(4,S_SCD_TREVT_ADDR_MATCH) 441 1.3.2.2 nathanw #define V_SCD_TREVT_ADDR_MATCH(x) _SB_MAKEVALUE(x,S_SCD_TREVT_ADDR_MATCH) 442 1.3.2.2 nathanw #define G_SCD_TREVT_ADDR_MATCH(x) _SB_GETVALUE(x,S_SCD_TREVT_ADDR_MATCH,M_SCD_TREVT_ADDR_MATCH) 443 1.3.2.2 nathanw 444 1.3.2.2 nathanw #define M_SCD_TREVT_REQID_MATCH _SB_MAKEMASK1(4) 445 1.3.2.2 nathanw #define M_SCD_TREVT_DATAID_MATCH _SB_MAKEMASK1(5) 446 1.3.2.2 nathanw #define M_SCD_TREVT_RESPID_MATCH _SB_MAKEMASK1(6) 447 1.3.2.2 nathanw #define M_SCD_TREVT_INTERRUPT _SB_MAKEMASK1(7) 448 1.3.2.2 nathanw #define M_SCD_TREVT_DEBUG_PIN _SB_MAKEMASK1(9) 449 1.3.2.2 nathanw #define M_SCD_TREVT_WRITE _SB_MAKEMASK1(10) 450 1.3.2.2 nathanw #define M_SCD_TREVT_READ _SB_MAKEMASK1(11) 451 1.3.2.2 nathanw 452 1.3.2.2 nathanw #define S_SCD_TREVT_REQID 12 453 1.3.2.2 nathanw #define M_SCD_TREVT_REQID _SB_MAKEMASK(4,S_SCD_TREVT_REQID) 454 1.3.2.2 nathanw #define V_SCD_TREVT_REQID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_REQID) 455 1.3.2.2 nathanw #define G_SCD_TREVT_REQID(x) _SB_GETVALUE(x,S_SCD_TREVT_REQID,M_SCD_TREVT_REQID) 456 1.3.2.2 nathanw 457 1.3.2.2 nathanw #define S_SCD_TREVT_RESPID 16 458 1.3.2.2 nathanw #define M_SCD_TREVT_RESPID _SB_MAKEMASK(4,S_SCD_TREVT_RESPID) 459 1.3.2.2 nathanw #define V_SCD_TREVT_RESPID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_RESPID) 460 1.3.2.2 nathanw #define G_SCD_TREVT_RESPID(x) _SB_GETVALUE(x,S_SCD_TREVT_RESPID,M_SCD_TREVT_RESPID) 461 1.3.2.2 nathanw 462 1.3.2.2 nathanw #define S_SCD_TREVT_DATAID 20 463 1.3.2.2 nathanw #define M_SCD_TREVT_DATAID _SB_MAKEMASK(4,S_SCD_TREVT_DATAID) 464 1.3.2.2 nathanw #define V_SCD_TREVT_DATAID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_DATAID) 465 1.3.2.2 nathanw #define G_SCD_TREVT_DATAID(x) _SB_GETVALUE(x,S_SCD_TREVT_DATAID,M_SCD_TREVT_DATID) 466 1.3.2.2 nathanw 467 1.3.2.2 nathanw #define S_SCD_TREVT_COUNT 24 468 1.3.2.2 nathanw #define M_SCD_TREVT_COUNT _SB_MAKEMASK(8,S_SCD_TREVT_COUNT) 469 1.3.2.2 nathanw #define V_SCD_TREVT_COUNT(x) _SB_MAKEVALUE(x,S_SCD_TREVT_COUNT) 470 1.3.2.2 nathanw #define G_SCD_TREVT_COUNT(x) _SB_GETVALUE(x,S_SCD_TREVT_COUNT,M_SCD_TREVT_COUNT) 471 1.3.2.2 nathanw 472 1.3.2.2 nathanw /* 473 1.3.2.2 nathanw * Trace Sequence registers 474 1.3.2.2 nathanw */ 475 1.3.2.2 nathanw 476 1.3.2.2 nathanw #define S_SCD_TRSEQ_EVENT4 0 477 1.3.2.2 nathanw #define M_SCD_TRSEQ_EVENT4 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT4) 478 1.3.2.2 nathanw #define V_SCD_TRSEQ_EVENT4(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT4) 479 1.3.2.2 nathanw #define G_SCD_TRSEQ_EVENT4(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT4,M_SCD_TRSEQ_EVENT4) 480 1.3.2.2 nathanw 481 1.3.2.2 nathanw #define S_SCD_TRSEQ_EVENT3 4 482 1.3.2.2 nathanw #define M_SCD_TRSEQ_EVENT3 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT3) 483 1.3.2.2 nathanw #define V_SCD_TRSEQ_EVENT3(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT3) 484 1.3.2.2 nathanw #define G_SCD_TRSEQ_EVENT3(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT3,M_SCD_TRSEQ_EVENT3) 485 1.3.2.2 nathanw 486 1.3.2.2 nathanw #define S_SCD_TRSEQ_EVENT2 8 487 1.3.2.2 nathanw #define M_SCD_TRSEQ_EVENT2 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT2) 488 1.3.2.2 nathanw #define V_SCD_TRSEQ_EVENT2(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT2) 489 1.3.2.2 nathanw #define G_SCD_TRSEQ_EVENT2(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT2,M_SCD_TRSEQ_EVENT2) 490 1.3.2.2 nathanw 491 1.3.2.2 nathanw #define S_SCD_TRSEQ_EVENT1 12 492 1.3.2.2 nathanw #define M_SCD_TRSEQ_EVENT1 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT1) 493 1.3.2.2 nathanw #define V_SCD_TRSEQ_EVENT1(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT1) 494 1.3.2.2 nathanw #define G_SCD_TRSEQ_EVENT1(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT1,M_SCD_TRSEQ_EVENT1) 495 1.3.2.2 nathanw 496 1.3.2.2 nathanw #define K_SCD_TRSEQ_E0 0 497 1.3.2.2 nathanw #define K_SCD_TRSEQ_E1 1 498 1.3.2.2 nathanw #define K_SCD_TRSEQ_E2 2 499 1.3.2.2 nathanw #define K_SCD_TRSEQ_E3 3 500 1.3.2.2 nathanw #define K_SCD_TRSEQ_E0_E1 4 501 1.3.2.2 nathanw #define K_SCD_TRSEQ_E1_E2 5 502 1.3.2.2 nathanw #define K_SCD_TRSEQ_E2_E3 6 503 1.3.2.2 nathanw #define K_SCD_TRSEQ_E0_E1_E2 7 504 1.3.2.2 nathanw #define K_SCD_TRSEQ_E0_E1_E2_E3 8 505 1.3.2.2 nathanw #define K_SCD_TRSEQ_E0E1 9 506 1.3.2.2 nathanw #define K_SCD_TRSEQ_E0E1E2 10 507 1.3.2.2 nathanw #define K_SCD_TRSEQ_E0E1E2E3 11 508 1.3.2.2 nathanw #define K_SCD_TRSEQ_E0E1_E2 12 509 1.3.2.2 nathanw #define K_SCD_TRSEQ_E0E1_E2E3 13 510 1.3.2.2 nathanw #define K_SCD_TRSEQ_E0E1_E2_E3 14 511 1.3.2.2 nathanw #define K_SCD_TRSEQ_IGNORED 15 512 1.3.2.2 nathanw 513 1.3.2.2 nathanw #define K_SCD_TRSEQ_TRIGGER_ALL (V_SCD_TRSEQ_EVENT1(K_SCD_TRSEQ_IGNORED) | \ 514 1.3.2.2 nathanw V_SCD_TRSEQ_EVENT2(K_SCD_TRSEQ_IGNORED) | \ 515 1.3.2.2 nathanw V_SCD_TRSEQ_EVENT3(K_SCD_TRSEQ_IGNORED) | \ 516 1.3.2.2 nathanw V_SCD_TRSEQ_EVENT4(K_SCD_TRSEQ_IGNORED)) 517 1.3.2.2 nathanw 518 1.3.2.2 nathanw #define S_SCD_TRSEQ_FUNCTION 16 519 1.3.2.2 nathanw #define M_SCD_TRSEQ_FUNCTION _SB_MAKEMASK(4,S_SCD_TRSEQ_FUNCTION) 520 1.3.2.2 nathanw #define V_SCD_TRSEQ_FUNCTION(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_FUNCTION) 521 1.3.2.2 nathanw #define G_SCD_TRSEQ_FUNCTION(x) _SB_GETVALUE(x,S_SCD_TRSEQ_FUNCTION,M_SCD_TRSEQ_FUNCTION) 522 1.3.2.2 nathanw 523 1.3.2.2 nathanw #define K_SCD_TRSEQ_FUNC_NOP 0 524 1.3.2.2 nathanw #define K_SCD_TRSEQ_FUNC_START 1 525 1.3.2.2 nathanw #define K_SCD_TRSEQ_FUNC_STOP 2 526 1.3.2.2 nathanw #define K_SCD_TRSEQ_FUNC_FREEZE 3 527 1.3.2.2 nathanw 528 1.3.2.2 nathanw #define V_SCD_TRSEQ_FUNC_NOP V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_NOP) 529 1.3.2.2 nathanw #define V_SCD_TRSEQ_FUNC_START V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_START) 530 1.3.2.2 nathanw #define V_SCD_TRSEQ_FUNC_STOP V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_STOP) 531 1.3.2.2 nathanw #define V_SCD_TRSEQ_FUNC_FREEZE V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_FREEZE) 532 1.3.2.2 nathanw 533 1.3.2.2 nathanw #define M_SCD_TRSEQ_ASAMPLE _SB_MAKEMASK1(18) 534 1.3.2.2 nathanw #define M_SCD_TRSEQ_DSAMPLE _SB_MAKEMASK1(19) 535 1.3.2.2 nathanw #define M_SCD_TRSEQ_DEBUGPIN _SB_MAKEMASK1(20) 536 1.3.2.2 nathanw #define M_SCD_TRSEQ_DEBUGCPU _SB_MAKEMASK1(21) 537 1.3.2.2 nathanw #define M_SCD_TRSEQ_CLEARUSE _SB_MAKEMASK1(22) 538 1.3.2.2 nathanw 539 1.3.2.2 nathanw #endif 540
Indexes created Wed Oct 29 12:09:47 GMT 2025