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      1 /* $NetBSD: iocreg.h,v 1.2 2005/12/11 12:18:53 christos Exp $	 */
      2 
      3 /*
      4  * Copyright (c) 2003 Christopher Sekiya
      5  * Copyright (c) 2001 Rafal K. Boni
      6  * All rights reserved.
      7  *
      8  * Redistribution and use in source and binary forms, with or without
      9  * modification, are permitted provided that the following conditions
     10  * are met:
     11  * 1. Redistributions of source code must retain the above copyright
     12  *    notice, this list of conditions and the following disclaimer.
     13  * 2. Redistributions in binary form must reproduce the above copyright
     14  *    notice, this list of conditions and the following disclaimer in the
     15  *    documentation and/or other materials provided with the distribution.
     16  * 3. The name of the author may not be used to endorse or promote products
     17  *    derived from this software without specific prior written permission.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     20  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     21  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     22  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     23  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     24  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     25  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     26  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     27  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     28  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     29  */
     30 
     31 #ifndef _ARCH_SGIMIPS_IOC_IOCREG_H_
     32 #define	_ARCH_SGIMIPS_IOC_IOCREG_H_
     33 
     34 /*
     35  * IOC1/2 memory map.
     36  *
     37  * The IOC1/2 is connected to the HPC#0, PBus channel 6, so these registers
     38  * are based from the external register window for PBus channel 6 on HPC#0.
     39  *
     40  */
     41 
     42 #define IOC_PLP_REGS			0x00	/* Parallel port registers */
     43 #define IOC_PLP_REGS_SIZE		0x2c
     44 
     45 #define IOC_PLP_DATA			0x00	/* Data register */
     46 #define IOC_PLP_CTL			0x04	/* Control register */
     47 #define IOC_PLP_STAT			0x08	/* Status register */
     48 #define IOC_PLP_DMACTL			0x0c	/* DMA control register */
     49 #define IOC_PLP_INTSTAT			0x10	/* Interrupt status register */
     50 #define IOC_PLP_INTMASK			0x14	/* Interrupt mask register */
     51 #define IOC_PLP_TIMER1			0x18	/* Timer 1 register */
     52 #define IOC_PLP_TIMER2			0x1c	/* Timer 2 register */
     53 #define IOC_PLP_TIMER3			0x20	/* Timer 3 register */
     54 #define IOC_PLP_TIMER4			0x24	/* Timer 4 register */
     55 
     56 #define IOC_SERIAL_REGS			0x30	/* Serial port registers */
     57 #define IOC_SERIAL_REGS_SIZE		0x0c
     58 
     59 #define IOC_SERIAL_PORT1_CMD		0x00	/* Port 1 command transfer */
     60 #define IOC_SERIAL_PORT1_DATA		0x04	/* Port 1 data transfer */
     61 #define IOC_SERIAL_PORT2_CMD		0x08	/* Port 2 command transfer */
     62 #define IOC_SERIAL_PORT2_DATA		0x0c	/* Port 2 data transfer */
     63 
     64 #define IOC_KB_REGS			0x40	/* Keyboard/mouse registers */
     65 #define IOC_KB_REGS_SIZE		0x08
     66 
     67 /* Miscellaneous registers */
     68 
     69 #define IOC_MISC_REGS			0x48	/* Misc. IOC regs */
     70 #define IOC_MISC_REGS_SIZE		0x34
     71 
     72 #define IOC_GCSEL			0x48	/* General select register */
     73 
     74 #define IOC_GCREG			0x4c	/* General control register */
     75 
     76 #define IOC_PANEL			0x50	/* Front Panel register */
     77 #define IOC_PANEL_POWER_STATE		0x01
     78 #define IOC_PANEL_POWER_IRQ		0x02
     79 #define IOC_PANEL_VDOWN_IRQ		0x10
     80 #define IOC_PANEL_VDOWN_HOLD		0x20
     81 #define IOC_PANEL_VUP_IRQ		0x40
     82 #define IOC_PANEL_VUP_HOLD		0x80
     83 
     84 #define IOC_SYSID			0x58	/* System ID register */
     85 #define IOC_SYSID_SYSTYPE		0x01	/* 0: Sapphire, 1: Full House */
     86 #define IOC_SYSID_BOARDREV		0x1e
     87 #define IOC_SYSID_BOARDREV_SHIFT	1
     88 #define IOC_SYSID_CHIPREV		0xe0
     89 #define IOC_SYSID_CHIPREV_SHIFT		5
     90 
     91 #define IOC_READ			0x60	/* Read register */
     92 #define IOC_READ_SCSI0_POWER		0x10
     93 #define IOC_READ_SCSI1_POWER		0x20
     94 #define IOC_READ_ENET_POWER		0x40
     95 #define IOC_READ_ENET_LINK		0x80
     96 
     97 #define IOC_DMASEL			0x68	/* DMA select register */
     98 #define IOC_DMASEL_ISDN_B		0x01
     99 #define IOC_DMASEL_ISDN_A		0x02
    100 #define IOC_DMASEL_PARALLEL		0x04
    101 #define IOC_DMASEL_SERIAL_10MHZ		0x00
    102 #define IOC_DMASEL_SERIAL_6MHZ		0x10
    103 #define IOC_DMASEL_SERIAL_EXTERNAL	0x20
    104 
    105 #define IOC_RESET			0x70	/* Reset register */
    106 #define IOC_RESET_PARALLEL		0x01
    107 #define IOC_RESET_PCKBC			0x02
    108 #define IOC_RESET_EISA			0x04
    109 #define IOC_RESET_ISDN			0x08
    110 #define IOC_RESET_LED_GREEN		0x10
    111 #define IOC_RESET_LED_RED		0x20
    112 #define IOC_RESET_LED_ORANGE		0x40
    113 
    114 #define IOC_WRITE			0x78	/* Write register */
    115 #define IOC_WRITE_ENET_NTH		0x01
    116 #define IOC_WRITE_ENET_UTP		0x02
    117 #define IOC_WRITE_ENET_AUI		0x04
    118 #define IOC_WRITE_ENET_AUTO		0x08
    119 #define IOC_WRITE_PC_UART2		0x10
    120 #define IOC_WRITE_PC_UART1		0x20
    121 #define IOC_WRITE_MARGIN_LOW		0x40
    122 #define IOC_WRITE_MARGIN_HIGH		0x80
    123 
    124 #endif				/* _ARCH_SGIMIPS_IOC_IOCREG_H_ */
    125