1 /* $NetBSD: smu7_fusion.h,v 1.3 2021/12/18 23:45:43 riastradh Exp $ */ 2 3 /* 4 * Copyright 2013 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #ifndef SMU7_FUSION_H 27 #define SMU7_FUSION_H 28 29 #include "smu7.h" 30 31 #pragma pack(push, 1) 32 33 #define SMU7_DTE_ITERATIONS 5 34 #define SMU7_DTE_SOURCES 5 35 #define SMU7_DTE_SINKS 3 36 #define SMU7_NUM_CPU_TES 2 37 #define SMU7_NUM_GPU_TES 1 38 #define SMU7_NUM_NON_TES 2 39 40 // All 'soft registers' should be uint32_t. 41 struct SMU7_SoftRegisters 42 { 43 uint32_t RefClockFrequency; 44 uint32_t PmTimerP; 45 uint32_t FeatureEnables; 46 uint32_t HandshakeDisables; 47 48 uint8_t DisplayPhy1Config; 49 uint8_t DisplayPhy2Config; 50 uint8_t DisplayPhy3Config; 51 uint8_t DisplayPhy4Config; 52 53 uint8_t DisplayPhy5Config; 54 uint8_t DisplayPhy6Config; 55 uint8_t DisplayPhy7Config; 56 uint8_t DisplayPhy8Config; 57 58 uint32_t AverageGraphicsA; 59 uint32_t AverageMemoryA; 60 uint32_t AverageGioA; 61 62 uint8_t SClkDpmEnabledLevels; 63 uint8_t MClkDpmEnabledLevels; 64 uint8_t LClkDpmEnabledLevels; 65 uint8_t PCIeDpmEnabledLevels; 66 67 uint8_t UVDDpmEnabledLevels; 68 uint8_t SAMUDpmEnabledLevels; 69 uint8_t ACPDpmEnabledLevels; 70 uint8_t VCEDpmEnabledLevels; 71 72 uint32_t DRAM_LOG_ADDR_H; 73 uint32_t DRAM_LOG_ADDR_L; 74 uint32_t DRAM_LOG_PHY_ADDR_H; 75 uint32_t DRAM_LOG_PHY_ADDR_L; 76 uint32_t DRAM_LOG_BUFF_SIZE; 77 uint32_t UlvEnterC; 78 uint32_t UlvTime; 79 uint32_t Reserved[3]; 80 81 }; 82 83 typedef struct SMU7_SoftRegisters SMU7_SoftRegisters; 84 85 struct SMU7_Fusion_GraphicsLevel 86 { 87 uint32_t MinVddNb; 88 89 uint32_t SclkFrequency; 90 91 uint8_t Vid; 92 uint8_t VidOffset; 93 uint16_t AT; 94 95 uint8_t PowerThrottle; 96 uint8_t GnbSlow; 97 uint8_t ForceNbPs1; 98 uint8_t SclkDid; 99 100 uint8_t DisplayWatermark; 101 uint8_t EnabledForActivity; 102 uint8_t EnabledForThrottle; 103 uint8_t UpH; 104 105 uint8_t DownH; 106 uint8_t VoltageDownH; 107 uint8_t DeepSleepDivId; 108 109 uint8_t ClkBypassCntl; 110 111 uint32_t reserved; 112 }; 113 114 typedef struct SMU7_Fusion_GraphicsLevel SMU7_Fusion_GraphicsLevel; 115 116 struct SMU7_Fusion_GIOLevel 117 { 118 uint8_t EnabledForActivity; 119 uint8_t LclkDid; 120 uint8_t Vid; 121 uint8_t VoltageDownH; 122 123 uint32_t MinVddNb; 124 125 uint16_t ResidencyCounter; 126 uint8_t UpH; 127 uint8_t DownH; 128 129 uint32_t LclkFrequency; 130 131 uint8_t ActivityLevel; 132 uint8_t EnabledForThrottle; 133 134 uint8_t ClkBypassCntl; 135 136 uint8_t padding; 137 }; 138 139 typedef struct SMU7_Fusion_GIOLevel SMU7_Fusion_GIOLevel; 140 141 // UVD VCLK/DCLK state (level) definition. 142 struct SMU7_Fusion_UvdLevel 143 { 144 uint32_t VclkFrequency; 145 uint32_t DclkFrequency; 146 uint16_t MinVddNb; 147 uint8_t VclkDivider; 148 uint8_t DclkDivider; 149 150 uint8_t VClkBypassCntl; 151 uint8_t DClkBypassCntl; 152 153 uint8_t padding[2]; 154 155 }; 156 157 typedef struct SMU7_Fusion_UvdLevel SMU7_Fusion_UvdLevel; 158 159 // Clocks for other external blocks (VCE, ACP, SAMU). 160 struct SMU7_Fusion_ExtClkLevel 161 { 162 uint32_t Frequency; 163 uint16_t MinVoltage; 164 uint8_t Divider; 165 uint8_t ClkBypassCntl; 166 167 uint32_t Reserved; 168 }; 169 typedef struct SMU7_Fusion_ExtClkLevel SMU7_Fusion_ExtClkLevel; 170 171 struct SMU7_Fusion_ACPILevel 172 { 173 uint32_t Flags; 174 uint32_t MinVddNb; 175 uint32_t SclkFrequency; 176 uint8_t SclkDid; 177 uint8_t GnbSlow; 178 uint8_t ForceNbPs1; 179 uint8_t DisplayWatermark; 180 uint8_t DeepSleepDivId; 181 uint8_t padding[3]; 182 }; 183 184 typedef struct SMU7_Fusion_ACPILevel SMU7_Fusion_ACPILevel; 185 186 struct SMU7_Fusion_NbDpm 187 { 188 uint8_t DpmXNbPsHi; 189 uint8_t DpmXNbPsLo; 190 uint8_t Dpm0PgNbPsHi; 191 uint8_t Dpm0PgNbPsLo; 192 uint8_t EnablePsi1; 193 uint8_t SkipDPM0; 194 uint8_t SkipPG; 195 uint8_t Hysteresis; 196 uint8_t EnableDpmPstatePoll; 197 uint8_t padding[3]; 198 }; 199 200 typedef struct SMU7_Fusion_NbDpm SMU7_Fusion_NbDpm; 201 202 struct SMU7_Fusion_StateInfo 203 { 204 uint32_t SclkFrequency; 205 uint32_t LclkFrequency; 206 uint32_t VclkFrequency; 207 uint32_t DclkFrequency; 208 uint32_t SamclkFrequency; 209 uint32_t AclkFrequency; 210 uint32_t EclkFrequency; 211 uint8_t DisplayWatermark; 212 uint8_t McArbIndex; 213 int8_t SclkIndex; 214 int8_t MclkIndex; 215 }; 216 217 typedef struct SMU7_Fusion_StateInfo SMU7_Fusion_StateInfo; 218 219 struct SMU7_Fusion_DpmTable 220 { 221 uint32_t SystemFlags; 222 223 SMU7_PIDController GraphicsPIDController; 224 SMU7_PIDController GioPIDController; 225 226 uint8_t GraphicsDpmLevelCount; 227 uint8_t GIOLevelCount; 228 uint8_t UvdLevelCount; 229 uint8_t VceLevelCount; 230 231 uint8_t AcpLevelCount; 232 uint8_t SamuLevelCount; 233 uint16_t FpsHighT; 234 235 SMU7_Fusion_GraphicsLevel GraphicsLevel [SMU__NUM_SCLK_DPM_STATE]; 236 SMU7_Fusion_ACPILevel ACPILevel; 237 SMU7_Fusion_UvdLevel UvdLevel [SMU7_MAX_LEVELS_UVD]; 238 SMU7_Fusion_ExtClkLevel VceLevel [SMU7_MAX_LEVELS_VCE]; 239 SMU7_Fusion_ExtClkLevel AcpLevel [SMU7_MAX_LEVELS_ACP]; 240 SMU7_Fusion_ExtClkLevel SamuLevel [SMU7_MAX_LEVELS_SAMU]; 241 242 uint8_t UvdBootLevel; 243 uint8_t VceBootLevel; 244 uint8_t AcpBootLevel; 245 uint8_t SamuBootLevel; 246 uint8_t UVDInterval; 247 uint8_t VCEInterval; 248 uint8_t ACPInterval; 249 uint8_t SAMUInterval; 250 251 uint8_t GraphicsBootLevel; 252 uint8_t GraphicsInterval; 253 uint8_t GraphicsThermThrottleEnable; 254 uint8_t GraphicsVoltageChangeEnable; 255 256 uint8_t GraphicsClkSlowEnable; 257 uint8_t GraphicsClkSlowDivider; 258 uint16_t FpsLowT; 259 260 uint32_t DisplayCac; 261 uint32_t LowSclkInterruptT; 262 263 uint32_t DRAM_LOG_ADDR_H; 264 uint32_t DRAM_LOG_ADDR_L; 265 uint32_t DRAM_LOG_PHY_ADDR_H; 266 uint32_t DRAM_LOG_PHY_ADDR_L; 267 uint32_t DRAM_LOG_BUFF_SIZE; 268 269 }; 270 271 struct SMU7_Fusion_GIODpmTable 272 { 273 274 SMU7_Fusion_GIOLevel GIOLevel [SMU7_MAX_LEVELS_GIO]; 275 276 SMU7_PIDController GioPIDController; 277 278 uint32_t GIOLevelCount; 279 280 uint8_t Enable; 281 uint8_t GIOVoltageChangeEnable; 282 uint8_t GIOBootLevel; 283 uint8_t padding; 284 uint8_t padding1[2]; 285 uint8_t TargetState; 286 uint8_t CurrenttState; 287 uint8_t ThrottleOnHtc; 288 uint8_t ThermThrottleStatus; 289 uint8_t ThermThrottleTempSelect; 290 uint8_t ThermThrottleEnable; 291 uint16_t TemperatureLimitHigh; 292 uint16_t TemperatureLimitLow; 293 294 }; 295 296 typedef struct SMU7_Fusion_DpmTable SMU7_Fusion_DpmTable; 297 typedef struct SMU7_Fusion_GIODpmTable SMU7_Fusion_GIODpmTable; 298 299 #pragma pack(pop) 300 301 #endif 302 303
Indexes created Sat Sep 20 22:09:52 GMT 2025