1 /* $NetBSD: vc4_drm.h,v 1.2 2021/12/18 23:45:46 riastradh Exp $ */ 2 3 /* 4 * Copyright 2014-2015 Broadcom 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 23 * IN THE SOFTWARE. 24 */ 25 26 #ifndef _UAPI_VC4_DRM_H_ 27 #define _UAPI_VC4_DRM_H_ 28 29 #include "drm.h" 30 31 #if defined(__cplusplus) 32 extern "C" { 33 #endif 34 35 #define DRM_VC4_SUBMIT_CL 0x00 36 #define DRM_VC4_WAIT_SEQNO 0x01 37 #define DRM_VC4_WAIT_BO 0x02 38 #define DRM_VC4_CREATE_BO 0x03 39 #define DRM_VC4_MMAP_BO 0x04 40 #define DRM_VC4_CREATE_SHADER_BO 0x05 41 #define DRM_VC4_GET_HANG_STATE 0x06 42 #define DRM_VC4_GET_PARAM 0x07 43 #define DRM_VC4_SET_TILING 0x08 44 #define DRM_VC4_GET_TILING 0x09 45 #define DRM_VC4_LABEL_BO 0x0a 46 #define DRM_VC4_GEM_MADVISE 0x0b 47 #define DRM_VC4_PERFMON_CREATE 0x0c 48 #define DRM_VC4_PERFMON_DESTROY 0x0d 49 #define DRM_VC4_PERFMON_GET_VALUES 0x0e 50 51 #define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl) 52 #define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno) 53 #define DRM_IOCTL_VC4_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo) 54 #define DRM_IOCTL_VC4_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_BO, struct drm_vc4_create_bo) 55 #define DRM_IOCTL_VC4_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo) 56 #define DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo) 57 #define DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state) 58 #define DRM_IOCTL_VC4_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_PARAM, struct drm_vc4_get_param) 59 #define DRM_IOCTL_VC4_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SET_TILING, struct drm_vc4_set_tiling) 60 #define DRM_IOCTL_VC4_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_TILING, struct drm_vc4_get_tiling) 61 #define DRM_IOCTL_VC4_LABEL_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_LABEL_BO, struct drm_vc4_label_bo) 62 #define DRM_IOCTL_VC4_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GEM_MADVISE, struct drm_vc4_gem_madvise) 63 #define DRM_IOCTL_VC4_PERFMON_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_CREATE, struct drm_vc4_perfmon_create) 64 #define DRM_IOCTL_VC4_PERFMON_DESTROY DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_DESTROY, struct drm_vc4_perfmon_destroy) 65 #define DRM_IOCTL_VC4_PERFMON_GET_VALUES DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_GET_VALUES, struct drm_vc4_perfmon_get_values) 66 67 struct drm_vc4_submit_rcl_surface { 68 __u32 hindex; /* Handle index, or ~0 if not present. */ 69 __u32 offset; /* Offset to start of buffer. */ 70 /* 71 * Bits for either render config (color_write) or load/store packet. 72 * Bits should all be 0 for MSAA load/stores. 73 */ 74 __u16 bits; 75 76 #define VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES (1 << 0) 77 __u16 flags; 78 }; 79 80 /** 81 * struct drm_vc4_submit_cl - ioctl argument for submitting commands to the 3D 82 * engine. 83 * 84 * Drivers typically use GPU BOs to store batchbuffers / command lists and 85 * their associated state. However, because the VC4 lacks an MMU, we have to 86 * do validation of memory accesses by the GPU commands. If we were to store 87 * our commands in BOs, we'd need to do uncached readback from them to do the 88 * validation process, which is too expensive. Instead, userspace accumulates 89 * commands and associated state in plain memory, then the kernel copies the 90 * data to its own address space, and then validates and stores it in a GPU 91 * BO. 92 */ 93 struct drm_vc4_submit_cl { 94 /* Pointer to the binner command list. 95 * 96 * This is the first set of commands executed, which runs the 97 * coordinate shader to determine where primitives land on the screen, 98 * then writes out the state updates and draw calls necessary per tile 99 * to the tile allocation BO. 100 */ 101 __u64 bin_cl; 102 103 /* Pointer to the shader records. 104 * 105 * Shader records are the structures read by the hardware that contain 106 * pointers to uniforms, shaders, and vertex attributes. The 107 * reference to the shader record has enough information to determine 108 * how many pointers are necessary (fixed number for shaders/uniforms, 109 * and an attribute count), so those BO indices into bo_handles are 110 * just stored as __u32s before each shader record passed in. 111 */ 112 __u64 shader_rec; 113 114 /* Pointer to uniform data and texture handles for the textures 115 * referenced by the shader. 116 * 117 * For each shader state record, there is a set of uniform data in the 118 * order referenced by the record (FS, VS, then CS). Each set of 119 * uniform data has a __u32 index into bo_handles per texture 120 * sample operation, in the order the QPU_W_TMUn_S writes appear in 121 * the program. Following the texture BO handle indices is the actual 122 * uniform data. 123 * 124 * The individual uniform state blocks don't have sizes passed in, 125 * because the kernel has to determine the sizes anyway during shader 126 * code validation. 127 */ 128 __u64 uniforms; 129 __u64 bo_handles; 130 131 /* Size in bytes of the binner command list. */ 132 __u32 bin_cl_size; 133 /* Size in bytes of the set of shader records. */ 134 __u32 shader_rec_size; 135 /* Number of shader records. 136 * 137 * This could just be computed from the contents of shader_records and 138 * the address bits of references to them from the bin CL, but it 139 * keeps the kernel from having to resize some allocations it makes. 140 */ 141 __u32 shader_rec_count; 142 /* Size in bytes of the uniform state. */ 143 __u32 uniforms_size; 144 145 /* Number of BO handles passed in (size is that times 4). */ 146 __u32 bo_handle_count; 147 148 /* RCL setup: */ 149 __u16 width; 150 __u16 height; 151 __u8 min_x_tile; 152 __u8 min_y_tile; 153 __u8 max_x_tile; 154 __u8 max_y_tile; 155 struct drm_vc4_submit_rcl_surface color_read; 156 struct drm_vc4_submit_rcl_surface color_write; 157 struct drm_vc4_submit_rcl_surface zs_read; 158 struct drm_vc4_submit_rcl_surface zs_write; 159 struct drm_vc4_submit_rcl_surface msaa_color_write; 160 struct drm_vc4_submit_rcl_surface msaa_zs_write; 161 __u32 clear_color[2]; 162 __u32 clear_z; 163 __u8 clear_s; 164 165 __u32 pad:24; 166 167 #define VC4_SUBMIT_CL_USE_CLEAR_COLOR (1 << 0) 168 /* By default, the kernel gets to choose the order that the tiles are 169 * rendered in. If this is set, then the tiles will be rendered in a 170 * raster order, with the right-to-left vs left-to-right and 171 * top-to-bottom vs bottom-to-top dictated by 172 * VC4_SUBMIT_CL_RCL_ORDER_INCREASING_*. This allows overlapping 173 * blits to be implemented using the 3D engine. 174 */ 175 #define VC4_SUBMIT_CL_FIXED_RCL_ORDER (1 << 1) 176 #define VC4_SUBMIT_CL_RCL_ORDER_INCREASING_X (1 << 2) 177 #define VC4_SUBMIT_CL_RCL_ORDER_INCREASING_Y (1 << 3) 178 __u32 flags; 179 180 /* Returned value of the seqno of this render job (for the 181 * wait ioctl). 182 */ 183 __u64 seqno; 184 185 /* ID of the perfmon to attach to this job. 0 means no perfmon. */ 186 __u32 perfmonid; 187 188 /* Syncobj handle to wait on. If set, processing of this render job 189 * will not start until the syncobj is signaled. 0 means ignore. 190 */ 191 __u32 in_sync; 192 193 /* Syncobj handle to export fence to. If set, the fence in the syncobj 194 * will be replaced with a fence that signals upon completion of this 195 * render job. 0 means ignore. 196 */ 197 __u32 out_sync; 198 199 __u32 pad2; 200 }; 201 202 /** 203 * struct drm_vc4_wait_seqno - ioctl argument for waiting for 204 * DRM_VC4_SUBMIT_CL completion using its returned seqno. 205 * 206 * timeout_ns is the timeout in nanoseconds, where "0" means "don't 207 * block, just return the status." 208 */ 209 struct drm_vc4_wait_seqno { 210 __u64 seqno; 211 __u64 timeout_ns; 212 }; 213 214 /** 215 * struct drm_vc4_wait_bo - ioctl argument for waiting for 216 * completion of the last DRM_VC4_SUBMIT_CL on a BO. 217 * 218 * This is useful for cases where multiple processes might be 219 * rendering to a BO and you want to wait for all rendering to be 220 * completed. 221 */ 222 struct drm_vc4_wait_bo { 223 __u32 handle; 224 __u32 pad; 225 __u64 timeout_ns; 226 }; 227 228 /** 229 * struct drm_vc4_create_bo - ioctl argument for creating VC4 BOs. 230 * 231 * There are currently no values for the flags argument, but it may be 232 * used in a future extension. 233 */ 234 struct drm_vc4_create_bo { 235 __u32 size; 236 __u32 flags; 237 /** Returned GEM handle for the BO. */ 238 __u32 handle; 239 __u32 pad; 240 }; 241 242 /** 243 * struct drm_vc4_mmap_bo - ioctl argument for mapping VC4 BOs. 244 * 245 * This doesn't actually perform an mmap. Instead, it returns the 246 * offset you need to use in an mmap on the DRM device node. This 247 * means that tools like valgrind end up knowing about the mapped 248 * memory. 249 * 250 * There are currently no values for the flags argument, but it may be 251 * used in a future extension. 252 */ 253 struct drm_vc4_mmap_bo { 254 /** Handle for the object being mapped. */ 255 __u32 handle; 256 __u32 flags; 257 /** offset into the drm node to use for subsequent mmap call. */ 258 __u64 offset; 259 }; 260 261 /** 262 * struct drm_vc4_create_shader_bo - ioctl argument for creating VC4 263 * shader BOs. 264 * 265 * Since allowing a shader to be overwritten while it's also being 266 * executed from would allow privlege escalation, shaders must be 267 * created using this ioctl, and they can't be mmapped later. 268 */ 269 struct drm_vc4_create_shader_bo { 270 /* Size of the data argument. */ 271 __u32 size; 272 /* Flags, currently must be 0. */ 273 __u32 flags; 274 275 /* Pointer to the data. */ 276 __u64 data; 277 278 /** Returned GEM handle for the BO. */ 279 __u32 handle; 280 /* Pad, must be 0. */ 281 __u32 pad; 282 }; 283 284 struct drm_vc4_get_hang_state_bo { 285 __u32 handle; 286 __u32 paddr; 287 __u32 size; 288 __u32 pad; 289 }; 290 291 /** 292 * struct drm_vc4_hang_state - ioctl argument for collecting state 293 * from a GPU hang for analysis. 294 */ 295 struct drm_vc4_get_hang_state { 296 /** Pointer to array of struct drm_vc4_get_hang_state_bo. */ 297 __u64 bo; 298 /** 299 * On input, the size of the bo array. Output is the number 300 * of bos to be returned. 301 */ 302 __u32 bo_count; 303 304 __u32 start_bin, start_render; 305 306 __u32 ct0ca, ct0ea; 307 __u32 ct1ca, ct1ea; 308 __u32 ct0cs, ct1cs; 309 __u32 ct0ra0, ct1ra0; 310 311 __u32 bpca, bpcs; 312 __u32 bpoa, bpos; 313 314 __u32 vpmbase; 315 316 __u32 dbge; 317 __u32 fdbgo; 318 __u32 fdbgb; 319 __u32 fdbgr; 320 __u32 fdbgs; 321 __u32 errstat; 322 323 /* Pad that we may save more registers into in the future. */ 324 __u32 pad[16]; 325 }; 326 327 #define DRM_VC4_PARAM_V3D_IDENT0 0 328 #define DRM_VC4_PARAM_V3D_IDENT1 1 329 #define DRM_VC4_PARAM_V3D_IDENT2 2 330 #define DRM_VC4_PARAM_SUPPORTS_BRANCHES 3 331 #define DRM_VC4_PARAM_SUPPORTS_ETC1 4 332 #define DRM_VC4_PARAM_SUPPORTS_THREADED_FS 5 333 #define DRM_VC4_PARAM_SUPPORTS_FIXED_RCL_ORDER 6 334 #define DRM_VC4_PARAM_SUPPORTS_MADVISE 7 335 #define DRM_VC4_PARAM_SUPPORTS_PERFMON 8 336 337 struct drm_vc4_get_param { 338 __u32 param; 339 __u32 pad; 340 __u64 value; 341 }; 342 343 struct drm_vc4_get_tiling { 344 __u32 handle; 345 __u32 flags; 346 __u64 modifier; 347 }; 348 349 struct drm_vc4_set_tiling { 350 __u32 handle; 351 __u32 flags; 352 __u64 modifier; 353 }; 354 355 /** 356 * struct drm_vc4_label_bo - Attach a name to a BO for debug purposes. 357 */ 358 struct drm_vc4_label_bo { 359 __u32 handle; 360 __u32 len; 361 __u64 name; 362 }; 363 364 /* 365 * States prefixed with '__' are internal states and cannot be passed to the 366 * DRM_IOCTL_VC4_GEM_MADVISE ioctl. 367 */ 368 #define VC4_MADV_WILLNEED 0 369 #define VC4_MADV_DONTNEED 1 370 #define __VC4_MADV_PURGED 2 371 #define __VC4_MADV_NOTSUPP 3 372 373 struct drm_vc4_gem_madvise { 374 __u32 handle; 375 __u32 madv; 376 __u32 retained; 377 __u32 pad; 378 }; 379 380 enum { 381 VC4_PERFCNT_FEP_VALID_PRIMS_NO_RENDER, 382 VC4_PERFCNT_FEP_VALID_PRIMS_RENDER, 383 VC4_PERFCNT_FEP_CLIPPED_QUADS, 384 VC4_PERFCNT_FEP_VALID_QUADS, 385 VC4_PERFCNT_TLB_QUADS_NOT_PASSING_STENCIL, 386 VC4_PERFCNT_TLB_QUADS_NOT_PASSING_Z_AND_STENCIL, 387 VC4_PERFCNT_TLB_QUADS_PASSING_Z_AND_STENCIL, 388 VC4_PERFCNT_TLB_QUADS_ZERO_COVERAGE, 389 VC4_PERFCNT_TLB_QUADS_NON_ZERO_COVERAGE, 390 VC4_PERFCNT_TLB_QUADS_WRITTEN_TO_COLOR_BUF, 391 VC4_PERFCNT_PLB_PRIMS_OUTSIDE_VIEWPORT, 392 VC4_PERFCNT_PLB_PRIMS_NEED_CLIPPING, 393 VC4_PERFCNT_PSE_PRIMS_REVERSED, 394 VC4_PERFCNT_QPU_TOTAL_IDLE_CYCLES, 395 VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_VERTEX_COORD_SHADING, 396 VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_FRAGMENT_SHADING, 397 VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_EXEC_VALID_INST, 398 VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_TMUS, 399 VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_SCOREBOARD, 400 VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_VARYINGS, 401 VC4_PERFCNT_QPU_TOTAL_INST_CACHE_HIT, 402 VC4_PERFCNT_QPU_TOTAL_INST_CACHE_MISS, 403 VC4_PERFCNT_QPU_TOTAL_UNIFORM_CACHE_HIT, 404 VC4_PERFCNT_QPU_TOTAL_UNIFORM_CACHE_MISS, 405 VC4_PERFCNT_TMU_TOTAL_TEXT_QUADS_PROCESSED, 406 VC4_PERFCNT_TMU_TOTAL_TEXT_CACHE_MISS, 407 VC4_PERFCNT_VPM_TOTAL_CLK_CYCLES_VDW_STALLED, 408 VC4_PERFCNT_VPM_TOTAL_CLK_CYCLES_VCD_STALLED, 409 VC4_PERFCNT_L2C_TOTAL_L2_CACHE_HIT, 410 VC4_PERFCNT_L2C_TOTAL_L2_CACHE_MISS, 411 VC4_PERFCNT_NUM_EVENTS, 412 }; 413 414 #define DRM_VC4_MAX_PERF_COUNTERS 16 415 416 struct drm_vc4_perfmon_create { 417 __u32 id; 418 __u32 ncounters; 419 __u8 events[DRM_VC4_MAX_PERF_COUNTERS]; 420 }; 421 422 struct drm_vc4_perfmon_destroy { 423 __u32 id; 424 }; 425 426 /* 427 * Returns the values of the performance counters tracked by this 428 * perfmon (as an array of ncounters u64 values). 429 * 430 * No implicit synchronization is performed, so the user has to 431 * guarantee that any jobs using this perfmon have already been 432 * completed (probably by blocking on the seqno returned by the 433 * last exec that used the perfmon). 434 */ 435 struct drm_vc4_perfmon_get_values { 436 __u32 id; 437 __u64 values_ptr; 438 }; 439 440 #if defined(__cplusplus) 441 } 442 #endif 443 444 #endif /* _UAPI_VC4_DRM_H_ */ 445
Indexes created Tue Sep 23 07:09:52 GMT 2025