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      1 /*	$NetBSD: histb-clock.h,v 1.1.1.5 2020/01/03 14:33:05 skrll Exp $	*/
      2 
      3 /* SPDX-License-Identifier: GPL-2.0-or-later */
      4 /*
      5  * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
      6  */
      7 
      8 #ifndef __DTS_HISTB_CLOCK_H
      9 #define __DTS_HISTB_CLOCK_H
     10 
     11 /* clocks provided by core CRG */
     12 #define HISTB_OSC_CLK			0
     13 #define HISTB_APB_CLK			1
     14 #define HISTB_AHB_CLK			2
     15 #define HISTB_UART1_CLK			3
     16 #define HISTB_UART2_CLK			4
     17 #define HISTB_UART3_CLK			5
     18 #define HISTB_I2C0_CLK			6
     19 #define HISTB_I2C1_CLK			7
     20 #define HISTB_I2C2_CLK			8
     21 #define HISTB_I2C3_CLK			9
     22 #define HISTB_I2C4_CLK			10
     23 #define HISTB_I2C5_CLK			11
     24 #define HISTB_SPI0_CLK			12
     25 #define HISTB_SPI1_CLK			13
     26 #define HISTB_SPI2_CLK			14
     27 #define HISTB_SCI_CLK			15
     28 #define HISTB_FMC_CLK			16
     29 #define HISTB_MMC_BIU_CLK		17
     30 #define HISTB_MMC_CIU_CLK		18
     31 #define HISTB_MMC_DRV_CLK		19
     32 #define HISTB_MMC_SAMPLE_CLK		20
     33 #define HISTB_SDIO0_BIU_CLK		21
     34 #define HISTB_SDIO0_CIU_CLK		22
     35 #define HISTB_SDIO0_DRV_CLK		23
     36 #define HISTB_SDIO0_SAMPLE_CLK		24
     37 #define HISTB_PCIE_AUX_CLK		25
     38 #define HISTB_PCIE_PIPE_CLK		26
     39 #define HISTB_PCIE_SYS_CLK		27
     40 #define HISTB_PCIE_BUS_CLK		28
     41 #define HISTB_ETH0_MAC_CLK		29
     42 #define HISTB_ETH0_MACIF_CLK		30
     43 #define HISTB_ETH1_MAC_CLK		31
     44 #define HISTB_ETH1_MACIF_CLK		32
     45 #define HISTB_COMBPHY1_CLK		33
     46 #define HISTB_USB2_BUS_CLK		34
     47 #define HISTB_USB2_PHY_CLK		35
     48 #define HISTB_USB2_UTMI_CLK		36
     49 #define HISTB_USB2_12M_CLK		37
     50 #define HISTB_USB2_48M_CLK		38
     51 #define HISTB_USB2_OTG_UTMI_CLK		39
     52 #define HISTB_USB2_PHY1_REF_CLK		40
     53 #define HISTB_USB2_PHY2_REF_CLK		41
     54 #define HISTB_COMBPHY0_CLK		42
     55 #define HISTB_USB3_BUS_CLK		43
     56 #define HISTB_USB3_UTMI_CLK		44
     57 #define HISTB_USB3_PIPE_CLK		45
     58 #define HISTB_USB3_SUSPEND_CLK		46
     59 #define HISTB_USB3_BUS_CLK1		47
     60 #define HISTB_USB3_UTMI_CLK1		48
     61 #define HISTB_USB3_PIPE_CLK1		49
     62 #define HISTB_USB3_SUSPEND_CLK1		50
     63 
     64 /* clocks provided by mcu CRG */
     65 #define HISTB_MCE_CLK			1
     66 #define HISTB_IR_CLK			2
     67 #define HISTB_TIMER01_CLK		3
     68 #define HISTB_LEDC_CLK			4
     69 #define HISTB_UART0_CLK			5
     70 #define HISTB_LSADC_CLK			6
     71 
     72 #endif	/* __DTS_HISTB_CLOCK_H */
     73