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      1 /*	$NetBSD: nuvoton,npcm845-clk.h,v 1.1.1.1 2026/01/18 05:21:33 skrll Exp $	*/
      2 
      3 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
      4 /*
      5  * Copyright (C) 2021 Nuvoton Technologies.
      6  * Author: Tomer Maimon <tomer.maimon (at) nuvoton.com>
      7  *
      8  * Device Tree binding constants for NPCM8XX clock controller.
      9  */
     10 
     11 #ifndef __DT_BINDINGS_CLOCK_NPCM8XX_H
     12 #define __DT_BINDINGS_CLOCK_NPCM8XX_H
     13 
     14 #define NPCM8XX_CLK_CPU		0
     15 #define NPCM8XX_CLK_GFX_PIXEL	1
     16 #define NPCM8XX_CLK_MC		2
     17 #define NPCM8XX_CLK_ADC		3
     18 #define NPCM8XX_CLK_AHB		4
     19 #define NPCM8XX_CLK_TIMER	5
     20 #define NPCM8XX_CLK_UART	6
     21 #define NPCM8XX_CLK_UART2	7
     22 #define NPCM8XX_CLK_MMC		8
     23 #define NPCM8XX_CLK_SPI3	9
     24 #define NPCM8XX_CLK_PCI		10
     25 #define NPCM8XX_CLK_AXI		11
     26 #define NPCM8XX_CLK_APB4	12
     27 #define NPCM8XX_CLK_APB3	13
     28 #define NPCM8XX_CLK_APB2	14
     29 #define NPCM8XX_CLK_APB1	15
     30 #define NPCM8XX_CLK_APB5	16
     31 #define NPCM8XX_CLK_CLKOUT	17
     32 #define NPCM8XX_CLK_GFX		18
     33 #define NPCM8XX_CLK_SU		19
     34 #define NPCM8XX_CLK_SU48	20
     35 #define NPCM8XX_CLK_SDHC	21
     36 #define NPCM8XX_CLK_SPI0	22
     37 #define NPCM8XX_CLK_SPI1	23
     38 #define NPCM8XX_CLK_SPIX	24
     39 #define NPCM8XX_CLK_RG		25
     40 #define NPCM8XX_CLK_RCP		26
     41 #define NPCM8XX_CLK_PRE_ADC	27
     42 #define NPCM8XX_CLK_ATB		28
     43 #define NPCM8XX_CLK_PRE_CLK	29
     44 #define NPCM8XX_CLK_TH		30
     45 #define NPCM8XX_CLK_REFCLK	31
     46 #define NPCM8XX_CLK_SYSBYPCK	32
     47 #define NPCM8XX_CLK_MCBYPCK	33
     48 
     49 #define NPCM8XX_NUM_CLOCKS	(NPCM8XX_CLK_MCBYPCK + 1)
     50 
     51 #endif
     52