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      1 /*	$NetBSD: qcom,gcc-msm8976.h,v 1.1.1.1 2026/01/18 05:21:35 skrll Exp $	*/
      2 
      3 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
      4 /*
      5  * Copyright (C) 2016, The Linux Foundation. All rights reserved.
      6  * Copyright (C) 2016-2021, AngeloGioacchino Del Regno
      7  *                     <angelogioacchino.delregno (at) somainline.org>
      8  */
      9 
     10 #ifndef _DT_BINDINGS_CLK_MSM_GCC_8976_H
     11 #define _DT_BINDINGS_CLK_MSM_GCC_8976_H
     12 
     13 #define GPLL0					0
     14 #define GPLL2					1
     15 #define GPLL3					2
     16 #define GPLL4					3
     17 #define GPLL6					4
     18 #define GPLL0_CLK_SRC				5
     19 #define GPLL2_CLK_SRC				6
     20 #define GPLL3_CLK_SRC				7
     21 #define GPLL4_CLK_SRC				8
     22 #define GPLL6_CLK_SRC				9
     23 #define GCC_BLSP1_QUP1_SPI_APPS_CLK		10
     24 #define GCC_BLSP1_QUP1_I2C_APPS_CLK		11
     25 #define GCC_BLSP1_QUP2_I2C_APPS_CLK		12
     26 #define GCC_BLSP1_QUP2_SPI_APPS_CLK		13
     27 #define GCC_BLSP1_QUP3_I2C_APPS_CLK		14
     28 #define GCC_BLSP1_QUP3_SPI_APPS_CLK		15
     29 #define GCC_BLSP1_QUP4_I2C_APPS_CLK		16
     30 #define GCC_BLSP1_QUP4_SPI_APPS_CLK		17
     31 #define GCC_BLSP1_UART1_APPS_CLK		18
     32 #define GCC_BLSP1_UART2_APPS_CLK		19
     33 #define GCC_BLSP2_QUP1_I2C_APPS_CLK		20
     34 #define GCC_BLSP2_QUP1_SPI_APPS_CLK		21
     35 #define GCC_BLSP2_QUP2_I2C_APPS_CLK		22
     36 #define GCC_BLSP2_QUP2_SPI_APPS_CLK		23
     37 #define GCC_BLSP2_QUP3_I2C_APPS_CLK		24
     38 #define GCC_BLSP2_QUP3_SPI_APPS_CLK		25
     39 #define GCC_BLSP2_QUP4_I2C_APPS_CLK		26
     40 #define GCC_BLSP2_QUP4_SPI_APPS_CLK		27
     41 #define GCC_BLSP2_UART1_APPS_CLK		28
     42 #define GCC_BLSP2_UART2_APPS_CLK		29
     43 #define GCC_CAMSS_CCI_AHB_CLK			30
     44 #define GCC_CAMSS_CCI_CLK			31
     45 #define GCC_CAMSS_CPP_AHB_CLK			32
     46 #define GCC_CAMSS_CPP_AXI_CLK			33
     47 #define GCC_CAMSS_CPP_CLK			34
     48 #define GCC_CAMSS_CSI0_AHB_CLK			35
     49 #define GCC_CAMSS_CSI0_CLK			36
     50 #define GCC_CAMSS_CSI0PHY_CLK			37
     51 #define GCC_CAMSS_CSI0PIX_CLK			38
     52 #define GCC_CAMSS_CSI0RDI_CLK			39
     53 #define GCC_CAMSS_CSI1_AHB_CLK			40
     54 #define GCC_CAMSS_CSI1_CLK			41
     55 #define GCC_CAMSS_CSI1PHY_CLK			42
     56 #define GCC_CAMSS_CSI1PIX_CLK			43
     57 #define GCC_CAMSS_CSI1RDI_CLK			44
     58 #define GCC_CAMSS_CSI2_AHB_CLK			45
     59 #define GCC_CAMSS_CSI2_CLK			46
     60 #define GCC_CAMSS_CSI2PHY_CLK			47
     61 #define GCC_CAMSS_CSI2PIX_CLK			48
     62 #define GCC_CAMSS_CSI2RDI_CLK			49
     63 #define GCC_CAMSS_CSI_VFE0_CLK			50
     64 #define GCC_CAMSS_CSI_VFE1_CLK			51
     65 #define GCC_CAMSS_GP0_CLK			52
     66 #define GCC_CAMSS_GP1_CLK			53
     67 #define GCC_CAMSS_ISPIF_AHB_CLK			54
     68 #define GCC_CAMSS_JPEG0_CLK			55
     69 #define GCC_CAMSS_JPEG_AHB_CLK			56
     70 #define GCC_CAMSS_JPEG_AXI_CLK			57
     71 #define GCC_CAMSS_MCLK0_CLK			58
     72 #define GCC_CAMSS_MCLK1_CLK			59
     73 #define GCC_CAMSS_MCLK2_CLK			60
     74 #define GCC_CAMSS_MICRO_AHB_CLK			61
     75 #define GCC_CAMSS_CSI0PHYTIMER_CLK		62
     76 #define GCC_CAMSS_CSI1PHYTIMER_CLK		63
     77 #define GCC_CAMSS_AHB_CLK			64
     78 #define GCC_CAMSS_TOP_AHB_CLK			65
     79 #define GCC_CAMSS_VFE0_CLK			66
     80 #define GCC_CAMSS_VFE_AHB_CLK			67
     81 #define GCC_CAMSS_VFE_AXI_CLK			68
     82 #define GCC_CAMSS_VFE1_AHB_CLK			69
     83 #define GCC_CAMSS_VFE1_AXI_CLK			70
     84 #define GCC_CAMSS_VFE1_CLK			71
     85 #define GCC_DCC_CLK				72
     86 #define GCC_GP1_CLK				73
     87 #define GCC_GP2_CLK				74
     88 #define GCC_GP3_CLK				75
     89 #define GCC_MDSS_AHB_CLK			76
     90 #define GCC_MDSS_AXI_CLK			77
     91 #define GCC_MDSS_ESC0_CLK			78
     92 #define GCC_MDSS_ESC1_CLK			79
     93 #define GCC_MDSS_MDP_CLK			80
     94 #define GCC_MDSS_VSYNC_CLK			81
     95 #define GCC_MSS_CFG_AHB_CLK			82
     96 #define GCC_MSS_Q6_BIMC_AXI_CLK			83
     97 #define GCC_PDM2_CLK				84
     98 #define GCC_PRNG_AHB_CLK			85
     99 #define GCC_PDM_AHB_CLK				86
    100 #define GCC_RBCPR_GFX_AHB_CLK			87
    101 #define GCC_RBCPR_GFX_CLK			88
    102 #define GCC_SDCC1_AHB_CLK			89
    103 #define GCC_SDCC1_APPS_CLK			90
    104 #define GCC_SDCC1_ICE_CORE_CLK			91
    105 #define GCC_SDCC2_AHB_CLK			92
    106 #define GCC_SDCC2_APPS_CLK			93
    107 #define GCC_SDCC3_AHB_CLK			94
    108 #define GCC_SDCC3_APPS_CLK			95
    109 #define GCC_USB2A_PHY_SLEEP_CLK			96
    110 #define GCC_USB_HS_PHY_CFG_AHB_CLK		97
    111 #define GCC_USB_FS_AHB_CLK			98
    112 #define GCC_USB_FS_IC_CLK			99
    113 #define GCC_USB_FS_SYSTEM_CLK			100
    114 #define GCC_USB_HS_AHB_CLK			101
    115 #define GCC_USB_HS_SYSTEM_CLK			102
    116 #define GCC_VENUS0_AHB_CLK			103
    117 #define GCC_VENUS0_AXI_CLK			104
    118 #define GCC_VENUS0_CORE0_VCODEC0_CLK		105
    119 #define GCC_VENUS0_CORE1_VCODEC0_CLK		106
    120 #define GCC_VENUS0_VCODEC0_CLK			107
    121 #define GCC_APSS_AHB_CLK			108
    122 #define GCC_APSS_AXI_CLK			109
    123 #define GCC_BLSP1_AHB_CLK			110
    124 #define GCC_BLSP2_AHB_CLK			111
    125 #define GCC_BOOT_ROM_AHB_CLK			112
    126 #define GCC_CRYPTO_AHB_CLK			113
    127 #define GCC_CRYPTO_AXI_CLK			114
    128 #define GCC_CRYPTO_CLK				115
    129 #define GCC_CPP_TBU_CLK				116
    130 #define GCC_APSS_TCU_CLK			117
    131 #define GCC_JPEG_TBU_CLK			118
    132 #define GCC_MDP_RT_TBU_CLK			119
    133 #define GCC_MDP_TBU_CLK				120
    134 #define GCC_SMMU_CFG_CLK			121
    135 #define GCC_VENUS_1_TBU_CLK			122
    136 #define GCC_VENUS_TBU_CLK			123
    137 #define GCC_VFE1_TBU_CLK			124
    138 #define GCC_VFE_TBU_CLK				125
    139 #define GCC_APS_0_CLK				126
    140 #define GCC_APS_1_CLK				127
    141 #define APS_0_CLK_SRC				128
    142 #define APS_1_CLK_SRC				129
    143 #define APSS_AHB_CLK_SRC			130
    144 #define BLSP1_QUP1_I2C_APPS_CLK_SRC		131
    145 #define BLSP1_QUP1_SPI_APPS_CLK_SRC		132
    146 #define BLSP1_QUP2_I2C_APPS_CLK_SRC		133
    147 #define BLSP1_QUP2_SPI_APPS_CLK_SRC		134
    148 #define BLSP1_QUP3_I2C_APPS_CLK_SRC		135
    149 #define BLSP1_QUP3_SPI_APPS_CLK_SRC		136
    150 #define BLSP1_QUP4_I2C_APPS_CLK_SRC		137
    151 #define BLSP1_QUP4_SPI_APPS_CLK_SRC		138
    152 #define BLSP1_UART1_APPS_CLK_SRC		139
    153 #define BLSP1_UART2_APPS_CLK_SRC		140
    154 #define BLSP2_QUP1_I2C_APPS_CLK_SRC		141
    155 #define BLSP2_QUP1_SPI_APPS_CLK_SRC		142
    156 #define BLSP2_QUP2_I2C_APPS_CLK_SRC		143
    157 #define BLSP2_QUP2_SPI_APPS_CLK_SRC		144
    158 #define BLSP2_QUP3_I2C_APPS_CLK_SRC		145
    159 #define BLSP2_QUP3_SPI_APPS_CLK_SRC		146
    160 #define BLSP2_QUP4_I2C_APPS_CLK_SRC		147
    161 #define BLSP2_QUP4_SPI_APPS_CLK_SRC		148
    162 #define BLSP2_UART1_APPS_CLK_SRC		149
    163 #define BLSP2_UART2_APPS_CLK_SRC		150
    164 #define CCI_CLK_SRC				151
    165 #define CPP_CLK_SRC				152
    166 #define CSI0_CLK_SRC				153
    167 #define CSI1_CLK_SRC				154
    168 #define CSI2_CLK_SRC				155
    169 #define CAMSS_GP0_CLK_SRC			156
    170 #define CAMSS_GP1_CLK_SRC			157
    171 #define JPEG0_CLK_SRC				158
    172 #define MCLK0_CLK_SRC				159
    173 #define MCLK1_CLK_SRC				160
    174 #define MCLK2_CLK_SRC				161
    175 #define CSI0PHYTIMER_CLK_SRC			162
    176 #define CSI1PHYTIMER_CLK_SRC			163
    177 #define CAMSS_TOP_AHB_CLK_SRC			164
    178 #define VFE0_CLK_SRC				165
    179 #define VFE1_CLK_SRC				166
    180 #define CRYPTO_CLK_SRC				167
    181 #define GP1_CLK_SRC				168
    182 #define GP2_CLK_SRC				169
    183 #define GP3_CLK_SRC				170
    184 #define ESC0_CLK_SRC				171
    185 #define ESC1_CLK_SRC				172
    186 #define MDP_CLK_SRC				173
    187 #define VSYNC_CLK_SRC				174
    188 #define PDM2_CLK_SRC				175
    189 #define RBCPR_GFX_CLK_SRC			176
    190 #define SDCC1_APPS_CLK_SRC			177
    191 #define SDCC1_ICE_CORE_CLK_SRC			178
    192 #define SDCC2_APPS_CLK_SRC			179
    193 #define SDCC3_APPS_CLK_SRC			180
    194 #define USB_FS_IC_CLK_SRC			181
    195 #define USB_FS_SYSTEM_CLK_SRC			182
    196 #define USB_HS_SYSTEM_CLK_SRC			183
    197 #define VCODEC0_CLK_SRC				184
    198 #define GCC_MDSS_BYTE0_CLK_SRC			185
    199 #define GCC_MDSS_BYTE1_CLK_SRC			186
    200 #define GCC_MDSS_BYTE0_CLK			187
    201 #define GCC_MDSS_BYTE1_CLK			188
    202 #define GCC_MDSS_PCLK0_CLK_SRC			189
    203 #define GCC_MDSS_PCLK1_CLK_SRC			190
    204 #define GCC_MDSS_PCLK0_CLK			191
    205 #define GCC_MDSS_PCLK1_CLK			192
    206 #define GCC_GFX3D_CLK_SRC			193
    207 #define GCC_GFX3D_OXILI_CLK			194
    208 #define GCC_GFX3D_BIMC_CLK			195
    209 #define GCC_GFX3D_OXILI_AHB_CLK			196
    210 #define GCC_GFX3D_OXILI_AON_CLK			197
    211 #define GCC_GFX3D_OXILI_GMEM_CLK		198
    212 #define GCC_GFX3D_OXILI_TIMER_CLK		199
    213 #define GCC_GFX3D_TBU0_CLK			200
    214 #define GCC_GFX3D_TBU1_CLK			201
    215 #define GCC_GFX3D_TCU_CLK			202
    216 #define GCC_GFX3D_GTCU_AHB_CLK			203
    217 
    218 /* GCC block resets */
    219 #define RST_CAMSS_MICRO_BCR			0
    220 #define RST_USB_HS_BCR				1
    221 #define RST_QUSB2_PHY_BCR			2
    222 #define RST_USB2_HS_PHY_ONLY_BCR		3
    223 #define RST_USB_HS_PHY_CFG_AHB_BCR		4
    224 #define RST_USB_FS_BCR				5
    225 #define RST_CAMSS_CSI1PIX_BCR			6
    226 #define RST_CAMSS_CSI_VFE1_BCR			7
    227 #define RST_CAMSS_VFE1_BCR			8
    228 #define RST_CAMSS_CPP_BCR			9
    229 #define RST_MSS_BCR				10
    230 
    231 /* GDSCs */
    232 #define VENUS_GDSC				0
    233 #define VENUS_CORE0_GDSC			1
    234 #define VENUS_CORE1_GDSC			2
    235 #define MDSS_GDSC				3
    236 #define JPEG_GDSC				4
    237 #define VFE0_GDSC				5
    238 #define VFE1_GDSC				6
    239 #define CPP_GDSC				7
    240 #define OXILI_GX_GDSC				8
    241 #define OXILI_CX_GDSC				9
    242 
    243 #endif /* _DT_BINDINGS_CLK_MSM_GCC_8976_H */
    244