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      1 /*	$NetBSD: renesas,r8a779h0-cpg-mssr.h,v 1.1.1.1 2026/01/18 05:21:38 skrll Exp $	*/
      2 
      3 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
      4 /*
      5  * Copyright (C) 2023 Renesas Electronics Corp.
      6  */
      7 #ifndef __DT_BINDINGS_CLOCK_RENESAS_R8A779H0_CPG_MSSR_H__
      8 #define __DT_BINDINGS_CLOCK_RENESAS_R8A779H0_CPG_MSSR_H__
      9 
     10 #include <dt-bindings/clock/renesas-cpg-mssr.h>
     11 
     12 /* r8a779h0 CPG Core Clocks */
     13 
     14 #define R8A779H0_CLK_ZX			0
     15 #define R8A779H0_CLK_ZD			1
     16 #define R8A779H0_CLK_ZS			2
     17 #define R8A779H0_CLK_ZT			3
     18 #define R8A779H0_CLK_ZTR		4
     19 #define R8A779H0_CLK_S0D2		5
     20 #define R8A779H0_CLK_S0D3		6
     21 #define R8A779H0_CLK_S0D4		7
     22 #define R8A779H0_CLK_S0D1_VIO		8
     23 #define R8A779H0_CLK_S0D2_VIO		9
     24 #define R8A779H0_CLK_S0D4_VIO		10
     25 #define R8A779H0_CLK_S0D8_VIO		11
     26 #define R8A779H0_CLK_VIOBUSD1		12
     27 #define R8A779H0_CLK_VIOBUSD2		13
     28 #define R8A779H0_CLK_S0D1_VC		14
     29 #define R8A779H0_CLK_S0D2_VC		15
     30 #define R8A779H0_CLK_S0D4_VC		16
     31 #define R8A779H0_CLK_VCBUSD1		17
     32 #define R8A779H0_CLK_VCBUSD2		18
     33 #define R8A779H0_CLK_S0D2_MM		19
     34 #define R8A779H0_CLK_S0D4_MM		20
     35 #define R8A779H0_CLK_S0D2_U3DG		21
     36 #define R8A779H0_CLK_S0D4_U3DG		22
     37 #define R8A779H0_CLK_S0D2_RT		23
     38 #define R8A779H0_CLK_S0D3_RT		24
     39 #define R8A779H0_CLK_S0D4_RT		25
     40 #define R8A779H0_CLK_S0D6_RT		26
     41 #define R8A779H0_CLK_S0D2_PER		27
     42 #define R8A779H0_CLK_S0D3_PER		28
     43 #define R8A779H0_CLK_S0D4_PER		29
     44 #define R8A779H0_CLK_S0D6_PER		30
     45 #define R8A779H0_CLK_S0D12_PER		31
     46 #define R8A779H0_CLK_S0D24_PER		32
     47 #define R8A779H0_CLK_S0D1_HSC		33
     48 #define R8A779H0_CLK_S0D2_HSC		34
     49 #define R8A779H0_CLK_S0D4_HSC		35
     50 #define R8A779H0_CLK_S0D8_HSC		36
     51 #define R8A779H0_CLK_SVD1_IR		37
     52 #define R8A779H0_CLK_SVD2_IR		38
     53 #define R8A779H0_CLK_IMPAD1		39
     54 #define R8A779H0_CLK_IMPAD4		40
     55 #define R8A779H0_CLK_IMPB		41
     56 #define R8A779H0_CLK_SVD1_VIP		42
     57 #define R8A779H0_CLK_SVD2_VIP		43
     58 #define R8A779H0_CLK_CL			44
     59 #define R8A779H0_CLK_CL16M		45
     60 #define R8A779H0_CLK_CL16M_MM		46
     61 #define R8A779H0_CLK_CL16M_RT		47
     62 #define R8A779H0_CLK_CL16M_PER		48
     63 #define R8A779H0_CLK_CL16M_HSC		49
     64 #define R8A779H0_CLK_ZC0		50
     65 #define R8A779H0_CLK_ZC1		51
     66 #define R8A779H0_CLK_ZC2		52
     67 #define R8A779H0_CLK_ZC3		53
     68 #define R8A779H0_CLK_ZB3		54
     69 #define R8A779H0_CLK_ZB3D2		55
     70 #define R8A779H0_CLK_ZB3D4		56
     71 #define R8A779H0_CLK_ZG			57
     72 #define R8A779H0_CLK_SD0H		58
     73 #define R8A779H0_CLK_SD0		59
     74 #define R8A779H0_CLK_RPC		60
     75 #define R8A779H0_CLK_RPCD2		61
     76 #define R8A779H0_CLK_MSO		62
     77 #define R8A779H0_CLK_CANFD		63
     78 #define R8A779H0_CLK_CSI		64
     79 #define R8A779H0_CLK_FRAY		65
     80 #define R8A779H0_CLK_IPC		66
     81 #define R8A779H0_CLK_SASYNCRT		67
     82 #define R8A779H0_CLK_SASYNCPERD1	68
     83 #define R8A779H0_CLK_SASYNCPERD2	69
     84 #define R8A779H0_CLK_SASYNCPERD4	70
     85 #define R8A779H0_CLK_DSIEXT		71
     86 #define R8A779H0_CLK_DSIREF		72
     87 #define R8A779H0_CLK_ADGH		73
     88 #define R8A779H0_CLK_OSC		74
     89 #define R8A779H0_CLK_ZR0		75
     90 #define R8A779H0_CLK_ZR1		76
     91 #define R8A779H0_CLK_ZR2		77
     92 #define R8A779H0_CLK_RGMII		78
     93 #define R8A779H0_CLK_CPEX		79
     94 #define R8A779H0_CLK_CP			80
     95 #define R8A779H0_CLK_CBFUSA		81
     96 #define R8A779H0_CLK_R			82
     97 
     98 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R8A779H0_CPG_MSSR_H__ */
     99