1 /* $NetBSD: jz4780-dma.h,v 1.1.1.1 2018/06/27 16:27:08 jmcneill Exp $ */ 2 3 #ifndef __DT_BINDINGS_DMA_JZ4780_DMA_H__ 4 #define __DT_BINDINGS_DMA_JZ4780_DMA_H__ 5 6 /* 7 * Request type numbers for the JZ4780 DMA controller (written to the DRTn 8 * register for the channel). 9 */ 10 #define JZ4780_DMA_I2S1_TX 0x4 11 #define JZ4780_DMA_I2S1_RX 0x5 12 #define JZ4780_DMA_I2S0_TX 0x6 13 #define JZ4780_DMA_I2S0_RX 0x7 14 #define JZ4780_DMA_AUTO 0x8 15 #define JZ4780_DMA_SADC_RX 0x9 16 #define JZ4780_DMA_UART4_TX 0xc 17 #define JZ4780_DMA_UART4_RX 0xd 18 #define JZ4780_DMA_UART3_TX 0xe 19 #define JZ4780_DMA_UART3_RX 0xf 20 #define JZ4780_DMA_UART2_TX 0x10 21 #define JZ4780_DMA_UART2_RX 0x11 22 #define JZ4780_DMA_UART1_TX 0x12 23 #define JZ4780_DMA_UART1_RX 0x13 24 #define JZ4780_DMA_UART0_TX 0x14 25 #define JZ4780_DMA_UART0_RX 0x15 26 #define JZ4780_DMA_SSI0_TX 0x16 27 #define JZ4780_DMA_SSI0_RX 0x17 28 #define JZ4780_DMA_SSI1_TX 0x18 29 #define JZ4780_DMA_SSI1_RX 0x19 30 #define JZ4780_DMA_MSC0_TX 0x1a 31 #define JZ4780_DMA_MSC0_RX 0x1b 32 #define JZ4780_DMA_MSC1_TX 0x1c 33 #define JZ4780_DMA_MSC1_RX 0x1d 34 #define JZ4780_DMA_MSC2_TX 0x1e 35 #define JZ4780_DMA_MSC2_RX 0x1f 36 #define JZ4780_DMA_PCM0_TX 0x20 37 #define JZ4780_DMA_PCM0_RX 0x21 38 #define JZ4780_DMA_SMB0_TX 0x24 39 #define JZ4780_DMA_SMB0_RX 0x25 40 #define JZ4780_DMA_SMB1_TX 0x26 41 #define JZ4780_DMA_SMB1_RX 0x27 42 #define JZ4780_DMA_SMB2_TX 0x28 43 #define JZ4780_DMA_SMB2_RX 0x29 44 #define JZ4780_DMA_SMB3_TX 0x2a 45 #define JZ4780_DMA_SMB3_RX 0x2b 46 #define JZ4780_DMA_SMB4_TX 0x2c 47 #define JZ4780_DMA_SMB4_RX 0x2d 48 #define JZ4780_DMA_DES_TX 0x2e 49 #define JZ4780_DMA_DES_RX 0x2f 50 51 #endif /* __DT_BINDINGS_DMA_JZ4780_DMA_H__ */ 52
Indexes created Mon Sep 29 21:09:56 GMT 2025