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      1 /*	$NetBSD: mt8173-gce.h,v 1.1.1.1 2019/01/22 14:57:01 jmcneill Exp $	*/
      2 
      3 /* SPDX-License-Identifier: GPL-2.0 */
      4 /*
      5  * Copyright (c) 2018 MediaTek Inc.
      6  * Author: Houlong Wei <houlong.wei (at) mediatek.com>
      7  *
      8  */
      9 
     10 #ifndef _DT_BINDINGS_GCE_MT8173_H
     11 #define _DT_BINDINGS_GCE_MT8173_H
     12 
     13 /* GCE HW thread priority */
     14 #define CMDQ_THR_PRIO_LOWEST	0
     15 #define CMDQ_THR_PRIO_HIGHEST	1
     16 
     17 /* GCE SUBSYS */
     18 #define SUBSYS_1400XXXX		1
     19 #define SUBSYS_1401XXXX		2
     20 #define SUBSYS_1402XXXX		3
     21 
     22 /* GCE HW EVENT */
     23 #define CMDQ_EVENT_DISP_OVL0_SOF		11
     24 #define CMDQ_EVENT_DISP_OVL1_SOF		12
     25 #define CMDQ_EVENT_DISP_RDMA0_SOF		13
     26 #define CMDQ_EVENT_DISP_RDMA1_SOF		14
     27 #define CMDQ_EVENT_DISP_RDMA2_SOF		15
     28 #define CMDQ_EVENT_DISP_WDMA0_SOF		16
     29 #define CMDQ_EVENT_DISP_WDMA1_SOF		17
     30 #define CMDQ_EVENT_DISP_OVL0_EOF		39
     31 #define CMDQ_EVENT_DISP_OVL1_EOF		40
     32 #define CMDQ_EVENT_DISP_RDMA0_EOF		41
     33 #define CMDQ_EVENT_DISP_RDMA1_EOF		42
     34 #define CMDQ_EVENT_DISP_RDMA2_EOF		43
     35 #define CMDQ_EVENT_DISP_WDMA0_EOF		44
     36 #define CMDQ_EVENT_DISP_WDMA1_EOF		45
     37 #define CMDQ_EVENT_MUTEX0_STREAM_EOF		53
     38 #define CMDQ_EVENT_MUTEX1_STREAM_EOF		54
     39 #define CMDQ_EVENT_MUTEX2_STREAM_EOF		55
     40 #define CMDQ_EVENT_MUTEX3_STREAM_EOF		56
     41 #define CMDQ_EVENT_MUTEX4_STREAM_EOF		57
     42 #define CMDQ_EVENT_DISP_RDMA0_UNDERRUN		63
     43 #define CMDQ_EVENT_DISP_RDMA1_UNDERRUN		64
     44 #define CMDQ_EVENT_DISP_RDMA2_UNDERRUN		65
     45 
     46 #endif
     47