1 /* $NetBSD: qcom,spmi-vadc.h,v 1.1.1.3 2021/11/07 16:49:57 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0 */ 4 /* 5 * Copyright (c) 2012-2014,2018,2020 The Linux Foundation. All rights reserved. 6 */ 7 8 #ifndef _DT_BINDINGS_QCOM_SPMI_VADC_H 9 #define _DT_BINDINGS_QCOM_SPMI_VADC_H 10 11 /* Voltage ADC channels */ 12 #define VADC_USBIN 0x00 13 #define VADC_DCIN 0x01 14 #define VADC_VCHG_SNS 0x02 15 #define VADC_SPARE1_03 0x03 16 #define VADC_USB_ID_MV 0x04 17 #define VADC_VCOIN 0x05 18 #define VADC_VBAT_SNS 0x06 19 #define VADC_VSYS 0x07 20 #define VADC_DIE_TEMP 0x08 21 #define VADC_REF_625MV 0x09 22 #define VADC_REF_1250MV 0x0a 23 #define VADC_CHG_TEMP 0x0b 24 #define VADC_SPARE1 0x0c 25 #define VADC_SPARE2 0x0d 26 #define VADC_GND_REF 0x0e 27 #define VADC_VDD_VADC 0x0f 28 29 #define VADC_P_MUX1_1_1 0x10 30 #define VADC_P_MUX2_1_1 0x11 31 #define VADC_P_MUX3_1_1 0x12 32 #define VADC_P_MUX4_1_1 0x13 33 #define VADC_P_MUX5_1_1 0x14 34 #define VADC_P_MUX6_1_1 0x15 35 #define VADC_P_MUX7_1_1 0x16 36 #define VADC_P_MUX8_1_1 0x17 37 #define VADC_P_MUX9_1_1 0x18 38 #define VADC_P_MUX10_1_1 0x19 39 #define VADC_P_MUX11_1_1 0x1a 40 #define VADC_P_MUX12_1_1 0x1b 41 #define VADC_P_MUX13_1_1 0x1c 42 #define VADC_P_MUX14_1_1 0x1d 43 #define VADC_P_MUX15_1_1 0x1e 44 #define VADC_P_MUX16_1_1 0x1f 45 46 #define VADC_P_MUX1_1_3 0x20 47 #define VADC_P_MUX2_1_3 0x21 48 #define VADC_P_MUX3_1_3 0x22 49 #define VADC_P_MUX4_1_3 0x23 50 #define VADC_P_MUX5_1_3 0x24 51 #define VADC_P_MUX6_1_3 0x25 52 #define VADC_P_MUX7_1_3 0x26 53 #define VADC_P_MUX8_1_3 0x27 54 #define VADC_P_MUX9_1_3 0x28 55 #define VADC_P_MUX10_1_3 0x29 56 #define VADC_P_MUX11_1_3 0x2a 57 #define VADC_P_MUX12_1_3 0x2b 58 #define VADC_P_MUX13_1_3 0x2c 59 #define VADC_P_MUX14_1_3 0x2d 60 #define VADC_P_MUX15_1_3 0x2e 61 #define VADC_P_MUX16_1_3 0x2f 62 63 #define VADC_LR_MUX1_BAT_THERM 0x30 64 #define VADC_LR_MUX2_BAT_ID 0x31 65 #define VADC_LR_MUX3_XO_THERM 0x32 66 #define VADC_LR_MUX4_AMUX_THM1 0x33 67 #define VADC_LR_MUX5_AMUX_THM2 0x34 68 #define VADC_LR_MUX6_AMUX_THM3 0x35 69 #define VADC_LR_MUX7_HW_ID 0x36 70 #define VADC_LR_MUX8_AMUX_THM4 0x37 71 #define VADC_LR_MUX9_AMUX_THM5 0x38 72 #define VADC_LR_MUX10_USB_ID 0x39 73 #define VADC_AMUX_PU1 0x3a 74 #define VADC_AMUX_PU2 0x3b 75 #define VADC_LR_MUX3_BUF_XO_THERM 0x3c 76 77 #define VADC_LR_MUX1_PU1_BAT_THERM 0x70 78 #define VADC_LR_MUX2_PU1_BAT_ID 0x71 79 #define VADC_LR_MUX3_PU1_XO_THERM 0x72 80 #define VADC_LR_MUX4_PU1_AMUX_THM1 0x73 81 #define VADC_LR_MUX5_PU1_AMUX_THM2 0x74 82 #define VADC_LR_MUX6_PU1_AMUX_THM3 0x75 83 #define VADC_LR_MUX7_PU1_AMUX_HW_ID 0x76 84 #define VADC_LR_MUX8_PU1_AMUX_THM4 0x77 85 #define VADC_LR_MUX9_PU1_AMUX_THM5 0x78 86 #define VADC_LR_MUX10_PU1_AMUX_USB_ID 0x79 87 #define VADC_LR_MUX3_BUF_PU1_XO_THERM 0x7c 88 89 #define VADC_LR_MUX1_PU2_BAT_THERM 0xb0 90 #define VADC_LR_MUX2_PU2_BAT_ID 0xb1 91 #define VADC_LR_MUX3_PU2_XO_THERM 0xb2 92 #define VADC_LR_MUX4_PU2_AMUX_THM1 0xb3 93 #define VADC_LR_MUX5_PU2_AMUX_THM2 0xb4 94 #define VADC_LR_MUX6_PU2_AMUX_THM3 0xb5 95 #define VADC_LR_MUX7_PU2_AMUX_HW_ID 0xb6 96 #define VADC_LR_MUX8_PU2_AMUX_THM4 0xb7 97 #define VADC_LR_MUX9_PU2_AMUX_THM5 0xb8 98 #define VADC_LR_MUX10_PU2_AMUX_USB_ID 0xb9 99 #define VADC_LR_MUX3_BUF_PU2_XO_THERM 0xbc 100 101 #define VADC_LR_MUX1_PU1_PU2_BAT_THERM 0xf0 102 #define VADC_LR_MUX2_PU1_PU2_BAT_ID 0xf1 103 #define VADC_LR_MUX3_PU1_PU2_XO_THERM 0xf2 104 #define VADC_LR_MUX4_PU1_PU2_AMUX_THM1 0xf3 105 #define VADC_LR_MUX5_PU1_PU2_AMUX_THM2 0xf4 106 #define VADC_LR_MUX6_PU1_PU2_AMUX_THM3 0xf5 107 #define VADC_LR_MUX7_PU1_PU2_AMUX_HW_ID 0xf6 108 #define VADC_LR_MUX8_PU1_PU2_AMUX_THM4 0xf7 109 #define VADC_LR_MUX9_PU1_PU2_AMUX_THM5 0xf8 110 #define VADC_LR_MUX10_PU1_PU2_AMUX_USB_ID 0xf9 111 #define VADC_LR_MUX3_BUF_PU1_PU2_XO_THERM 0xfc 112 113 /* ADC channels for SPMI PMIC5 */ 114 115 #define ADC5_REF_GND 0x00 116 #define ADC5_1P25VREF 0x01 117 #define ADC5_VREF_VADC 0x02 118 #define ADC5_VREF_VADC5_DIV_3 0x82 119 #define ADC5_VPH_PWR 0x83 120 #define ADC5_VBAT_SNS 0x84 121 #define ADC5_VCOIN 0x85 122 #define ADC5_DIE_TEMP 0x06 123 #define ADC5_USB_IN_I 0x07 124 #define ADC5_USB_IN_V_16 0x08 125 #define ADC5_CHG_TEMP 0x09 126 #define ADC5_BAT_THERM 0x0a 127 #define ADC5_BAT_ID 0x0b 128 #define ADC5_XO_THERM 0x0c 129 #define ADC5_AMUX_THM1 0x0d 130 #define ADC5_AMUX_THM2 0x0e 131 #define ADC5_AMUX_THM3 0x0f 132 #define ADC5_AMUX_THM4 0x10 133 #define ADC5_AMUX_THM5 0x11 134 #define ADC5_GPIO1 0x12 135 #define ADC5_GPIO2 0x13 136 #define ADC5_GPIO3 0x14 137 #define ADC5_GPIO4 0x15 138 #define ADC5_GPIO5 0x16 139 #define ADC5_GPIO6 0x17 140 #define ADC5_GPIO7 0x18 141 #define ADC5_SBUx 0x99 142 #define ADC5_MID_CHG_DIV6 0x1e 143 #define ADC5_OFF 0xff 144 145 /* 30k pull-up1 */ 146 #define ADC5_BAT_THERM_30K_PU 0x2a 147 #define ADC5_BAT_ID_30K_PU 0x2b 148 #define ADC5_XO_THERM_30K_PU 0x2c 149 #define ADC5_AMUX_THM1_30K_PU 0x2d 150 #define ADC5_AMUX_THM2_30K_PU 0x2e 151 #define ADC5_AMUX_THM3_30K_PU 0x2f 152 #define ADC5_AMUX_THM4_30K_PU 0x30 153 #define ADC5_AMUX_THM5_30K_PU 0x31 154 #define ADC5_GPIO1_30K_PU 0x32 155 #define ADC5_GPIO2_30K_PU 0x33 156 #define ADC5_GPIO3_30K_PU 0x34 157 #define ADC5_GPIO4_30K_PU 0x35 158 #define ADC5_GPIO5_30K_PU 0x36 159 #define ADC5_GPIO6_30K_PU 0x37 160 #define ADC5_GPIO7_30K_PU 0x38 161 #define ADC5_SBUx_30K_PU 0x39 162 163 /* 100k pull-up2 */ 164 #define ADC5_BAT_THERM_100K_PU 0x4a 165 #define ADC5_BAT_ID_100K_PU 0x4b 166 #define ADC5_XO_THERM_100K_PU 0x4c 167 #define ADC5_AMUX_THM1_100K_PU 0x4d 168 #define ADC5_AMUX_THM2_100K_PU 0x4e 169 #define ADC5_AMUX_THM3_100K_PU 0x4f 170 #define ADC5_AMUX_THM4_100K_PU 0x50 171 #define ADC5_AMUX_THM5_100K_PU 0x51 172 #define ADC5_GPIO1_100K_PU 0x52 173 #define ADC5_GPIO2_100K_PU 0x53 174 #define ADC5_GPIO3_100K_PU 0x54 175 #define ADC5_GPIO4_100K_PU 0x55 176 #define ADC5_GPIO5_100K_PU 0x56 177 #define ADC5_GPIO6_100K_PU 0x57 178 #define ADC5_GPIO7_100K_PU 0x58 179 #define ADC5_SBUx_100K_PU 0x59 180 181 /* 400k pull-up3 */ 182 #define ADC5_BAT_THERM_400K_PU 0x6a 183 #define ADC5_BAT_ID_400K_PU 0x6b 184 #define ADC5_XO_THERM_400K_PU 0x6c 185 #define ADC5_AMUX_THM1_400K_PU 0x6d 186 #define ADC5_AMUX_THM2_400K_PU 0x6e 187 #define ADC5_AMUX_THM3_400K_PU 0x6f 188 #define ADC5_AMUX_THM4_400K_PU 0x70 189 #define ADC5_AMUX_THM5_400K_PU 0x71 190 #define ADC5_GPIO1_400K_PU 0x72 191 #define ADC5_GPIO2_400K_PU 0x73 192 #define ADC5_GPIO3_400K_PU 0x74 193 #define ADC5_GPIO4_400K_PU 0x75 194 #define ADC5_GPIO5_400K_PU 0x76 195 #define ADC5_GPIO6_400K_PU 0x77 196 #define ADC5_GPIO7_400K_PU 0x78 197 #define ADC5_SBUx_400K_PU 0x79 198 199 /* 1/3 Divider */ 200 #define ADC5_GPIO1_DIV3 0x92 201 #define ADC5_GPIO2_DIV3 0x93 202 #define ADC5_GPIO3_DIV3 0x94 203 #define ADC5_GPIO4_DIV3 0x95 204 #define ADC5_GPIO5_DIV3 0x96 205 #define ADC5_GPIO6_DIV3 0x97 206 #define ADC5_GPIO7_DIV3 0x98 207 #define ADC5_SBUx_DIV3 0x99 208 209 /* Current and combined current/voltage channels */ 210 #define ADC5_INT_EXT_ISENSE 0xa1 211 #define ADC5_PARALLEL_ISENSE 0xa5 212 #define ADC5_CUR_REPLICA_VDS 0xa7 213 #define ADC5_CUR_SENS_BATFET_VDS_OFFSET 0xa9 214 #define ADC5_CUR_SENS_REPLICA_VDS_OFFSET 0xab 215 #define ADC5_EXT_SENS_OFFSET 0xad 216 217 #define ADC5_INT_EXT_ISENSE_VBAT_VDATA 0xb0 218 #define ADC5_INT_EXT_ISENSE_VBAT_IDATA 0xb1 219 #define ADC5_EXT_ISENSE_VBAT_VDATA 0xb2 220 #define ADC5_EXT_ISENSE_VBAT_IDATA 0xb3 221 #define ADC5_PARALLEL_ISENSE_VBAT_VDATA 0xb4 222 #define ADC5_PARALLEL_ISENSE_VBAT_IDATA 0xb5 223 224 #define ADC5_MAX_CHANNEL 0xc0 225 226 /* ADC channels for ADC for PMIC7 */ 227 228 #define ADC7_REF_GND 0x00 229 #define ADC7_1P25VREF 0x01 230 #define ADC7_VREF_VADC 0x02 231 #define ADC7_DIE_TEMP 0x03 232 233 #define ADC7_AMUX_THM1 0x04 234 #define ADC7_AMUX_THM2 0x05 235 #define ADC7_AMUX_THM3 0x06 236 #define ADC7_AMUX_THM4 0x07 237 #define ADC7_AMUX_THM5 0x08 238 #define ADC7_AMUX_THM6 0x09 239 #define ADC7_GPIO1 0x0a 240 #define ADC7_GPIO2 0x0b 241 #define ADC7_GPIO3 0x0c 242 #define ADC7_GPIO4 0x0d 243 244 #define ADC7_CHG_TEMP 0x10 245 #define ADC7_USB_IN_V_16 0x11 246 #define ADC7_VDC_16 0x12 247 #define ADC7_CC1_ID 0x13 248 #define ADC7_VREF_BAT_THERM 0x15 249 #define ADC7_IIN_FB 0x17 250 251 /* 30k pull-up1 */ 252 #define ADC7_AMUX_THM1_30K_PU 0x24 253 #define ADC7_AMUX_THM2_30K_PU 0x25 254 #define ADC7_AMUX_THM3_30K_PU 0x26 255 #define ADC7_AMUX_THM4_30K_PU 0x27 256 #define ADC7_AMUX_THM5_30K_PU 0x28 257 #define ADC7_AMUX_THM6_30K_PU 0x29 258 #define ADC7_GPIO1_30K_PU 0x2a 259 #define ADC7_GPIO2_30K_PU 0x2b 260 #define ADC7_GPIO3_30K_PU 0x2c 261 #define ADC7_GPIO4_30K_PU 0x2d 262 #define ADC7_CC1_ID_30K_PU 0x33 263 264 /* 100k pull-up2 */ 265 #define ADC7_AMUX_THM1_100K_PU 0x44 266 #define ADC7_AMUX_THM2_100K_PU 0x45 267 #define ADC7_AMUX_THM3_100K_PU 0x46 268 #define ADC7_AMUX_THM4_100K_PU 0x47 269 #define ADC7_AMUX_THM5_100K_PU 0x48 270 #define ADC7_AMUX_THM6_100K_PU 0x49 271 #define ADC7_GPIO1_100K_PU 0x4a 272 #define ADC7_GPIO2_100K_PU 0x4b 273 #define ADC7_GPIO3_100K_PU 0x4c 274 #define ADC7_GPIO4_100K_PU 0x4d 275 #define ADC7_CC1_ID_100K_PU 0x53 276 277 /* 400k pull-up3 */ 278 #define ADC7_AMUX_THM1_400K_PU 0x64 279 #define ADC7_AMUX_THM2_400K_PU 0x65 280 #define ADC7_AMUX_THM3_400K_PU 0x66 281 #define ADC7_AMUX_THM4_400K_PU 0x67 282 #define ADC7_AMUX_THM5_400K_PU 0x68 283 #define ADC7_AMUX_THM6_400K_PU 0x69 284 #define ADC7_GPIO1_400K_PU 0x6a 285 #define ADC7_GPIO2_400K_PU 0x6b 286 #define ADC7_GPIO3_400K_PU 0x6c 287 #define ADC7_GPIO4_400K_PU 0x6d 288 #define ADC7_CC1_ID_400K_PU 0x73 289 290 /* 1/3 Divider */ 291 #define ADC7_GPIO1_DIV3 0x8a 292 #define ADC7_GPIO2_DIV3 0x8b 293 #define ADC7_GPIO3_DIV3 0x8c 294 #define ADC7_GPIO4_DIV3 0x8d 295 296 #define ADC7_VPH_PWR 0x8e 297 #define ADC7_VBAT_SNS 0x8f 298 299 #define ADC7_SBUx 0x94 300 #define ADC7_VBAT_2S_MID 0x96 301 302 #endif /* _DT_BINDINGS_QCOM_SPMI_VADC_H */ 303
Indexes created Sat Oct 25 16:10:12 GMT 2025