1 /* $NetBSD: tegra194-mc.h,v 1.1.1.1 2021/11/07 16:49:56 jmcneill Exp $ */ 2 3 #ifndef DT_BINDINGS_MEMORY_TEGRA194_MC_H 4 #define DT_BINDINGS_MEMORY_TEGRA194_MC_H 5 6 /* special clients */ 7 #define TEGRA194_SID_INVALID 0x00 8 #define TEGRA194_SID_PASSTHROUGH 0x7f 9 10 /* host1x clients */ 11 #define TEGRA194_SID_HOST1X 0x01 12 #define TEGRA194_SID_CSI 0x02 13 #define TEGRA194_SID_VIC 0x03 14 #define TEGRA194_SID_VI 0x04 15 #define TEGRA194_SID_ISP 0x05 16 #define TEGRA194_SID_NVDEC 0x06 17 #define TEGRA194_SID_NVENC 0x07 18 #define TEGRA194_SID_NVJPG 0x08 19 #define TEGRA194_SID_NVDISPLAY 0x09 20 #define TEGRA194_SID_TSEC 0x0a 21 #define TEGRA194_SID_TSECB 0x0b 22 #define TEGRA194_SID_SE 0x0c 23 #define TEGRA194_SID_SE1 0x0d 24 #define TEGRA194_SID_SE2 0x0e 25 #define TEGRA194_SID_SE3 0x0f 26 27 /* GPU clients */ 28 #define TEGRA194_SID_GPU 0x10 29 30 /* other SoC clients */ 31 #define TEGRA194_SID_AFI 0x11 32 #define TEGRA194_SID_HDA 0x12 33 #define TEGRA194_SID_ETR 0x13 34 #define TEGRA194_SID_EQOS 0x14 35 #define TEGRA194_SID_UFSHC 0x15 36 #define TEGRA194_SID_AON 0x16 37 #define TEGRA194_SID_SDMMC4 0x17 38 #define TEGRA194_SID_SDMMC3 0x18 39 #define TEGRA194_SID_SDMMC2 0x19 40 #define TEGRA194_SID_SDMMC1 0x1a 41 #define TEGRA194_SID_XUSB_HOST 0x1b 42 #define TEGRA194_SID_XUSB_DEV 0x1c 43 #define TEGRA194_SID_SATA 0x1d 44 #define TEGRA194_SID_APE 0x1e 45 #define TEGRA194_SID_SCE 0x1f 46 47 /* GPC DMA clients */ 48 #define TEGRA194_SID_GPCDMA_0 0x20 49 #define TEGRA194_SID_GPCDMA_1 0x21 50 #define TEGRA194_SID_GPCDMA_2 0x22 51 #define TEGRA194_SID_GPCDMA_3 0x23 52 #define TEGRA194_SID_GPCDMA_4 0x24 53 #define TEGRA194_SID_GPCDMA_5 0x25 54 #define TEGRA194_SID_GPCDMA_6 0x26 55 #define TEGRA194_SID_GPCDMA_7 0x27 56 57 /* APE DMA clients */ 58 #define TEGRA194_SID_APE_1 0x28 59 #define TEGRA194_SID_APE_2 0x29 60 61 /* camera RTCPU */ 62 #define TEGRA194_SID_RCE 0x2a 63 64 /* camera RTCPU on host1x address space */ 65 #define TEGRA194_SID_RCE_1X 0x2b 66 67 /* APE DMA clients */ 68 #define TEGRA194_SID_APE_3 0x2c 69 70 /* camera RTCPU running on APE */ 71 #define TEGRA194_SID_APE_CAM 0x2d 72 #define TEGRA194_SID_APE_CAM_1X 0x2e 73 74 #define TEGRA194_SID_RCE_RM 0x2f 75 #define TEGRA194_SID_VI_FALCON 0x30 76 #define TEGRA194_SID_ISP_FALCON 0x31 77 78 /* 79 * The BPMP has its SID value hardcoded in the firmware. Changing it requires 80 * considerable effort. 81 */ 82 #define TEGRA194_SID_BPMP 0x32 83 84 /* for SMMU tests */ 85 #define TEGRA194_SID_SMMU_TEST 0x33 86 87 /* host1x virtualization channels */ 88 #define TEGRA194_SID_HOST1X_CTX0 0x38 89 #define TEGRA194_SID_HOST1X_CTX1 0x39 90 #define TEGRA194_SID_HOST1X_CTX2 0x3a 91 #define TEGRA194_SID_HOST1X_CTX3 0x3b 92 #define TEGRA194_SID_HOST1X_CTX4 0x3c 93 #define TEGRA194_SID_HOST1X_CTX5 0x3d 94 #define TEGRA194_SID_HOST1X_CTX6 0x3e 95 #define TEGRA194_SID_HOST1X_CTX7 0x3f 96 97 /* host1x command buffers */ 98 #define TEGRA194_SID_HOST1X_VM0 0x40 99 #define TEGRA194_SID_HOST1X_VM1 0x41 100 #define TEGRA194_SID_HOST1X_VM2 0x42 101 #define TEGRA194_SID_HOST1X_VM3 0x43 102 #define TEGRA194_SID_HOST1X_VM4 0x44 103 #define TEGRA194_SID_HOST1X_VM5 0x45 104 #define TEGRA194_SID_HOST1X_VM6 0x46 105 #define TEGRA194_SID_HOST1X_VM7 0x47 106 107 /* SE data buffers */ 108 #define TEGRA194_SID_SE_VM0 0x48 109 #define TEGRA194_SID_SE_VM1 0x49 110 #define TEGRA194_SID_SE_VM2 0x4a 111 #define TEGRA194_SID_SE_VM3 0x4b 112 #define TEGRA194_SID_SE_VM4 0x4c 113 #define TEGRA194_SID_SE_VM5 0x4d 114 #define TEGRA194_SID_SE_VM6 0x4e 115 #define TEGRA194_SID_SE_VM7 0x4f 116 117 #define TEGRA194_SID_MIU 0x50 118 119 #define TEGRA194_SID_NVDLA0 0x51 120 #define TEGRA194_SID_NVDLA1 0x52 121 122 #define TEGRA194_SID_PVA0 0x53 123 #define TEGRA194_SID_PVA1 0x54 124 #define TEGRA194_SID_NVENC1 0x55 125 #define TEGRA194_SID_PCIE0 0x56 126 #define TEGRA194_SID_PCIE1 0x57 127 #define TEGRA194_SID_PCIE2 0x58 128 #define TEGRA194_SID_PCIE3 0x59 129 #define TEGRA194_SID_PCIE4 0x5a 130 #define TEGRA194_SID_PCIE5 0x5b 131 #define TEGRA194_SID_NVDEC1 0x5c 132 133 #define TEGRA194_SID_XUSB_VF0 0x5d 134 #define TEGRA194_SID_XUSB_VF1 0x5e 135 #define TEGRA194_SID_XUSB_VF2 0x5f 136 #define TEGRA194_SID_XUSB_VF3 0x60 137 138 #define TEGRA194_SID_RCE_VM3 0x61 139 #define TEGRA194_SID_VI_VM2 0x62 140 #define TEGRA194_SID_VI_VM3 0x63 141 #define TEGRA194_SID_RCE_SERVER 0x64 142 143 /* 144 * memory client IDs 145 */ 146 147 /* Misses from System Memory Management Unit (SMMU) Page Table Cache (PTC) */ 148 #define TEGRA194_MEMORY_CLIENT_PTCR 0x00 149 /* MSS internal memqual MIU7 read clients */ 150 #define TEGRA194_MEMORY_CLIENT_MIU7R 0x01 151 /* MSS internal memqual MIU7 write clients */ 152 #define TEGRA194_MEMORY_CLIENT_MIU7W 0x02 153 /* High-definition audio (HDA) read clients */ 154 #define TEGRA194_MEMORY_CLIENT_HDAR 0x15 155 /* Host channel data read clients */ 156 #define TEGRA194_MEMORY_CLIENT_HOST1XDMAR 0x16 157 #define TEGRA194_MEMORY_CLIENT_NVENCSRD 0x1c 158 /* SATA read clients */ 159 #define TEGRA194_MEMORY_CLIENT_SATAR 0x1f 160 /* Reads from Cortex-A9 4 CPU cores via the L2 cache */ 161 #define TEGRA194_MEMORY_CLIENT_MPCORER 0x27 162 #define TEGRA194_MEMORY_CLIENT_NVENCSWR 0x2b 163 /* High-definition audio (HDA) write clients */ 164 #define TEGRA194_MEMORY_CLIENT_HDAW 0x35 165 /* Writes from Cortex-A9 4 CPU cores via the L2 cache */ 166 #define TEGRA194_MEMORY_CLIENT_MPCOREW 0x39 167 /* SATA write clients */ 168 #define TEGRA194_MEMORY_CLIENT_SATAW 0x3d 169 /* ISP read client for Crossbar A */ 170 #define TEGRA194_MEMORY_CLIENT_ISPRA 0x44 171 /* ISP read client 1 for Crossbar A */ 172 #define TEGRA194_MEMORY_CLIENT_ISPFALR 0x45 173 /* ISP Write client for Crossbar A */ 174 #define TEGRA194_MEMORY_CLIENT_ISPWA 0x46 175 /* ISP Write client Crossbar B */ 176 #define TEGRA194_MEMORY_CLIENT_ISPWB 0x47 177 /* XUSB_HOST read clients */ 178 #define TEGRA194_MEMORY_CLIENT_XUSB_HOSTR 0x4a 179 /* XUSB_HOST write clients */ 180 #define TEGRA194_MEMORY_CLIENT_XUSB_HOSTW 0x4b 181 /* XUSB read clients */ 182 #define TEGRA194_MEMORY_CLIENT_XUSB_DEVR 0x4c 183 /* XUSB_DEV write clients */ 184 #define TEGRA194_MEMORY_CLIENT_XUSB_DEVW 0x4d 185 /* sdmmca memory read client */ 186 #define TEGRA194_MEMORY_CLIENT_SDMMCRA 0x60 187 /* sdmmc memory read client */ 188 #define TEGRA194_MEMORY_CLIENT_SDMMCR 0x62 189 /* sdmmcd memory read client */ 190 #define TEGRA194_MEMORY_CLIENT_SDMMCRAB 0x63 191 /* sdmmca memory write client */ 192 #define TEGRA194_MEMORY_CLIENT_SDMMCWA 0x64 193 /* sdmmc memory write client */ 194 #define TEGRA194_MEMORY_CLIENT_SDMMCW 0x66 195 /* sdmmcd memory write client */ 196 #define TEGRA194_MEMORY_CLIENT_SDMMCWAB 0x67 197 #define TEGRA194_MEMORY_CLIENT_VICSRD 0x6c 198 #define TEGRA194_MEMORY_CLIENT_VICSWR 0x6d 199 /* VI Write client */ 200 #define TEGRA194_MEMORY_CLIENT_VIW 0x72 201 #define TEGRA194_MEMORY_CLIENT_NVDECSRD 0x78 202 #define TEGRA194_MEMORY_CLIENT_NVDECSWR 0x79 203 /* Audio Processing (APE) engine read clients */ 204 #define TEGRA194_MEMORY_CLIENT_APER 0x7a 205 /* Audio Processing (APE) engine write clients */ 206 #define TEGRA194_MEMORY_CLIENT_APEW 0x7b 207 #define TEGRA194_MEMORY_CLIENT_NVJPGSRD 0x7e 208 #define TEGRA194_MEMORY_CLIENT_NVJPGSWR 0x7f 209 /* AXI AP and DFD-AUX0/1 read clients Both share the same interface on the on MSS */ 210 #define TEGRA194_MEMORY_CLIENT_AXIAPR 0x82 211 /* AXI AP and DFD-AUX0/1 write clients Both sahre the same interface on MSS */ 212 #define TEGRA194_MEMORY_CLIENT_AXIAPW 0x83 213 /* ETR read clients */ 214 #define TEGRA194_MEMORY_CLIENT_ETRR 0x84 215 /* ETR write clients */ 216 #define TEGRA194_MEMORY_CLIENT_ETRW 0x85 217 /* AXI Switch read client */ 218 #define TEGRA194_MEMORY_CLIENT_AXISR 0x8c 219 /* AXI Switch write client */ 220 #define TEGRA194_MEMORY_CLIENT_AXISW 0x8d 221 /* EQOS read client */ 222 #define TEGRA194_MEMORY_CLIENT_EQOSR 0x8e 223 /* EQOS write client */ 224 #define TEGRA194_MEMORY_CLIENT_EQOSW 0x8f 225 /* UFSHC read client */ 226 #define TEGRA194_MEMORY_CLIENT_UFSHCR 0x90 227 /* UFSHC write client */ 228 #define TEGRA194_MEMORY_CLIENT_UFSHCW 0x91 229 /* NVDISPLAY read client */ 230 #define TEGRA194_MEMORY_CLIENT_NVDISPLAYR 0x92 231 /* BPMP read client */ 232 #define TEGRA194_MEMORY_CLIENT_BPMPR 0x93 233 /* BPMP write client */ 234 #define TEGRA194_MEMORY_CLIENT_BPMPW 0x94 235 /* BPMPDMA read client */ 236 #define TEGRA194_MEMORY_CLIENT_BPMPDMAR 0x95 237 /* BPMPDMA write client */ 238 #define TEGRA194_MEMORY_CLIENT_BPMPDMAW 0x96 239 /* AON read client */ 240 #define TEGRA194_MEMORY_CLIENT_AONR 0x97 241 /* AON write client */ 242 #define TEGRA194_MEMORY_CLIENT_AONW 0x98 243 /* AONDMA read client */ 244 #define TEGRA194_MEMORY_CLIENT_AONDMAR 0x99 245 /* AONDMA write client */ 246 #define TEGRA194_MEMORY_CLIENT_AONDMAW 0x9a 247 /* SCE read client */ 248 #define TEGRA194_MEMORY_CLIENT_SCER 0x9b 249 /* SCE write client */ 250 #define TEGRA194_MEMORY_CLIENT_SCEW 0x9c 251 /* SCEDMA read client */ 252 #define TEGRA194_MEMORY_CLIENT_SCEDMAR 0x9d 253 /* SCEDMA write client */ 254 #define TEGRA194_MEMORY_CLIENT_SCEDMAW 0x9e 255 /* APEDMA read client */ 256 #define TEGRA194_MEMORY_CLIENT_APEDMAR 0x9f 257 /* APEDMA write client */ 258 #define TEGRA194_MEMORY_CLIENT_APEDMAW 0xa0 259 /* NVDISPLAY read client instance 2 */ 260 #define TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 0xa1 261 #define TEGRA194_MEMORY_CLIENT_VICSRD1 0xa2 262 #define TEGRA194_MEMORY_CLIENT_NVDECSRD1 0xa3 263 /* MSS internal memqual MIU0 read clients */ 264 #define TEGRA194_MEMORY_CLIENT_MIU0R 0xa6 265 /* MSS internal memqual MIU0 write clients */ 266 #define TEGRA194_MEMORY_CLIENT_MIU0W 0xa7 267 /* MSS internal memqual MIU1 read clients */ 268 #define TEGRA194_MEMORY_CLIENT_MIU1R 0xa8 269 /* MSS internal memqual MIU1 write clients */ 270 #define TEGRA194_MEMORY_CLIENT_MIU1W 0xa9 271 /* MSS internal memqual MIU2 read clients */ 272 #define TEGRA194_MEMORY_CLIENT_MIU2R 0xae 273 /* MSS internal memqual MIU2 write clients */ 274 #define TEGRA194_MEMORY_CLIENT_MIU2W 0xaf 275 /* MSS internal memqual MIU3 read clients */ 276 #define TEGRA194_MEMORY_CLIENT_MIU3R 0xb0 277 /* MSS internal memqual MIU3 write clients */ 278 #define TEGRA194_MEMORY_CLIENT_MIU3W 0xb1 279 /* MSS internal memqual MIU4 read clients */ 280 #define TEGRA194_MEMORY_CLIENT_MIU4R 0xb2 281 /* MSS internal memqual MIU4 write clients */ 282 #define TEGRA194_MEMORY_CLIENT_MIU4W 0xb3 283 #define TEGRA194_MEMORY_CLIENT_DPMUR 0xb4 284 #define TEGRA194_MEMORY_CLIENT_DPMUW 0xb5 285 #define TEGRA194_MEMORY_CLIENT_NVL0R 0xb6 286 #define TEGRA194_MEMORY_CLIENT_NVL0W 0xb7 287 #define TEGRA194_MEMORY_CLIENT_NVL1R 0xb8 288 #define TEGRA194_MEMORY_CLIENT_NVL1W 0xb9 289 #define TEGRA194_MEMORY_CLIENT_NVL2R 0xba 290 #define TEGRA194_MEMORY_CLIENT_NVL2W 0xbb 291 /* VI FLACON read clients */ 292 #define TEGRA194_MEMORY_CLIENT_VIFALR 0xbc 293 /* VIFAL write clients */ 294 #define TEGRA194_MEMORY_CLIENT_VIFALW 0xbd 295 /* DLA0ARDA read clients */ 296 #define TEGRA194_MEMORY_CLIENT_DLA0RDA 0xbe 297 /* DLA0 Falcon read clients */ 298 #define TEGRA194_MEMORY_CLIENT_DLA0FALRDB 0xbf 299 /* DLA0 write clients */ 300 #define TEGRA194_MEMORY_CLIENT_DLA0WRA 0xc0 301 /* DLA0 write clients */ 302 #define TEGRA194_MEMORY_CLIENT_DLA0FALWRB 0xc1 303 /* DLA1ARDA read clients */ 304 #define TEGRA194_MEMORY_CLIENT_DLA1RDA 0xc2 305 /* DLA1 Falcon read clients */ 306 #define TEGRA194_MEMORY_CLIENT_DLA1FALRDB 0xc3 307 /* DLA1 write clients */ 308 #define TEGRA194_MEMORY_CLIENT_DLA1WRA 0xc4 309 /* DLA1 write clients */ 310 #define TEGRA194_MEMORY_CLIENT_DLA1FALWRB 0xc5 311 /* PVA0RDA read clients */ 312 #define TEGRA194_MEMORY_CLIENT_PVA0RDA 0xc6 313 /* PVA0RDB read clients */ 314 #define TEGRA194_MEMORY_CLIENT_PVA0RDB 0xc7 315 /* PVA0RDC read clients */ 316 #define TEGRA194_MEMORY_CLIENT_PVA0RDC 0xc8 317 /* PVA0WRA write clients */ 318 #define TEGRA194_MEMORY_CLIENT_PVA0WRA 0xc9 319 /* PVA0WRB write clients */ 320 #define TEGRA194_MEMORY_CLIENT_PVA0WRB 0xca 321 /* PVA0WRC write clients */ 322 #define TEGRA194_MEMORY_CLIENT_PVA0WRC 0xcb 323 /* PVA1RDA read clients */ 324 #define TEGRA194_MEMORY_CLIENT_PVA1RDA 0xcc 325 /* PVA1RDB read clients */ 326 #define TEGRA194_MEMORY_CLIENT_PVA1RDB 0xcd 327 /* PVA1RDC read clients */ 328 #define TEGRA194_MEMORY_CLIENT_PVA1RDC 0xce 329 /* PVA1WRA write clients */ 330 #define TEGRA194_MEMORY_CLIENT_PVA1WRA 0xcf 331 /* PVA1WRB write clients */ 332 #define TEGRA194_MEMORY_CLIENT_PVA1WRB 0xd0 333 /* PVA1WRC write clients */ 334 #define TEGRA194_MEMORY_CLIENT_PVA1WRC 0xd1 335 /* RCE read client */ 336 #define TEGRA194_MEMORY_CLIENT_RCER 0xd2 337 /* RCE write client */ 338 #define TEGRA194_MEMORY_CLIENT_RCEW 0xd3 339 /* RCEDMA read client */ 340 #define TEGRA194_MEMORY_CLIENT_RCEDMAR 0xd4 341 /* RCEDMA write client */ 342 #define TEGRA194_MEMORY_CLIENT_RCEDMAW 0xd5 343 #define TEGRA194_MEMORY_CLIENT_NVENC1SRD 0xd6 344 #define TEGRA194_MEMORY_CLIENT_NVENC1SWR 0xd7 345 /* PCIE0 read clients */ 346 #define TEGRA194_MEMORY_CLIENT_PCIE0R 0xd8 347 /* PCIE0 write clients */ 348 #define TEGRA194_MEMORY_CLIENT_PCIE0W 0xd9 349 /* PCIE1 read clients */ 350 #define TEGRA194_MEMORY_CLIENT_PCIE1R 0xda 351 /* PCIE1 write clients */ 352 #define TEGRA194_MEMORY_CLIENT_PCIE1W 0xdb 353 /* PCIE2 read clients */ 354 #define TEGRA194_MEMORY_CLIENT_PCIE2AR 0xdc 355 /* PCIE2 write clients */ 356 #define TEGRA194_MEMORY_CLIENT_PCIE2AW 0xdd 357 /* PCIE3 read clients */ 358 #define TEGRA194_MEMORY_CLIENT_PCIE3R 0xde 359 /* PCIE3 write clients */ 360 #define TEGRA194_MEMORY_CLIENT_PCIE3W 0xdf 361 /* PCIE4 read clients */ 362 #define TEGRA194_MEMORY_CLIENT_PCIE4R 0xe0 363 /* PCIE4 write clients */ 364 #define TEGRA194_MEMORY_CLIENT_PCIE4W 0xe1 365 /* PCIE5 read clients */ 366 #define TEGRA194_MEMORY_CLIENT_PCIE5R 0xe2 367 /* PCIE5 write clients */ 368 #define TEGRA194_MEMORY_CLIENT_PCIE5W 0xe3 369 /* ISP read client 1 for Crossbar A */ 370 #define TEGRA194_MEMORY_CLIENT_ISPFALW 0xe4 371 #define TEGRA194_MEMORY_CLIENT_NVL3R 0xe5 372 #define TEGRA194_MEMORY_CLIENT_NVL3W 0xe6 373 #define TEGRA194_MEMORY_CLIENT_NVL4R 0xe7 374 #define TEGRA194_MEMORY_CLIENT_NVL4W 0xe8 375 /* DLA0ARDA1 read clients */ 376 #define TEGRA194_MEMORY_CLIENT_DLA0RDA1 0xe9 377 /* DLA1ARDA1 read clients */ 378 #define TEGRA194_MEMORY_CLIENT_DLA1RDA1 0xea 379 /* PVA0RDA1 read clients */ 380 #define TEGRA194_MEMORY_CLIENT_PVA0RDA1 0xeb 381 /* PVA0RDB1 read clients */ 382 #define TEGRA194_MEMORY_CLIENT_PVA0RDB1 0xec 383 /* PVA1RDA1 read clients */ 384 #define TEGRA194_MEMORY_CLIENT_PVA1RDA1 0xed 385 /* PVA1RDB1 read clients */ 386 #define TEGRA194_MEMORY_CLIENT_PVA1RDB1 0xee 387 /* PCIE5r1 read clients */ 388 #define TEGRA194_MEMORY_CLIENT_PCIE5R1 0xef 389 #define TEGRA194_MEMORY_CLIENT_NVENCSRD1 0xf0 390 #define TEGRA194_MEMORY_CLIENT_NVENC1SRD1 0xf1 391 /* ISP read client for Crossbar A */ 392 #define TEGRA194_MEMORY_CLIENT_ISPRA1 0xf2 393 /* PCIE0 read clients */ 394 #define TEGRA194_MEMORY_CLIENT_PCIE0R1 0xf3 395 #define TEGRA194_MEMORY_CLIENT_NVL0RHP 0xf4 396 #define TEGRA194_MEMORY_CLIENT_NVL1RHP 0xf5 397 #define TEGRA194_MEMORY_CLIENT_NVL2RHP 0xf6 398 #define TEGRA194_MEMORY_CLIENT_NVL3RHP 0xf7 399 #define TEGRA194_MEMORY_CLIENT_NVL4RHP 0xf8 400 #define TEGRA194_MEMORY_CLIENT_NVDEC1SRD 0xf9 401 #define TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 0xfa 402 #define TEGRA194_MEMORY_CLIENT_NVDEC1SWR 0xfb 403 /* MSS internal memqual MIU5 read clients */ 404 #define TEGRA194_MEMORY_CLIENT_MIU5R 0xfc 405 /* MSS internal memqual MIU5 write clients */ 406 #define TEGRA194_MEMORY_CLIENT_MIU5W 0xfd 407 /* MSS internal memqual MIU6 read clients */ 408 #define TEGRA194_MEMORY_CLIENT_MIU6R 0xfe 409 /* MSS internal memqual MIU6 write clients */ 410 #define TEGRA194_MEMORY_CLIENT_MIU6W 0xff 411 412 #endif 413
Indexes created Tue Sep 30 07:10:03 GMT 2025