1 /* $NetBSD: as3722.h,v 1.1.1.2 2017/11/30 19:40:51 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0 */ 4 /* 5 * This header provides macros for ams AS3722 device bindings. 6 * 7 * Copyright (c) 2013, NVIDIA Corporation. 8 * 9 * Author: Laxman Dewangan <ldewangan (at) nvidia.com> 10 * 11 */ 12 13 #ifndef __DT_BINDINGS_AS3722_H__ 14 #define __DT_BINDINGS_AS3722_H__ 15 16 /* External control pins */ 17 #define AS3722_EXT_CONTROL_PIN_ENABLE1 1 18 #define AS3722_EXT_CONTROL_PIN_ENABLE2 2 19 #define AS3722_EXT_CONTROL_PIN_ENABLE3 3 20 21 /* Interrupt numbers for AS3722 */ 22 #define AS3722_IRQ_LID 0 23 #define AS3722_IRQ_ACOK 1 24 #define AS3722_IRQ_ENABLE1 2 25 #define AS3722_IRQ_OCCUR_ALARM_SD0 3 26 #define AS3722_IRQ_ONKEY_LONG_PRESS 4 27 #define AS3722_IRQ_ONKEY 5 28 #define AS3722_IRQ_OVTMP 6 29 #define AS3722_IRQ_LOWBAT 7 30 #define AS3722_IRQ_SD0_LV 8 31 #define AS3722_IRQ_SD1_LV 9 32 #define AS3722_IRQ_SD2_LV 10 33 #define AS3722_IRQ_PWM1_OV_PROT 11 34 #define AS3722_IRQ_PWM2_OV_PROT 12 35 #define AS3722_IRQ_ENABLE2 13 36 #define AS3722_IRQ_SD6_LV 14 37 #define AS3722_IRQ_RTC_REP 15 38 #define AS3722_IRQ_RTC_ALARM 16 39 #define AS3722_IRQ_GPIO1 17 40 #define AS3722_IRQ_GPIO2 18 41 #define AS3722_IRQ_GPIO3 19 42 #define AS3722_IRQ_GPIO4 20 43 #define AS3722_IRQ_GPIO5 21 44 #define AS3722_IRQ_WATCHDOG 22 45 #define AS3722_IRQ_ENABLE3 23 46 #define AS3722_IRQ_TEMP_SD0_SHUTDOWN 24 47 #define AS3722_IRQ_TEMP_SD1_SHUTDOWN 25 48 #define AS3722_IRQ_TEMP_SD2_SHUTDOWN 26 49 #define AS3722_IRQ_TEMP_SD0_ALARM 27 50 #define AS3722_IRQ_TEMP_SD1_ALARM 28 51 #define AS3722_IRQ_TEMP_SD6_ALARM 29 52 #define AS3722_IRQ_OCCUR_ALARM_SD6 30 53 #define AS3722_IRQ_ADC 31 54 55 #endif /* __DT_BINDINGS_AS3722_H__ */ 56
Indexes created Sat Sep 27 21:09:56 GMT 2025