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      1 /*	$NetBSD: mt7629-resets.h,v 1.1.1.1 2020/01/03 14:33:06 skrll Exp $	*/
      2 
      3 /* SPDX-License-Identifier: GPL-2.0 */
      4 /*
      5  * Copyright (C) 2019 MediaTek Inc.
      6  */
      7 
      8 #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7629
      9 #define _DT_BINDINGS_RESET_CONTROLLER_MT7629
     10 
     11 /* INFRACFG resets */
     12 #define MT7629_INFRA_EMI_MPU_RST		0
     13 #define MT7629_INFRA_UART5_RST			2
     14 #define MT7629_INFRA_CIRQ_EINT_RST		3
     15 #define MT7629_INFRA_APXGPT_RST			4
     16 #define MT7629_INFRA_SCPSYS_RST			5
     17 #define MT7629_INFRA_KP_RST			6
     18 #define MT7629_INFRA_SPI1_RST			7
     19 #define MT7629_INFRA_SPI4_RST			8
     20 #define MT7629_INFRA_SYSTIMER_RST		9
     21 #define MT7629_INFRA_IRRX_RST			10
     22 #define MT7629_INFRA_AO_BUS_RST			16
     23 #define MT7629_INFRA_EMI_RST			32
     24 #define MT7629_INFRA_APMIXED_RST		35
     25 #define MT7629_INFRA_MIPI_RST			36
     26 #define MT7629_INFRA_TRNG_RST			37
     27 #define MT7629_INFRA_SYSCIRQ_RST		38
     28 #define MT7629_INFRA_MIPI_CSI_RST		39
     29 #define MT7629_INFRA_GCE_FAXI_RST		40
     30 #define MT7629_INFRA_I2C_SRAM_RST		41
     31 #define MT7629_INFRA_IOMMU_RST			47
     32 
     33 /* PERICFG resets */
     34 #define MT7629_PERI_UART0_SW_RST		0
     35 #define MT7629_PERI_UART1_SW_RST		1
     36 #define MT7629_PERI_UART2_SW_RST		2
     37 #define MT7629_PERI_BTIF_SW_RST			6
     38 #define MT7629_PERI_PWN_SW_RST			8
     39 #define MT7629_PERI_DMA_SW_RST			11
     40 #define MT7629_PERI_NFI_SW_RST			14
     41 #define MT7629_PERI_I2C0_SW_RST			22
     42 #define MT7629_PERI_SPI0_SW_RST			33
     43 #define MT7629_PERI_SPI1_SW_RST			34
     44 #define MT7629_PERI_FLASHIF_SW_RST		36
     45 
     46 /* PCIe Subsystem resets */
     47 #define MT7629_PCIE1_CORE_RST			19
     48 #define MT7629_PCIE1_MMIO_RST			20
     49 #define MT7629_PCIE1_HRST			21
     50 #define MT7629_PCIE1_USER_RST			22
     51 #define MT7629_PCIE1_PIPE_RST			23
     52 #define MT7629_PCIE0_CORE_RST			27
     53 #define MT7629_PCIE0_MMIO_RST			28
     54 #define MT7629_PCIE0_HRST			29
     55 #define MT7629_PCIE0_USER_RST			30
     56 #define MT7629_PCIE0_PIPE_RST			31
     57 
     58 /* SSUSB Subsystem resets */
     59 #define MT7629_SSUSB_PHY_PWR_RST		3
     60 #define MT7629_SSUSB_MAC_PWR_RST		4
     61 
     62 /* ETH Subsystem resets */
     63 #define MT7629_ETHSYS_SYS_RST			0
     64 #define MT7629_ETHSYS_MCM_RST			2
     65 #define MT7629_ETHSYS_HSDMA_RST			5
     66 #define MT7629_ETHSYS_FE_RST			6
     67 #define MT7629_ETHSYS_ESW_RST			16
     68 #define MT7629_ETHSYS_GMAC_RST			23
     69 #define MT7629_ETHSYS_EPHY_RST			24
     70 #define MT7629_ETHSYS_CRYPTO_RST		29
     71 #define MT7629_ETHSYS_PPE_RST			31
     72 
     73 #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT7629 */
     74