1 /* $NetBSD: stm32mp1-resets.h,v 1.1.1.2 2021/11/07 16:49:57 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 4 /* 5 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved 6 * Author: Gabriel Fernandez <gabriel.fernandez (at) st.com> for STMicroelectronics. 7 */ 8 9 #ifndef _DT_BINDINGS_STM32MP1_RESET_H_ 10 #define _DT_BINDINGS_STM32MP1_RESET_H_ 11 12 #define MCU_HOLD_BOOT_R 2144 13 #define LTDC_R 3072 14 #define DSI_R 3076 15 #define DDRPERFM_R 3080 16 #define USBPHY_R 3088 17 #define SPI6_R 3136 18 #define I2C4_R 3138 19 #define I2C6_R 3139 20 #define USART1_R 3140 21 #define STGEN_R 3156 22 #define GPIOZ_R 3200 23 #define CRYP1_R 3204 24 #define HASH1_R 3205 25 #define RNG1_R 3206 26 #define AXIM_R 3216 27 #define GPU_R 3269 28 #define ETHMAC_R 3274 29 #define FMC_R 3276 30 #define QSPI_R 3278 31 #define SDMMC1_R 3280 32 #define SDMMC2_R 3281 33 #define CRC1_R 3284 34 #define USBH_R 3288 35 #define MDMA_R 3328 36 #define MCU_R 8225 37 #define TIM2_R 19456 38 #define TIM3_R 19457 39 #define TIM4_R 19458 40 #define TIM5_R 19459 41 #define TIM6_R 19460 42 #define TIM7_R 19461 43 #define TIM12_R 16462 44 #define TIM13_R 16463 45 #define TIM14_R 16464 46 #define LPTIM1_R 19465 47 #define SPI2_R 19467 48 #define SPI3_R 19468 49 #define USART2_R 19470 50 #define USART3_R 19471 51 #define UART4_R 19472 52 #define UART5_R 19473 53 #define UART7_R 19474 54 #define UART8_R 19475 55 #define I2C1_R 19477 56 #define I2C2_R 19478 57 #define I2C3_R 19479 58 #define I2C5_R 19480 59 #define SPDIF_R 19482 60 #define CEC_R 19483 61 #define DAC12_R 19485 62 #define MDIO_R 19847 63 #define TIM1_R 19520 64 #define TIM8_R 19521 65 #define TIM15_R 19522 66 #define TIM16_R 19523 67 #define TIM17_R 19524 68 #define SPI1_R 19528 69 #define SPI4_R 19529 70 #define SPI5_R 19530 71 #define USART6_R 19533 72 #define SAI1_R 19536 73 #define SAI2_R 19537 74 #define SAI3_R 19538 75 #define DFSDM_R 19540 76 #define FDCAN_R 19544 77 #define LPTIM2_R 19584 78 #define LPTIM3_R 19585 79 #define LPTIM4_R 19586 80 #define LPTIM5_R 19587 81 #define SAI4_R 19592 82 #define SYSCFG_R 19595 83 #define VREF_R 19597 84 #define TMPSENS_R 19600 85 #define PMBCTRL_R 19601 86 #define DMA1_R 19648 87 #define DMA2_R 19649 88 #define DMAMUX_R 19650 89 #define ADC12_R 19653 90 #define USBO_R 19656 91 #define SDMMC3_R 19664 92 #define CAMITF_R 19712 93 #define CRYP2_R 19716 94 #define HASH2_R 19717 95 #define RNG2_R 19718 96 #define CRC2_R 19719 97 #define HSEM_R 19723 98 #define MBOX_R 19724 99 #define GPIOA_R 19776 100 #define GPIOB_R 19777 101 #define GPIOC_R 19778 102 #define GPIOD_R 19779 103 #define GPIOE_R 19780 104 #define GPIOF_R 19781 105 #define GPIOG_R 19782 106 #define GPIOH_R 19783 107 #define GPIOI_R 19784 108 #define GPIOJ_R 19785 109 #define GPIOK_R 19786 110 111 /* SCMI reset domain identifiers */ 112 #define RST_SCMI0_SPI6 0 113 #define RST_SCMI0_I2C4 1 114 #define RST_SCMI0_I2C6 2 115 #define RST_SCMI0_USART1 3 116 #define RST_SCMI0_STGEN 4 117 #define RST_SCMI0_GPIOZ 5 118 #define RST_SCMI0_CRYP1 6 119 #define RST_SCMI0_HASH1 7 120 #define RST_SCMI0_RNG1 8 121 #define RST_SCMI0_MDMA 9 122 #define RST_SCMI0_MCU 10 123 #define RST_SCMI0_MCU_HOLD_BOOT 11 124 125 #endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */ 126
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