drm_mode.h revision 037b3c26
122944501Smrg/*
222944501Smrg * Copyright (c) 2007 Dave Airlie <airlied@linux.ie>
322944501Smrg * Copyright (c) 2007 Jakob Bornecrantz <wallbraker@gmail.com>
422944501Smrg * Copyright (c) 2008 Red Hat Inc.
522944501Smrg * Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA
622944501Smrg * Copyright (c) 2007-2008 Intel Corporation
722944501Smrg *
822944501Smrg * Permission is hereby granted, free of charge, to any person obtaining a
922944501Smrg * copy of this software and associated documentation files (the "Software"),
1022944501Smrg * to deal in the Software without restriction, including without limitation
1122944501Smrg * the rights to use, copy, modify, merge, publish, distribute, sublicense,
1222944501Smrg * and/or sell copies of the Software, and to permit persons to whom the
1322944501Smrg * Software is furnished to do so, subject to the following conditions:
1422944501Smrg *
1522944501Smrg * The above copyright notice and this permission notice shall be included in
1622944501Smrg * all copies or substantial portions of the Software.
1722944501Smrg *
1822944501Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1922944501Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
2022944501Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
2122944501Smrg * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
2222944501Smrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
2322944501Smrg * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
2422944501Smrg * IN THE SOFTWARE.
2522944501Smrg */
2622944501Smrg
2722944501Smrg#ifndef _DRM_MODE_H
2822944501Smrg#define _DRM_MODE_H
2922944501Smrg
303f012e29Smrg#include "drm.h"
313f012e29Smrg
32037b3c26Smrg#if defined(__cplusplus)
33037b3c26Smrgextern "C" {
34037b3c26Smrg#endif
35037b3c26Smrg
3622944501Smrg#define DRM_DISPLAY_INFO_LEN	32
3722944501Smrg#define DRM_CONNECTOR_NAME_LEN	32
3822944501Smrg#define DRM_DISPLAY_MODE_LEN	32
3922944501Smrg#define DRM_PROP_NAME_LEN	32
4022944501Smrg
4122944501Smrg#define DRM_MODE_TYPE_BUILTIN	(1<<0)
4222944501Smrg#define DRM_MODE_TYPE_CLOCK_C	((1<<1) | DRM_MODE_TYPE_BUILTIN)
4322944501Smrg#define DRM_MODE_TYPE_CRTC_C	((1<<2) | DRM_MODE_TYPE_BUILTIN)
4422944501Smrg#define DRM_MODE_TYPE_PREFERRED	(1<<3)
4522944501Smrg#define DRM_MODE_TYPE_DEFAULT	(1<<4)
4622944501Smrg#define DRM_MODE_TYPE_USERDEF	(1<<5)
4722944501Smrg#define DRM_MODE_TYPE_DRIVER	(1<<6)
4822944501Smrg
4922944501Smrg/* Video mode flags */
5022944501Smrg/* bit compatible with the xorg definitions. */
51e88f27b3Smrg#define DRM_MODE_FLAG_PHSYNC			(1<<0)
52e88f27b3Smrg#define DRM_MODE_FLAG_NHSYNC			(1<<1)
53e88f27b3Smrg#define DRM_MODE_FLAG_PVSYNC			(1<<2)
54e88f27b3Smrg#define DRM_MODE_FLAG_NVSYNC			(1<<3)
55e88f27b3Smrg#define DRM_MODE_FLAG_INTERLACE			(1<<4)
56e88f27b3Smrg#define DRM_MODE_FLAG_DBLSCAN			(1<<5)
57e88f27b3Smrg#define DRM_MODE_FLAG_CSYNC			(1<<6)
58e88f27b3Smrg#define DRM_MODE_FLAG_PCSYNC			(1<<7)
59e88f27b3Smrg#define DRM_MODE_FLAG_NCSYNC			(1<<8)
60e88f27b3Smrg#define DRM_MODE_FLAG_HSKEW			(1<<9) /* hskew provided */
61e88f27b3Smrg#define DRM_MODE_FLAG_BCAST			(1<<10)
62e88f27b3Smrg#define DRM_MODE_FLAG_PIXMUX			(1<<11)
63e88f27b3Smrg#define DRM_MODE_FLAG_DBLCLK			(1<<12)
64e88f27b3Smrg#define DRM_MODE_FLAG_CLKDIV2			(1<<13)
653f012e29Smrg /*
663f012e29Smrg  * When adding a new stereo mode don't forget to adjust DRM_MODE_FLAGS_3D_MAX
673f012e29Smrg  * (define not exposed to user space).
683f012e29Smrg  */
69e88f27b3Smrg#define DRM_MODE_FLAG_3D_MASK			(0x1f<<14)
70e88f27b3Smrg#define  DRM_MODE_FLAG_3D_NONE			(0<<14)
71e88f27b3Smrg#define  DRM_MODE_FLAG_3D_FRAME_PACKING		(1<<14)
72e88f27b3Smrg#define  DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE	(2<<14)
73e88f27b3Smrg#define  DRM_MODE_FLAG_3D_LINE_ALTERNATIVE	(3<<14)
74e88f27b3Smrg#define  DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL	(4<<14)
75e88f27b3Smrg#define  DRM_MODE_FLAG_3D_L_DEPTH		(5<<14)
76e88f27b3Smrg#define  DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH	(6<<14)
77e88f27b3Smrg#define  DRM_MODE_FLAG_3D_TOP_AND_BOTTOM	(7<<14)
78e88f27b3Smrg#define  DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF	(8<<14)
79e88f27b3Smrg
8022944501Smrg
8122944501Smrg/* DPMS flags */
8222944501Smrg/* bit compatible with the xorg definitions. */
8322944501Smrg#define DRM_MODE_DPMS_ON	0
8422944501Smrg#define DRM_MODE_DPMS_STANDBY	1
8522944501Smrg#define DRM_MODE_DPMS_SUSPEND	2
8622944501Smrg#define DRM_MODE_DPMS_OFF	3
8722944501Smrg
8822944501Smrg/* Scaling mode options */
8922944501Smrg#define DRM_MODE_SCALE_NONE		0 /* Unmodified timing (display or
9022944501Smrg					     software can still scale) */
9122944501Smrg#define DRM_MODE_SCALE_FULLSCREEN	1 /* Full screen, ignore aspect */
9222944501Smrg#define DRM_MODE_SCALE_CENTER		2 /* Centered, no scaling */
9322944501Smrg#define DRM_MODE_SCALE_ASPECT		3 /* Full screen, preserve aspect */
9422944501Smrg
953f012e29Smrg/* Picture aspect ratio options */
963f012e29Smrg#define DRM_MODE_PICTURE_ASPECT_NONE	0
973f012e29Smrg#define DRM_MODE_PICTURE_ASPECT_4_3	1
983f012e29Smrg#define DRM_MODE_PICTURE_ASPECT_16_9	2
993f012e29Smrg
10022944501Smrg/* Dithering mode options */
10122944501Smrg#define DRM_MODE_DITHERING_OFF	0
10222944501Smrg#define DRM_MODE_DITHERING_ON	1
103d049871aSmrg#define DRM_MODE_DITHERING_AUTO 2
10422944501Smrg
10513d1d17dSmrg/* Dirty info options */
10613d1d17dSmrg#define DRM_MODE_DIRTY_OFF      0
10713d1d17dSmrg#define DRM_MODE_DIRTY_ON       1
10813d1d17dSmrg#define DRM_MODE_DIRTY_ANNOTATE 2
10913d1d17dSmrg
11022944501Smrgstruct drm_mode_modeinfo {
11122944501Smrg	__u32 clock;
1123f012e29Smrg	__u16 hdisplay;
1133f012e29Smrg	__u16 hsync_start;
1143f012e29Smrg	__u16 hsync_end;
1153f012e29Smrg	__u16 htotal;
1163f012e29Smrg	__u16 hskew;
1173f012e29Smrg	__u16 vdisplay;
1183f012e29Smrg	__u16 vsync_start;
1193f012e29Smrg	__u16 vsync_end;
1203f012e29Smrg	__u16 vtotal;
1213f012e29Smrg	__u16 vscan;
12222944501Smrg
123d049871aSmrg	__u32 vrefresh;
12422944501Smrg
12522944501Smrg	__u32 flags;
12622944501Smrg	__u32 type;
12722944501Smrg	char name[DRM_DISPLAY_MODE_LEN];
12822944501Smrg};
12922944501Smrg
13022944501Smrgstruct drm_mode_card_res {
13122944501Smrg	__u64 fb_id_ptr;
13222944501Smrg	__u64 crtc_id_ptr;
13322944501Smrg	__u64 connector_id_ptr;
13422944501Smrg	__u64 encoder_id_ptr;
13522944501Smrg	__u32 count_fbs;
13622944501Smrg	__u32 count_crtcs;
13722944501Smrg	__u32 count_connectors;
13822944501Smrg	__u32 count_encoders;
1393f012e29Smrg	__u32 min_width;
1403f012e29Smrg	__u32 max_width;
1413f012e29Smrg	__u32 min_height;
1423f012e29Smrg	__u32 max_height;
14322944501Smrg};
14422944501Smrg
14522944501Smrgstruct drm_mode_crtc {
14622944501Smrg	__u64 set_connectors_ptr;
14722944501Smrg	__u32 count_connectors;
14822944501Smrg
14922944501Smrg	__u32 crtc_id; /**< Id */
15022944501Smrg	__u32 fb_id; /**< Id of framebuffer */
15122944501Smrg
1523f012e29Smrg	__u32 x; /**< x Position on the framebuffer */
1533f012e29Smrg	__u32 y; /**< y Position on the framebuffer */
15422944501Smrg
15522944501Smrg	__u32 gamma_size;
15622944501Smrg	__u32 mode_valid;
15722944501Smrg	struct drm_mode_modeinfo mode;
15822944501Smrg};
15922944501Smrg
1603f012e29Smrg#define DRM_MODE_PRESENT_TOP_FIELD	(1<<0)
1613f012e29Smrg#define DRM_MODE_PRESENT_BOTTOM_FIELD	(1<<1)
162e88f27b3Smrg
163e88f27b3Smrg/* Planes blend with or override other bits on the CRTC */
164e88f27b3Smrgstruct drm_mode_set_plane {
165e88f27b3Smrg	__u32 plane_id;
166e88f27b3Smrg	__u32 crtc_id;
167e88f27b3Smrg	__u32 fb_id; /* fb object contains surface format type */
1683f012e29Smrg	__u32 flags; /* see above flags */
169e88f27b3Smrg
170e88f27b3Smrg	/* Signed dest location allows it to be partially off screen */
1713f012e29Smrg	__s32 crtc_x;
1723f012e29Smrg	__s32 crtc_y;
1733f012e29Smrg	__u32 crtc_w;
1743f012e29Smrg	__u32 crtc_h;
175e88f27b3Smrg
176e88f27b3Smrg	/* Source values are 16.16 fixed point */
1773f012e29Smrg	__u32 src_x;
1783f012e29Smrg	__u32 src_y;
1793f012e29Smrg	__u32 src_h;
1803f012e29Smrg	__u32 src_w;
181e88f27b3Smrg};
182e88f27b3Smrg
183e88f27b3Smrgstruct drm_mode_get_plane {
184e88f27b3Smrg	__u32 plane_id;
185e88f27b3Smrg
186e88f27b3Smrg	__u32 crtc_id;
187e88f27b3Smrg	__u32 fb_id;
188e88f27b3Smrg
189e88f27b3Smrg	__u32 possible_crtcs;
190e88f27b3Smrg	__u32 gamma_size;
191e88f27b3Smrg
192e88f27b3Smrg	__u32 count_format_types;
193e88f27b3Smrg	__u64 format_type_ptr;
194e88f27b3Smrg};
195e88f27b3Smrg
196e88f27b3Smrgstruct drm_mode_get_plane_res {
197e88f27b3Smrg	__u64 plane_id_ptr;
198e88f27b3Smrg	__u32 count_planes;
199e88f27b3Smrg};
200e88f27b3Smrg
20122944501Smrg#define DRM_MODE_ENCODER_NONE	0
20222944501Smrg#define DRM_MODE_ENCODER_DAC	1
20322944501Smrg#define DRM_MODE_ENCODER_TMDS	2
20422944501Smrg#define DRM_MODE_ENCODER_LVDS	3
20522944501Smrg#define DRM_MODE_ENCODER_TVDAC	4
20608d7334dSsnj#define DRM_MODE_ENCODER_VIRTUAL 5
20708d7334dSsnj#define DRM_MODE_ENCODER_DSI	6
20808d7334dSsnj#define DRM_MODE_ENCODER_DPMST	7
209037b3c26Smrg#define DRM_MODE_ENCODER_DPI	8
21022944501Smrg
21122944501Smrgstruct drm_mode_get_encoder {
21222944501Smrg	__u32 encoder_id;
21322944501Smrg	__u32 encoder_type;
21422944501Smrg
21522944501Smrg	__u32 crtc_id; /**< Id of crtc */
21622944501Smrg
21722944501Smrg	__u32 possible_crtcs;
21822944501Smrg	__u32 possible_clones;
21922944501Smrg};
22022944501Smrg
22122944501Smrg/* This is for connectors with multiple signal types. */
22222944501Smrg/* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */
22322944501Smrg#define DRM_MODE_SUBCONNECTOR_Automatic	0
22422944501Smrg#define DRM_MODE_SUBCONNECTOR_Unknown	0
22522944501Smrg#define DRM_MODE_SUBCONNECTOR_DVID	3
22622944501Smrg#define DRM_MODE_SUBCONNECTOR_DVIA	4
22722944501Smrg#define DRM_MODE_SUBCONNECTOR_Composite	5
22822944501Smrg#define DRM_MODE_SUBCONNECTOR_SVIDEO	6
22922944501Smrg#define DRM_MODE_SUBCONNECTOR_Component	8
23022944501Smrg#define DRM_MODE_SUBCONNECTOR_SCART	9
23122944501Smrg
23222944501Smrg#define DRM_MODE_CONNECTOR_Unknown	0
23322944501Smrg#define DRM_MODE_CONNECTOR_VGA		1
23422944501Smrg#define DRM_MODE_CONNECTOR_DVII		2
23522944501Smrg#define DRM_MODE_CONNECTOR_DVID		3
23622944501Smrg#define DRM_MODE_CONNECTOR_DVIA		4
23722944501Smrg#define DRM_MODE_CONNECTOR_Composite	5
23822944501Smrg#define DRM_MODE_CONNECTOR_SVIDEO	6
23922944501Smrg#define DRM_MODE_CONNECTOR_LVDS		7
24022944501Smrg#define DRM_MODE_CONNECTOR_Component	8
24122944501Smrg#define DRM_MODE_CONNECTOR_9PinDIN	9
24222944501Smrg#define DRM_MODE_CONNECTOR_DisplayPort	10
24322944501Smrg#define DRM_MODE_CONNECTOR_HDMIA	11
24422944501Smrg#define DRM_MODE_CONNECTOR_HDMIB	12
24522944501Smrg#define DRM_MODE_CONNECTOR_TV		13
246d049871aSmrg#define DRM_MODE_CONNECTOR_eDP		14
24708d7334dSsnj#define DRM_MODE_CONNECTOR_VIRTUAL      15
24808d7334dSsnj#define DRM_MODE_CONNECTOR_DSI		16
249037b3c26Smrg#define DRM_MODE_CONNECTOR_DPI		17
25022944501Smrg
25122944501Smrgstruct drm_mode_get_connector {
25222944501Smrg
25322944501Smrg	__u64 encoders_ptr;
25422944501Smrg	__u64 modes_ptr;
25522944501Smrg	__u64 props_ptr;
25622944501Smrg	__u64 prop_values_ptr;
25722944501Smrg
25822944501Smrg	__u32 count_modes;
25922944501Smrg	__u32 count_props;
26022944501Smrg	__u32 count_encoders;
26122944501Smrg
26222944501Smrg	__u32 encoder_id; /**< Current Encoder */
26322944501Smrg	__u32 connector_id; /**< Id */
26422944501Smrg	__u32 connector_type;
26522944501Smrg	__u32 connector_type_id;
26622944501Smrg
26722944501Smrg	__u32 connection;
2683f012e29Smrg	__u32 mm_width;  /**< width in millimeters */
2693f012e29Smrg	__u32 mm_height; /**< height in millimeters */
27022944501Smrg	__u32 subpixel;
2713f012e29Smrg
2723f012e29Smrg	__u32 pad;
27322944501Smrg};
27422944501Smrg
27522944501Smrg#define DRM_MODE_PROP_PENDING	(1<<0)
27622944501Smrg#define DRM_MODE_PROP_RANGE	(1<<1)
27722944501Smrg#define DRM_MODE_PROP_IMMUTABLE	(1<<2)
27822944501Smrg#define DRM_MODE_PROP_ENUM	(1<<3) /* enumerated type with text strings */
27922944501Smrg#define DRM_MODE_PROP_BLOB	(1<<4)
280e88f27b3Smrg#define DRM_MODE_PROP_BITMASK	(1<<5) /* bitmask of enumerated types */
28122944501Smrg
28208d7334dSsnj/* non-extended types: legacy bitmask, one bit per type: */
28308d7334dSsnj#define DRM_MODE_PROP_LEGACY_TYPE  ( \
28408d7334dSsnj		DRM_MODE_PROP_RANGE | \
28508d7334dSsnj		DRM_MODE_PROP_ENUM | \
28608d7334dSsnj		DRM_MODE_PROP_BLOB | \
28708d7334dSsnj		DRM_MODE_PROP_BITMASK)
28808d7334dSsnj
28908d7334dSsnj/* extended-types: rather than continue to consume a bit per type,
29008d7334dSsnj * grab a chunk of the bits to use as integer type id.
29108d7334dSsnj */
29208d7334dSsnj#define DRM_MODE_PROP_EXTENDED_TYPE	0x0000ffc0
29308d7334dSsnj#define DRM_MODE_PROP_TYPE(n)		((n) << 6)
29408d7334dSsnj#define DRM_MODE_PROP_OBJECT		DRM_MODE_PROP_TYPE(1)
29508d7334dSsnj#define DRM_MODE_PROP_SIGNED_RANGE	DRM_MODE_PROP_TYPE(2)
29608d7334dSsnj
2973f012e29Smrg/* the PROP_ATOMIC flag is used to hide properties from userspace that
2983f012e29Smrg * is not aware of atomic properties.  This is mostly to work around
2993f012e29Smrg * older userspace (DDX drivers) that read/write each prop they find,
3003f012e29Smrg * witout being aware that this could be triggering a lengthy modeset.
3013f012e29Smrg */
3023f012e29Smrg#define DRM_MODE_PROP_ATOMIC        0x80000000
3033f012e29Smrg
30422944501Smrgstruct drm_mode_property_enum {
30522944501Smrg	__u64 value;
30622944501Smrg	char name[DRM_PROP_NAME_LEN];
30722944501Smrg};
30822944501Smrg
30922944501Smrgstruct drm_mode_get_property {
31022944501Smrg	__u64 values_ptr; /* values and blob lengths */
31122944501Smrg	__u64 enum_blob_ptr; /* enum and blob id ptrs */
31222944501Smrg
31322944501Smrg	__u32 prop_id;
31422944501Smrg	__u32 flags;
31522944501Smrg	char name[DRM_PROP_NAME_LEN];
31622944501Smrg
31722944501Smrg	__u32 count_values;
3183f012e29Smrg	/* This is only used to count enum values, not blobs. The _blobs is
3193f012e29Smrg	 * simply because of a historical reason, i.e. backwards compat. */
32022944501Smrg	__u32 count_enum_blobs;
32122944501Smrg};
32222944501Smrg
32322944501Smrgstruct drm_mode_connector_set_property {
32422944501Smrg	__u64 value;
32522944501Smrg	__u32 prop_id;
32622944501Smrg	__u32 connector_id;
32722944501Smrg};
32822944501Smrg
329e88f27b3Smrg#define DRM_MODE_OBJECT_CRTC 0xcccccccc
330e88f27b3Smrg#define DRM_MODE_OBJECT_CONNECTOR 0xc0c0c0c0
331e88f27b3Smrg#define DRM_MODE_OBJECT_ENCODER 0xe0e0e0e0
332e88f27b3Smrg#define DRM_MODE_OBJECT_MODE 0xdededede
333e88f27b3Smrg#define DRM_MODE_OBJECT_PROPERTY 0xb0b0b0b0
334e88f27b3Smrg#define DRM_MODE_OBJECT_FB 0xfbfbfbfb
335e88f27b3Smrg#define DRM_MODE_OBJECT_BLOB 0xbbbbbbbb
336e88f27b3Smrg#define DRM_MODE_OBJECT_PLANE 0xeeeeeeee
3373f012e29Smrg#define DRM_MODE_OBJECT_ANY 0
338e88f27b3Smrg
339e88f27b3Smrgstruct drm_mode_obj_get_properties {
340e88f27b3Smrg	__u64 props_ptr;
341e88f27b3Smrg	__u64 prop_values_ptr;
342e88f27b3Smrg	__u32 count_props;
343e88f27b3Smrg	__u32 obj_id;
344e88f27b3Smrg	__u32 obj_type;
345e88f27b3Smrg};
346e88f27b3Smrg
347e88f27b3Smrgstruct drm_mode_obj_set_property {
348e88f27b3Smrg	__u64 value;
349e88f27b3Smrg	__u32 prop_id;
350e88f27b3Smrg	__u32 obj_id;
351e88f27b3Smrg	__u32 obj_type;
352e88f27b3Smrg};
353e88f27b3Smrg
35422944501Smrgstruct drm_mode_get_blob {
35522944501Smrg	__u32 blob_id;
35622944501Smrg	__u32 length;
35722944501Smrg	__u64 data;
35822944501Smrg};
35922944501Smrg
36022944501Smrgstruct drm_mode_fb_cmd {
36122944501Smrg	__u32 fb_id;
3623f012e29Smrg	__u32 width;
3633f012e29Smrg	__u32 height;
36422944501Smrg	__u32 pitch;
36522944501Smrg	__u32 bpp;
36622944501Smrg	__u32 depth;
36722944501Smrg	/* driver specific handle */
36822944501Smrg	__u32 handle;
36922944501Smrg};
37022944501Smrg
3713f012e29Smrg#define DRM_MODE_FB_INTERLACED	(1<<0) /* for interlaced framebuffers */
3723f012e29Smrg#define DRM_MODE_FB_MODIFIERS	(1<<1) /* enables ->modifer[] */
373e88f27b3Smrg
374e88f27b3Smrgstruct drm_mode_fb_cmd2 {
375e88f27b3Smrg	__u32 fb_id;
3763f012e29Smrg	__u32 width;
3773f012e29Smrg	__u32 height;
378e88f27b3Smrg	__u32 pixel_format; /* fourcc code from drm_fourcc.h */
3793f012e29Smrg	__u32 flags; /* see above flags */
380e88f27b3Smrg
381e88f27b3Smrg	/*
382e88f27b3Smrg	 * In case of planar formats, this ioctl allows up to 4
383e88f27b3Smrg	 * buffer objects with offsets and pitches per plane.
384e88f27b3Smrg	 * The pitch and offset order is dictated by the fourcc,
385e88f27b3Smrg	 * e.g. NV12 (http://fourcc.org/yuv.php#NV12) is described as:
386e88f27b3Smrg	 *
387e88f27b3Smrg	 *   YUV 4:2:0 image with a plane of 8 bit Y samples
388e88f27b3Smrg	 *   followed by an interleaved U/V plane containing
389e88f27b3Smrg	 *   8 bit 2x2 subsampled colour difference samples.
390e88f27b3Smrg	 *
3913f012e29Smrg	 * So it would consist of Y as offsets[0] and UV as
3923f012e29Smrg	 * offsets[1].  Note that offsets[0] will generally
3933f012e29Smrg	 * be 0 (but this is not required).
3943f012e29Smrg	 *
3953f012e29Smrg	 * To accommodate tiled, compressed, etc formats, a per-plane
3963f012e29Smrg	 * modifier can be specified.  The default value of zero
3973f012e29Smrg	 * indicates "native" format as specified by the fourcc.
3983f012e29Smrg	 * Vendor specific modifier token.  This allows, for example,
3993f012e29Smrg	 * different tiling/swizzling pattern on different planes.
4003f012e29Smrg	 * See discussion above of DRM_FORMAT_MOD_xxx.
401e88f27b3Smrg	 */
402e88f27b3Smrg	__u32 handles[4];
403e88f27b3Smrg	__u32 pitches[4]; /* pitch for each plane */
404e88f27b3Smrg	__u32 offsets[4]; /* offset of each plane */
4053f012e29Smrg	__u64 modifier[4]; /* ie, tiling, compressed (per plane) */
406e88f27b3Smrg};
407e88f27b3Smrg
40822944501Smrg#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01
40922944501Smrg#define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02
41022944501Smrg#define DRM_MODE_FB_DIRTY_FLAGS         0x03
41122944501Smrg
4123f012e29Smrg#define DRM_MODE_FB_DIRTY_MAX_CLIPS     256
4133f012e29Smrg
41422944501Smrg/*
41522944501Smrg * Mark a region of a framebuffer as dirty.
41622944501Smrg *
41722944501Smrg * Some hardware does not automatically update display contents
41822944501Smrg * as a hardware or software draw to a framebuffer. This ioctl
41922944501Smrg * allows userspace to tell the kernel and the hardware what
42022944501Smrg * regions of the framebuffer have changed.
42122944501Smrg *
42222944501Smrg * The kernel or hardware is free to update more then just the
42322944501Smrg * region specified by the clip rects. The kernel or hardware
42422944501Smrg * may also delay and/or coalesce several calls to dirty into a
42522944501Smrg * single update.
42622944501Smrg *
42722944501Smrg * Userspace may annotate the updates, the annotates are a
42822944501Smrg * promise made by the caller that the change is either a copy
42922944501Smrg * of pixels or a fill of a single color in the region specified.
43022944501Smrg *
43122944501Smrg * If the DRM_MODE_FB_DIRTY_ANNOTATE_COPY flag is given then
43222944501Smrg * the number of updated regions are half of num_clips given,
43322944501Smrg * where the clip rects are paired in src and dst. The width and
43422944501Smrg * height of each one of the pairs must match.
43522944501Smrg *
43622944501Smrg * If the DRM_MODE_FB_DIRTY_ANNOTATE_FILL flag is given the caller
43722944501Smrg * promises that the region specified of the clip rects is filled
43822944501Smrg * completely with a single color as given in the color argument.
43922944501Smrg */
44022944501Smrg
44122944501Smrgstruct drm_mode_fb_dirty_cmd {
44222944501Smrg	__u32 fb_id;
44322944501Smrg	__u32 flags;
44422944501Smrg	__u32 color;
44522944501Smrg	__u32 num_clips;
44622944501Smrg	__u64 clips_ptr;
44722944501Smrg};
44822944501Smrg
44922944501Smrgstruct drm_mode_mode_cmd {
45022944501Smrg	__u32 connector_id;
45122944501Smrg	struct drm_mode_modeinfo mode;
45222944501Smrg};
45322944501Smrg
4543f012e29Smrg#define DRM_MODE_CURSOR_BO	0x01
4553f012e29Smrg#define DRM_MODE_CURSOR_MOVE	0x02
4563f012e29Smrg#define DRM_MODE_CURSOR_FLAGS	0x03
45722944501Smrg
45822944501Smrg/*
4593f012e29Smrg * depending on the value in flags different members are used.
46022944501Smrg *
46122944501Smrg * CURSOR_BO uses
4623f012e29Smrg *    crtc_id
46322944501Smrg *    width
46422944501Smrg *    height
4653f012e29Smrg *    handle - if 0 turns the cursor off
46622944501Smrg *
46722944501Smrg * CURSOR_MOVE uses
4683f012e29Smrg *    crtc_id
46922944501Smrg *    x
47022944501Smrg *    y
47122944501Smrg */
47222944501Smrgstruct drm_mode_cursor {
47322944501Smrg	__u32 flags;
47422944501Smrg	__u32 crtc_id;
47522944501Smrg	__s32 x;
47622944501Smrg	__s32 y;
47722944501Smrg	__u32 width;
47822944501Smrg	__u32 height;
47922944501Smrg	/* driver specific handle */
48022944501Smrg	__u32 handle;
48122944501Smrg};
48222944501Smrg
483e88f27b3Smrgstruct drm_mode_cursor2 {
484e88f27b3Smrg	__u32 flags;
485e88f27b3Smrg	__u32 crtc_id;
486e88f27b3Smrg	__s32 x;
487e88f27b3Smrg	__s32 y;
488e88f27b3Smrg	__u32 width;
489e88f27b3Smrg	__u32 height;
490e88f27b3Smrg	/* driver specific handle */
491e88f27b3Smrg	__u32 handle;
492e88f27b3Smrg	__s32 hot_x;
493e88f27b3Smrg	__s32 hot_y;
494e88f27b3Smrg};
495e88f27b3Smrg
49622944501Smrgstruct drm_mode_crtc_lut {
49722944501Smrg	__u32 crtc_id;
49822944501Smrg	__u32 gamma_size;
49922944501Smrg
50022944501Smrg	/* pointers to arrays */
50122944501Smrg	__u64 red;
50222944501Smrg	__u64 green;
50322944501Smrg	__u64 blue;
50422944501Smrg};
50522944501Smrg
5063f012e29Smrgstruct drm_color_ctm {
5073f012e29Smrg	/* Conversion matrix in S31.32 format. */
5083f012e29Smrg	__s64 matrix[9];
5093f012e29Smrg};
5103f012e29Smrg
5113f012e29Smrgstruct drm_color_lut {
5123f012e29Smrg	/*
5133f012e29Smrg	 * Data is U0.16 fixed point format.
5143f012e29Smrg	 */
5153f012e29Smrg	__u16 red;
5163f012e29Smrg	__u16 green;
5173f012e29Smrg	__u16 blue;
5183f012e29Smrg	__u16 reserved;
5193f012e29Smrg};
5203f012e29Smrg
52122944501Smrg#define DRM_MODE_PAGE_FLIP_EVENT 0x01
522e88f27b3Smrg#define DRM_MODE_PAGE_FLIP_ASYNC 0x02
523037b3c26Smrg#define DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4
524037b3c26Smrg#define DRM_MODE_PAGE_FLIP_TARGET_RELATIVE 0x8
525037b3c26Smrg#define DRM_MODE_PAGE_FLIP_TARGET (DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE | \
526037b3c26Smrg				   DRM_MODE_PAGE_FLIP_TARGET_RELATIVE)
527037b3c26Smrg#define DRM_MODE_PAGE_FLIP_FLAGS (DRM_MODE_PAGE_FLIP_EVENT | \
528037b3c26Smrg				  DRM_MODE_PAGE_FLIP_ASYNC | \
529037b3c26Smrg				  DRM_MODE_PAGE_FLIP_TARGET)
53022944501Smrg
53113d1d17dSmrg/*
53213d1d17dSmrg * Request a page flip on the specified crtc.
53313d1d17dSmrg *
53413d1d17dSmrg * This ioctl will ask KMS to schedule a page flip for the specified
53513d1d17dSmrg * crtc.  Once any pending rendering targeting the specified fb (as of
53613d1d17dSmrg * ioctl time) has completed, the crtc will be reprogrammed to display
53713d1d17dSmrg * that fb after the next vertical refresh.  The ioctl returns
53813d1d17dSmrg * immediately, but subsequent rendering to the current fb will block
53913d1d17dSmrg * in the execbuffer ioctl until the page flip happens.  If a page
54013d1d17dSmrg * flip is already pending as the ioctl is called, EBUSY will be
54113d1d17dSmrg * returned.
54213d1d17dSmrg *
5433f012e29Smrg * Flag DRM_MODE_PAGE_FLIP_EVENT requests that drm sends back a vblank
5443f012e29Smrg * event (see drm.h: struct drm_event_vblank) when the page flip is
5453f012e29Smrg * done.  The user_data field passed in with this ioctl will be
5463f012e29Smrg * returned as the user_data field in the vblank event struct.
5473f012e29Smrg *
5483f012e29Smrg * Flag DRM_MODE_PAGE_FLIP_ASYNC requests that the flip happen
5493f012e29Smrg * 'as soon as possible', meaning that it not delay waiting for vblank.
5503f012e29Smrg * This may cause tearing on the screen.
55113d1d17dSmrg *
552037b3c26Smrg * The reserved field must be zero.
55313d1d17dSmrg */
55413d1d17dSmrg
55522944501Smrgstruct drm_mode_crtc_page_flip {
55613d1d17dSmrg	__u32 crtc_id;
55713d1d17dSmrg	__u32 fb_id;
55813d1d17dSmrg	__u32 flags;
55913d1d17dSmrg	__u32 reserved;
56013d1d17dSmrg	__u64 user_data;
56122944501Smrg};
56222944501Smrg
563037b3c26Smrg/*
564037b3c26Smrg * Request a page flip on the specified crtc.
565037b3c26Smrg *
566037b3c26Smrg * Same as struct drm_mode_crtc_page_flip, but supports new flags and
567037b3c26Smrg * re-purposes the reserved field:
568037b3c26Smrg *
569037b3c26Smrg * The sequence field must be zero unless either of the
570037b3c26Smrg * DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE/RELATIVE flags is specified. When
571037b3c26Smrg * the ABSOLUTE flag is specified, the sequence field denotes the absolute
572037b3c26Smrg * vblank sequence when the flip should take effect. When the RELATIVE
573037b3c26Smrg * flag is specified, the sequence field denotes the relative (to the
574037b3c26Smrg * current one when the ioctl is called) vblank sequence when the flip
575037b3c26Smrg * should take effect. NOTE: DRM_IOCTL_WAIT_VBLANK must still be used to
576037b3c26Smrg * make sure the vblank sequence before the target one has passed before
577037b3c26Smrg * calling this ioctl. The purpose of the
578037b3c26Smrg * DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE/RELATIVE flags is merely to clarify
579037b3c26Smrg * the target for when code dealing with a page flip runs during a
580037b3c26Smrg * vertical blank period.
581037b3c26Smrg */
582037b3c26Smrg
583037b3c26Smrgstruct drm_mode_crtc_page_flip_target {
584037b3c26Smrg	__u32 crtc_id;
585037b3c26Smrg	__u32 fb_id;
586037b3c26Smrg	__u32 flags;
587037b3c26Smrg	__u32 sequence;
588037b3c26Smrg	__u64 user_data;
589037b3c26Smrg};
590037b3c26Smrg
591e88f27b3Smrg/* create a dumb scanout buffer */
592e88f27b3Smrgstruct drm_mode_create_dumb {
5933f012e29Smrg	__u32 height;
5943f012e29Smrg	__u32 width;
5953f012e29Smrg	__u32 bpp;
5963f012e29Smrg	__u32 flags;
5973f012e29Smrg	/* handle, pitch, size will be returned */
5983f012e29Smrg	__u32 handle;
5993f012e29Smrg	__u32 pitch;
6003f012e29Smrg	__u64 size;
601e88f27b3Smrg};
602e88f27b3Smrg
603e88f27b3Smrg/* set up for mmap of a dumb scanout buffer */
604e88f27b3Smrgstruct drm_mode_map_dumb {
6053f012e29Smrg	/** Handle for the object being mapped. */
6063f012e29Smrg	__u32 handle;
6073f012e29Smrg	__u32 pad;
6083f012e29Smrg	/**
6093f012e29Smrg	 * Fake offset to use for subsequent mmap call
6103f012e29Smrg	 *
6113f012e29Smrg	 * This is a fixed-size type for 32/64 compatibility.
6123f012e29Smrg	 */
6133f012e29Smrg	__u64 offset;
614e88f27b3Smrg};
615e88f27b3Smrg
616e88f27b3Smrgstruct drm_mode_destroy_dumb {
617e88f27b3Smrg	__u32 handle;
618e88f27b3Smrg};
619e88f27b3Smrg
620e6188e58Smrg/* page-flip flags are valid, plus: */
6213f012e29Smrg#define DRM_MODE_ATOMIC_TEST_ONLY 0x0100
6223f012e29Smrg#define DRM_MODE_ATOMIC_NONBLOCK  0x0200
6233f012e29Smrg#define DRM_MODE_ATOMIC_ALLOW_MODESET 0x0400
6243f012e29Smrg
6253f012e29Smrg#define DRM_MODE_ATOMIC_FLAGS (\
6263f012e29Smrg		DRM_MODE_PAGE_FLIP_EVENT |\
6273f012e29Smrg		DRM_MODE_PAGE_FLIP_ASYNC |\
6283f012e29Smrg		DRM_MODE_ATOMIC_TEST_ONLY |\
6293f012e29Smrg		DRM_MODE_ATOMIC_NONBLOCK |\
6303f012e29Smrg		DRM_MODE_ATOMIC_ALLOW_MODESET)
631e6188e58Smrg
632e6188e58Smrgstruct drm_mode_atomic {
633e6188e58Smrg	__u32 flags;
634e6188e58Smrg	__u32 count_objs;
635e6188e58Smrg	__u64 objs_ptr;
636e6188e58Smrg	__u64 count_props_ptr;
637e6188e58Smrg	__u64 props_ptr;
638e6188e58Smrg	__u64 prop_values_ptr;
639e6188e58Smrg	__u64 reserved;
640e6188e58Smrg	__u64 user_data;
641e6188e58Smrg};
642e6188e58Smrg
643e6188e58Smrg/**
644e6188e58Smrg * Create a new 'blob' data property, copying length bytes from data pointer,
645e6188e58Smrg * and returning new blob ID.
646e6188e58Smrg */
647e6188e58Smrgstruct drm_mode_create_blob {
648e6188e58Smrg	/** Pointer to data to copy. */
649e6188e58Smrg	__u64 data;
650e6188e58Smrg	/** Length of data to copy. */
651e6188e58Smrg	__u32 length;
652e6188e58Smrg	/** Return: new property ID. */
653e6188e58Smrg	__u32 blob_id;
654e6188e58Smrg};
655e6188e58Smrg
656e6188e58Smrg/**
657e6188e58Smrg * Destroy a user-created blob property.
658e6188e58Smrg */
659e6188e58Smrgstruct drm_mode_destroy_blob {
660e6188e58Smrg	__u32 blob_id;
661e6188e58Smrg};
662e6188e58Smrg
663037b3c26Smrg#if defined(__cplusplus)
664037b3c26Smrg}
665037b3c26Smrg#endif
666037b3c26Smrg
66722944501Smrg#endif
668