radeon_kms.c revision 1090d90a
1/* 2 * Copyright © 2009 Red Hat, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Dave Airlie <airlied@redhat.com> 25 * 26 */ 27#ifdef HAVE_CONFIG_H 28#include "config.h" 29#endif 30 31#include <errno.h> 32#include <sys/ioctl.h> 33/* Driver data structures */ 34#include "radeon.h" 35#include "radeon_drm_queue.h" 36#include "radeon_glamor.h" 37#include "radeon_reg.h" 38#include "radeon_probe.h" 39#include "micmap.h" 40 41#include "radeon_version.h" 42#include "shadow.h" 43#include <xf86Priv.h> 44 45#include "atipciids.h" 46 47/* DPMS */ 48#ifdef HAVE_XEXTPROTO_71 49#include <X11/extensions/dpmsconst.h> 50#else 51#define DPMS_SERVER 52#include <X11/extensions/dpms.h> 53#endif 54 55#include <X11/extensions/damageproto.h> 56 57#include "radeon_chipinfo_gen.h" 58 59#include "radeon_bo_gem.h" 60#include "radeon_cs_gem.h" 61#include "radeon_vbo.h" 62 63static DevScreenPrivateKeyRec radeon_client_private_key; 64 65extern SymTabRec RADEONChipsets[]; 66static Bool radeon_setup_kernel_mem(ScreenPtr pScreen); 67 68const OptionInfoRec RADEONOptions_KMS[] = { 69 { OPTION_ACCEL, "Accel", OPTV_BOOLEAN, {0}, FALSE }, 70 { OPTION_SW_CURSOR, "SWcursor", OPTV_BOOLEAN, {0}, FALSE }, 71 { OPTION_PAGE_FLIP, "EnablePageFlip", OPTV_BOOLEAN, {0}, FALSE }, 72 { OPTION_COLOR_TILING, "ColorTiling", OPTV_BOOLEAN, {0}, FALSE }, 73 { OPTION_COLOR_TILING_2D,"ColorTiling2D", OPTV_BOOLEAN, {0}, FALSE }, 74 { OPTION_RENDER_ACCEL, "RenderAccel", OPTV_BOOLEAN, {0}, FALSE }, 75 { OPTION_SUBPIXEL_ORDER, "SubPixelOrder", OPTV_ANYSTR, {0}, FALSE }, 76#ifdef USE_GLAMOR 77 { OPTION_ACCELMETHOD, "AccelMethod", OPTV_STRING, {0}, FALSE }, 78 { OPTION_SHADOW_PRIMARY, "ShadowPrimary", OPTV_BOOLEAN, {0}, FALSE }, 79#endif 80 { OPTION_EXA_VSYNC, "EXAVSync", OPTV_BOOLEAN, {0}, FALSE }, 81 { OPTION_EXA_PIXMAPS, "EXAPixmaps", OPTV_BOOLEAN, {0}, FALSE }, 82 { OPTION_ZAPHOD_HEADS, "ZaphodHeads", OPTV_STRING, {0}, FALSE }, 83 { OPTION_SWAPBUFFERS_WAIT,"SwapbuffersWait", OPTV_BOOLEAN, {0}, FALSE }, 84 { OPTION_DELETE_DP12, "DeleteUnusedDP12Displays", OPTV_BOOLEAN, {0}, FALSE}, 85 { OPTION_DRI3, "DRI3", OPTV_BOOLEAN, {0}, FALSE }, 86 { OPTION_DRI, "DRI", OPTV_INTEGER, {0}, FALSE }, 87 { OPTION_TEAR_FREE, "TearFree", OPTV_BOOLEAN, {0}, FALSE }, 88 { -1, NULL, OPTV_NONE, {0}, FALSE } 89}; 90 91const OptionInfoRec *RADEONOptionsWeak(void) { return RADEONOptions_KMS; } 92 93void radeon_cs_flush_indirect(ScrnInfoPtr pScrn) 94{ 95 RADEONInfoPtr info = RADEONPTR(pScrn); 96 struct radeon_accel_state *accel_state; 97 int ret; 98 99 info->gpu_flushed++; 100 101#ifdef USE_GLAMOR 102 if (info->use_glamor) { 103 glamor_block_handler(pScrn->pScreen); 104 return; 105 } 106#endif 107 108 if (!info->cs->cdw) 109 return; 110 111 accel_state = info->accel_state; 112 113 /* release the current VBO so we don't block on mapping it later */ 114 if (info->accel_state->vbo.vb_offset && info->accel_state->vbo.vb_bo) { 115 radeon_vbo_put(pScrn, &info->accel_state->vbo); 116 info->accel_state->vbo.vb_start_op = -1; 117 } 118 119 /* release the current VBO so we don't block on mapping it later */ 120 if (info->accel_state->cbuf.vb_bo) { 121 radeon_vbo_put(pScrn, &info->accel_state->cbuf); 122 info->accel_state->cbuf.vb_start_op = -1; 123 } 124 125 radeon_cs_emit(info->cs); 126 radeon_cs_erase(info->cs); 127 128 if (accel_state->use_vbos) 129 radeon_vbo_flush_bos(pScrn); 130 131 ret = radeon_cs_space_check_with_bo(info->cs, 132 accel_state->vbo.vb_bo, 133 RADEON_GEM_DOMAIN_GTT, 0); 134 if (ret) 135 ErrorF("space check failed in flush\n"); 136 137 if (info->reemit_current2d && info->state_2d.op) 138 info->reemit_current2d(pScrn, info->state_2d.op); 139 140 if (info->dri2.enabled) { 141 info->accel_state->XInited3D = FALSE; 142 info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN; 143 } 144 145} 146 147void radeon_ddx_cs_start(ScrnInfoPtr pScrn, 148 int n, const char *file, 149 const char *func, int line) 150{ 151 RADEONInfoPtr info = RADEONPTR(pScrn); 152 153 if (info->cs->cdw + n > info->cs->ndw) { 154 radeon_cs_flush_indirect(pScrn); 155 156 } 157 radeon_cs_begin(info->cs, n, file, func, line); 158} 159 160 161extern _X_EXPORT int gRADEONEntityIndex; 162 163static int getRADEONEntityIndex(void) 164{ 165 return gRADEONEntityIndex; 166} 167 168 169RADEONEntPtr RADEONEntPriv(ScrnInfoPtr pScrn) 170{ 171 DevUnion *pPriv; 172 RADEONInfoPtr info = RADEONPTR(pScrn); 173 pPriv = xf86GetEntityPrivate(info->pEnt->index, 174 getRADEONEntityIndex()); 175 return pPriv->ptr; 176} 177 178/* Allocate our private RADEONInfoRec */ 179static Bool RADEONGetRec(ScrnInfoPtr pScrn) 180{ 181 if (pScrn->driverPrivate) return TRUE; 182 183 pScrn->driverPrivate = xnfcalloc(sizeof(RADEONInfoRec), 1); 184 return TRUE; 185} 186 187/* Free our private RADEONInfoRec */ 188static void RADEONFreeRec(ScrnInfoPtr pScrn) 189{ 190 RADEONInfoPtr info; 191 192 if (!pScrn || !pScrn->driverPrivate) return; 193 194 info = RADEONPTR(pScrn); 195 196 if (info->fbcon_pixmap) 197 pScrn->pScreen->DestroyPixmap(info->fbcon_pixmap); 198 199 if (info->dri2.drm_fd > 0) { 200 DevUnion *pPriv; 201 RADEONEntPtr pRADEONEnt; 202 pPriv = xf86GetEntityPrivate(pScrn->entityList[0], 203 getRADEONEntityIndex()); 204 205 pRADEONEnt = pPriv->ptr; 206 pRADEONEnt->fd_ref--; 207 if (!pRADEONEnt->fd_ref) { 208#ifdef XF86_PDEV_SERVER_FD 209 if (!(pRADEONEnt->platform_dev && 210 pRADEONEnt->platform_dev->flags & XF86_PDEV_SERVER_FD)) 211#endif 212 drmClose(pRADEONEnt->fd); 213 pRADEONEnt->fd = 0; 214 } 215 } 216 217 if (info->accel_state) { 218 free(info->accel_state); 219 info->accel_state = NULL; 220 } 221 222 free(pScrn->driverPrivate); 223 pScrn->driverPrivate = NULL; 224} 225 226static void * 227radeonShadowWindow(ScreenPtr screen, CARD32 row, CARD32 offset, int mode, 228 CARD32 *size, void *closure) 229{ 230 ScrnInfoPtr pScrn = xf86ScreenToScrn(screen); 231 RADEONInfoPtr info = RADEONPTR(pScrn); 232 int stride; 233 234 stride = (pScrn->displayWidth * pScrn->bitsPerPixel) / 8; 235 *size = stride; 236 237 return ((uint8_t *)info->front_bo->ptr + row * stride + offset); 238} 239 240static void 241radeonUpdatePacked(ScreenPtr pScreen, shadowBufPtr pBuf) 242{ 243 shadowUpdatePacked(pScreen, pBuf); 244} 245 246static Bool 247callback_needs_flush(RADEONInfoPtr info, struct radeon_client_priv *client_priv) 248{ 249 return (int)(client_priv->needs_flush - info->gpu_flushed) > 0; 250} 251 252static void 253radeon_event_callback(CallbackListPtr *list, 254 pointer user_data, pointer call_data) 255{ 256 EventInfoRec *eventinfo = call_data; 257 ScrnInfoPtr pScrn = user_data; 258 ScreenPtr pScreen = pScrn->pScreen; 259 struct radeon_client_priv *client_priv = 260 dixLookupScreenPrivate(&eventinfo->client->devPrivates, 261 &radeon_client_private_key, pScreen); 262 struct radeon_client_priv *server_priv = 263 dixLookupScreenPrivate(&serverClient->devPrivates, 264 &radeon_client_private_key, pScreen); 265 RADEONInfoPtr info = RADEONPTR(pScrn); 266 int i; 267 268 if (callback_needs_flush(info, client_priv) || 269 callback_needs_flush(info, server_priv)) 270 return; 271 272 /* Don't let gpu_flushed get too far ahead of needs_flush, in order 273 * to prevent false positives in callback_needs_flush() 274 */ 275 client_priv->needs_flush = info->gpu_flushed; 276 server_priv->needs_flush = info->gpu_flushed; 277 278 for (i = 0; i < eventinfo->count; i++) { 279 if (eventinfo->events[i].u.u.type == info->callback_event_type) { 280 client_priv->needs_flush++; 281 server_priv->needs_flush++; 282 return; 283 } 284 } 285} 286 287static void 288radeon_flush_callback(CallbackListPtr *list, 289 pointer user_data, pointer call_data) 290{ 291 ScrnInfoPtr pScrn = user_data; 292 ScreenPtr pScreen = pScrn->pScreen; 293 ClientPtr client = call_data ? call_data : serverClient; 294 struct radeon_client_priv *client_priv = 295 dixLookupScreenPrivate(&client->devPrivates, 296 &radeon_client_private_key, pScreen); 297 RADEONInfoPtr info = RADEONPTR(pScrn); 298 299 if (pScrn->vtSema && callback_needs_flush(info, client_priv)) 300 radeon_cs_flush_indirect(pScrn); 301} 302 303static Bool RADEONCreateScreenResources_KMS(ScreenPtr pScreen) 304{ 305 ExtensionEntry *damage_ext; 306 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); 307 RADEONInfoPtr info = RADEONPTR(pScrn); 308 PixmapPtr pixmap; 309 struct radeon_surface *surface; 310 311 pScreen->CreateScreenResources = info->CreateScreenResources; 312 if (!(*pScreen->CreateScreenResources)(pScreen)) 313 return FALSE; 314 pScreen->CreateScreenResources = RADEONCreateScreenResources_KMS; 315 316 /* Set the RandR primary output if Xorg hasn't */ 317 if (dixPrivateKeyRegistered(rrPrivKey)) { 318 rrScrPrivPtr rrScrPriv = rrGetScrPriv(pScreen); 319 320 if (!radeon_is_gpu_screen(pScreen) && 321 !rrScrPriv->primaryOutput) 322 { 323 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 324 325 rrScrPriv->primaryOutput = xf86_config->output[0]->randr_output; 326 RROutputChanged(rrScrPriv->primaryOutput, FALSE); 327 rrScrPriv->layoutChanged = TRUE; 328 } 329 } 330 331 if (!drmmode_set_desired_modes(pScrn, &info->drmmode, 332 radeon_is_gpu_screen(pScreen))) 333 return FALSE; 334 335 drmmode_uevent_init(pScrn, &info->drmmode); 336 337 if (info->r600_shadow_fb) { 338 pixmap = pScreen->GetScreenPixmap(pScreen); 339 340 if (!shadowAdd(pScreen, pixmap, radeonUpdatePacked, 341 radeonShadowWindow, 0, NULL)) 342 return FALSE; 343 } 344 345 if (info->dri2.enabled || info->use_glamor) { 346 if (info->front_bo) { 347 PixmapPtr pPix = pScreen->GetScreenPixmap(pScreen); 348 if (!radeon_set_pixmap_bo(pPix, info->front_bo)) 349 return FALSE; 350 surface = radeon_get_pixmap_surface(pPix); 351 if (surface) { 352 *surface = info->front_surface; 353 } 354 } 355 } 356 357 if (info->use_glamor) 358 radeon_glamor_create_screen_resources(pScreen); 359 360 info->callback_event_type = -1; 361 if (!radeon_is_gpu_screen(pScreen) && 362 (damage_ext = CheckExtension("DAMAGE"))) { 363 info->callback_event_type = damage_ext->eventBase + XDamageNotify; 364 365 if (!AddCallback(&FlushCallback, radeon_flush_callback, pScrn)) 366 return FALSE; 367 368 if (!AddCallback(&EventCallback, radeon_event_callback, pScrn)) { 369 DeleteCallback(&FlushCallback, radeon_flush_callback, pScrn); 370 return FALSE; 371 } 372 373 if (!dixRegisterScreenPrivateKey(&radeon_client_private_key, pScreen, 374 PRIVATE_CLIENT, sizeof(struct radeon_client_priv))) { 375 DeleteCallback(&FlushCallback, radeon_flush_callback, pScrn); 376 DeleteCallback(&EventCallback, radeon_event_callback, pScrn); 377 return FALSE; 378 } 379 } 380 381 return TRUE; 382} 383 384static Bool 385radeon_scanout_extents_intersect(xf86CrtcPtr xf86_crtc, BoxPtr extents) 386{ 387#ifdef RADEON_PIXMAP_SHARING 388 if (xf86_crtc->scrn->is_gpu) { 389 extents->x1 -= xf86_crtc->x; 390 extents->y1 -= xf86_crtc->y; 391 extents->x2 -= xf86_crtc->x; 392 extents->y2 -= xf86_crtc->y; 393 } else 394#endif 395 { 396 extents->x1 -= xf86_crtc->filter_width >> 1; 397 extents->x2 += xf86_crtc->filter_width >> 1; 398 extents->y1 -= xf86_crtc->filter_height >> 1; 399 extents->y2 += xf86_crtc->filter_height >> 1; 400 pixman_f_transform_bounds(&xf86_crtc->f_framebuffer_to_crtc, extents); 401 } 402 403 extents->x1 = max(extents->x1, 0); 404 extents->y1 = max(extents->y1, 0); 405 extents->x2 = min(extents->x2, xf86_crtc->mode.HDisplay); 406 extents->y2 = min(extents->y2, xf86_crtc->mode.VDisplay); 407 408 return (extents->x1 < extents->x2 && extents->y1 < extents->y2); 409} 410 411#if XF86_CRTC_VERSION >= 4 412 413static RegionPtr 414transform_region(RegionPtr region, struct pict_f_transform *transform, 415 int w, int h) 416{ 417 BoxPtr boxes = RegionRects(region); 418 int nboxes = RegionNumRects(region); 419 xRectanglePtr rects = malloc(nboxes * sizeof(*rects)); 420 RegionPtr transformed; 421 int nrects = 0; 422 BoxRec box; 423 int i; 424 425 for (i = 0; i < nboxes; i++) { 426 box.x1 = boxes[i].x1; 427 box.x2 = boxes[i].x2; 428 box.y1 = boxes[i].y1; 429 box.y2 = boxes[i].y2; 430 pixman_f_transform_bounds(transform, &box); 431 432 box.x1 = max(box.x1, 0); 433 box.y1 = max(box.y1, 0); 434 box.x2 = min(box.x2, w); 435 box.y2 = min(box.y2, h); 436 if (box.x1 >= box.x2 || box.y1 >= box.y2) 437 continue; 438 439 rects[nrects].x = box.x1; 440 rects[nrects].y = box.y1; 441 rects[nrects].width = box.x2 - box.x1; 442 rects[nrects].height = box.y2 - box.y1; 443 nrects++; 444 } 445 446 transformed = RegionFromRects(nrects, rects, CT_UNSORTED); 447 free(rects); 448 return transformed; 449} 450 451#endif 452 453static void 454radeon_sync_scanout_pixmaps(xf86CrtcPtr xf86_crtc, RegionPtr new_region, 455 int scanout_id) 456{ 457 drmmode_crtc_private_ptr drmmode_crtc = xf86_crtc->driver_private; 458 DrawablePtr dst = &drmmode_crtc->scanout[scanout_id].pixmap->drawable; 459 DrawablePtr src = &drmmode_crtc->scanout[scanout_id ^ 1].pixmap->drawable; 460 RegionPtr last_region = &drmmode_crtc->scanout_last_region; 461 ScrnInfoPtr scrn = xf86_crtc->scrn; 462 ScreenPtr pScreen = scrn->pScreen; 463 RADEONInfoPtr info = RADEONPTR(scrn); 464 RegionRec remaining; 465 RegionPtr sync_region = NULL; 466 BoxRec extents; 467 Bool force; 468 GCPtr gc; 469 470 if (RegionNil(last_region)) 471 return; 472 473 RegionNull(&remaining); 474 RegionSubtract(&remaining, last_region, new_region); 475 if (RegionNil(&remaining)) 476 goto uninit; 477 478 extents = *RegionExtents(&remaining); 479 if (!radeon_scanout_extents_intersect(xf86_crtc, &extents)) 480 goto uninit; 481 482#if XF86_CRTC_VERSION >= 4 483 if (xf86_crtc->driverIsPerformingTransform) { 484 sync_region = transform_region(&remaining, 485 &xf86_crtc->f_framebuffer_to_crtc, 486 dst->width, dst->height); 487 } else 488#endif /* XF86_CRTC_VERSION >= 4 */ 489 { 490 sync_region = RegionDuplicate(&remaining); 491 RegionTranslate(sync_region, -xf86_crtc->x, -xf86_crtc->y); 492 } 493 494 force = info->accel_state->force; 495 info->accel_state->force = TRUE; 496 497 gc = GetScratchGC(dst->depth, pScreen); 498 if (gc) { 499 gc->funcs->ChangeClip(gc, CT_REGION, sync_region, 0); 500 ValidateGC(dst, gc); 501 sync_region = NULL; 502 gc->ops->CopyArea(src, dst, gc, 0, 0, dst->width, dst->height, 0, 0); 503 FreeScratchGC(gc); 504 } 505 506 info->accel_state->force = force; 507 508 uninit: 509 if (sync_region) 510 RegionDestroy(sync_region); 511 RegionUninit(&remaining); 512} 513 514#ifdef RADEON_PIXMAP_SHARING 515 516static RegionPtr 517dirty_region(PixmapDirtyUpdatePtr dirty) 518{ 519 RegionPtr damageregion = DamageRegion(dirty->damage); 520 RegionPtr dstregion; 521 522#ifdef HAS_DIRTYTRACKING_ROTATION 523 if (dirty->rotation != RR_Rotate_0) { 524 dstregion = transform_region(damageregion, 525 &dirty->f_inverse, 526 dirty->slave_dst->drawable.width, 527 dirty->slave_dst->drawable.height); 528 } else 529#endif 530 { 531 RegionRec pixregion; 532 533 dstregion = RegionDuplicate(damageregion); 534 RegionTranslate(dstregion, -dirty->x, -dirty->y); 535 PixmapRegionInit(&pixregion, dirty->slave_dst); 536 RegionIntersect(dstregion, dstregion, &pixregion); 537 RegionUninit(&pixregion); 538 } 539 540 return dstregion; 541} 542 543static void 544redisplay_dirty(PixmapDirtyUpdatePtr dirty, RegionPtr region) 545{ 546 ScrnInfoPtr pScrn = xf86ScreenToScrn(dirty->src->drawable.pScreen); 547 548 if (RegionNil(region)) 549 goto out; 550 551 if (dirty->slave_dst->master_pixmap) 552 DamageRegionAppend(&dirty->slave_dst->drawable, region); 553 554#ifdef HAS_DIRTYTRACKING_ROTATION 555 PixmapSyncDirtyHelper(dirty); 556#else 557 PixmapSyncDirtyHelper(dirty, region); 558#endif 559 560 radeon_cs_flush_indirect(pScrn); 561 if (dirty->slave_dst->master_pixmap) 562 DamageRegionProcessPending(&dirty->slave_dst->drawable); 563 564out: 565 DamageEmpty(dirty->damage); 566} 567 568static void 569radeon_prime_scanout_update_abort(xf86CrtcPtr crtc, void *event_data) 570{ 571 drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; 572 573 drmmode_crtc->scanout_update_pending = FALSE; 574} 575 576void 577radeon_sync_shared_pixmap(PixmapDirtyUpdatePtr dirty) 578{ 579 ScreenPtr master_screen = dirty->src->master_pixmap->drawable.pScreen; 580 PixmapDirtyUpdatePtr ent; 581 RegionPtr region; 582 583 xorg_list_for_each_entry(ent, &master_screen->pixmap_dirty_list, ent) { 584 if (ent->slave_dst != dirty->src) 585 continue; 586 587 region = dirty_region(ent); 588 redisplay_dirty(ent, region); 589 RegionDestroy(region); 590 } 591} 592 593 594#if HAS_SYNC_SHARED_PIXMAP 595 596static Bool 597master_has_sync_shared_pixmap(ScrnInfoPtr scrn, PixmapDirtyUpdatePtr dirty) 598{ 599 ScreenPtr master_screen = dirty->src->master_pixmap->drawable.pScreen; 600 601 return master_screen->SyncSharedPixmap != NULL; 602} 603 604static Bool 605slave_has_sync_shared_pixmap(ScrnInfoPtr scrn, PixmapDirtyUpdatePtr dirty) 606{ 607 ScreenPtr slave_screen = dirty->slave_dst->drawable.pScreen; 608 609 return slave_screen->SyncSharedPixmap != NULL; 610} 611 612static void 613call_sync_shared_pixmap(PixmapDirtyUpdatePtr dirty) 614{ 615 ScreenPtr master_screen = dirty->src->master_pixmap->drawable.pScreen; 616 617 master_screen->SyncSharedPixmap(dirty); 618} 619 620#else /* !HAS_SYNC_SHARED_PIXMAP */ 621 622static Bool 623master_has_sync_shared_pixmap(ScrnInfoPtr scrn, PixmapDirtyUpdatePtr dirty) 624{ 625 ScrnInfoPtr master_scrn = xf86ScreenToScrn(dirty->src->master_pixmap->drawable.pScreen); 626 627 return master_scrn->driverName == scrn->driverName; 628} 629 630static Bool 631slave_has_sync_shared_pixmap(ScrnInfoPtr scrn, PixmapDirtyUpdatePtr dirty) 632{ 633 ScrnInfoPtr slave_scrn = xf86ScreenToScrn(dirty->slave_dst->drawable.pScreen); 634 635 return slave_scrn->driverName == scrn->driverName; 636} 637 638static void 639call_sync_shared_pixmap(PixmapDirtyUpdatePtr dirty) 640{ 641 radeon_sync_shared_pixmap(dirty); 642} 643 644#endif /* HAS_SYNC_SHARED_PIXMAPS */ 645 646 647static xf86CrtcPtr 648radeon_prime_dirty_to_crtc(PixmapDirtyUpdatePtr dirty) 649{ 650 ScreenPtr screen = dirty->slave_dst->drawable.pScreen; 651 ScrnInfoPtr scrn = xf86ScreenToScrn(screen); 652 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(scrn); 653 int c; 654 655 /* Find the CRTC which is scanning out from this slave pixmap */ 656 for (c = 0; c < xf86_config->num_crtc; c++) { 657 xf86CrtcPtr xf86_crtc = xf86_config->crtc[c]; 658 drmmode_crtc_private_ptr drmmode_crtc = xf86_crtc->driver_private; 659 660 if (drmmode_crtc->scanout[0].pixmap == dirty->slave_dst || 661 drmmode_crtc->scanout[1].pixmap == dirty->slave_dst) 662 return xf86_crtc; 663 } 664 665 return NULL; 666} 667 668static Bool 669radeon_prime_scanout_do_update(xf86CrtcPtr crtc, unsigned scanout_id) 670{ 671 ScrnInfoPtr scrn = crtc->scrn; 672 ScreenPtr screen = scrn->pScreen; 673 drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; 674 PixmapPtr scanoutpix = crtc->randr_crtc->scanout_pixmap; 675 PixmapDirtyUpdatePtr dirty; 676 Bool ret = FALSE; 677 678 xorg_list_for_each_entry(dirty, &screen->pixmap_dirty_list, ent) { 679 if (dirty->src == scanoutpix && dirty->slave_dst == 680 drmmode_crtc->scanout[scanout_id ^ drmmode_crtc->tear_free].pixmap) { 681 RegionPtr region; 682 683 if (master_has_sync_shared_pixmap(scrn, dirty)) 684 call_sync_shared_pixmap(dirty); 685 686 region = dirty_region(dirty); 687 if (RegionNil(region)) 688 goto destroy; 689 690 if (drmmode_crtc->tear_free) { 691 RegionTranslate(region, crtc->x, crtc->y); 692 radeon_sync_scanout_pixmaps(crtc, region, scanout_id); 693 radeon_cs_flush_indirect(scrn); 694 RegionCopy(&drmmode_crtc->scanout_last_region, region); 695 RegionTranslate(region, -crtc->x, -crtc->y); 696 dirty->slave_dst = drmmode_crtc->scanout[scanout_id].pixmap; 697 } 698 699 redisplay_dirty(dirty, region); 700 ret = TRUE; 701 destroy: 702 RegionDestroy(region); 703 break; 704 } 705 } 706 707 return ret; 708} 709 710static void 711radeon_prime_scanout_update_handler(xf86CrtcPtr crtc, uint32_t frame, uint64_t usec, 712 void *event_data) 713{ 714 drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; 715 716 radeon_prime_scanout_do_update(crtc, 0); 717 drmmode_crtc->scanout_update_pending = FALSE; 718} 719 720static void 721radeon_prime_scanout_update(PixmapDirtyUpdatePtr dirty) 722{ 723 ScreenPtr screen = dirty->slave_dst->drawable.pScreen; 724 ScrnInfoPtr scrn = xf86ScreenToScrn(screen); 725 xf86CrtcPtr xf86_crtc = radeon_prime_dirty_to_crtc(dirty); 726 drmmode_crtc_private_ptr drmmode_crtc; 727 uintptr_t drm_queue_seq; 728 drmVBlank vbl; 729 730 if (!xf86_crtc || !xf86_crtc->enabled) 731 return; 732 733 drmmode_crtc = xf86_crtc->driver_private; 734 if (drmmode_crtc->scanout_update_pending || 735 !drmmode_crtc->scanout[0].pixmap || 736 drmmode_crtc->pending_dpms_mode != DPMSModeOn) 737 return; 738 739 drm_queue_seq = radeon_drm_queue_alloc(xf86_crtc, 740 RADEON_DRM_QUEUE_CLIENT_DEFAULT, 741 RADEON_DRM_QUEUE_ID_DEFAULT, NULL, 742 radeon_prime_scanout_update_handler, 743 radeon_prime_scanout_update_abort); 744 if (drm_queue_seq == RADEON_DRM_QUEUE_ERROR) { 745 xf86DrvMsg(scrn->scrnIndex, X_WARNING, 746 "radeon_drm_queue_alloc failed for PRIME update\n"); 747 return; 748 } 749 750 vbl.request.type = DRM_VBLANK_RELATIVE | DRM_VBLANK_EVENT; 751 vbl.request.type |= radeon_populate_vbl_request_type(xf86_crtc); 752 vbl.request.sequence = 1; 753 vbl.request.signal = drm_queue_seq; 754 if (drmWaitVBlank(RADEONPTR(scrn)->dri2.drm_fd, &vbl)) { 755 xf86DrvMsg(scrn->scrnIndex, X_WARNING, 756 "drmWaitVBlank failed for PRIME update: %s\n", 757 strerror(errno)); 758 radeon_drm_abort_entry(drm_queue_seq); 759 return; 760 } 761 762 drmmode_crtc->scanout_update_pending = TRUE; 763} 764 765static void 766radeon_prime_scanout_flip_abort(xf86CrtcPtr crtc, void *event_data) 767{ 768 drmmode_crtc_private_ptr drmmode_crtc = event_data; 769 770 drmmode_crtc->scanout_update_pending = FALSE; 771 drmmode_clear_pending_flip(crtc); 772} 773 774static void 775radeon_prime_scanout_flip(PixmapDirtyUpdatePtr ent) 776{ 777 ScreenPtr screen = ent->slave_dst->drawable.pScreen; 778 ScrnInfoPtr scrn = xf86ScreenToScrn(screen); 779 RADEONEntPtr pRADEONEnt = RADEONEntPriv(scrn); 780 xf86CrtcPtr crtc = radeon_prime_dirty_to_crtc(ent); 781 drmmode_crtc_private_ptr drmmode_crtc; 782 uintptr_t drm_queue_seq; 783 unsigned scanout_id; 784 785 if (!crtc || !crtc->enabled) 786 return; 787 788 drmmode_crtc = crtc->driver_private; 789 if (drmmode_crtc->scanout_update_pending || 790 !drmmode_crtc->scanout[drmmode_crtc->scanout_id].pixmap || 791 drmmode_crtc->pending_dpms_mode != DPMSModeOn) 792 return; 793 794 scanout_id = drmmode_crtc->scanout_id ^ 1; 795 if (!radeon_prime_scanout_do_update(crtc, scanout_id)) 796 return; 797 798 drm_queue_seq = radeon_drm_queue_alloc(crtc, 799 RADEON_DRM_QUEUE_CLIENT_DEFAULT, 800 RADEON_DRM_QUEUE_ID_DEFAULT, 801 drmmode_crtc, NULL, 802 radeon_prime_scanout_flip_abort); 803 if (drm_queue_seq == RADEON_DRM_QUEUE_ERROR) { 804 xf86DrvMsg(scrn->scrnIndex, X_WARNING, 805 "Allocating DRM event queue entry failed for PRIME flip.\n"); 806 return; 807 } 808 809 if (drmmode_page_flip_target_relative(pRADEONEnt, drmmode_crtc, 810 drmmode_crtc->scanout[scanout_id].fb_id, 811 0, drm_queue_seq, 0) != 0) { 812 xf86DrvMsg(scrn->scrnIndex, X_WARNING, "flip queue failed in %s: %s\n", 813 __func__, strerror(errno)); 814 radeon_drm_abort_entry(drm_queue_seq); 815 return; 816 } 817 818 drmmode_crtc->scanout_id = scanout_id; 819 drmmode_crtc->scanout_update_pending = TRUE; 820 drmmode_crtc->flip_pending = TRUE; 821} 822 823static void 824radeon_dirty_update(ScrnInfoPtr scrn) 825{ 826 ScreenPtr screen = scrn->pScreen; 827 PixmapDirtyUpdatePtr ent; 828 RegionPtr region; 829 830 xorg_list_for_each_entry(ent, &screen->pixmap_dirty_list, ent) { 831 if (screen->isGPU) { 832 PixmapDirtyUpdatePtr region_ent = ent; 833 834 if (master_has_sync_shared_pixmap(scrn, ent)) { 835 ScreenPtr master_screen = ent->src->master_pixmap->drawable.pScreen; 836 837 xorg_list_for_each_entry(region_ent, &master_screen->pixmap_dirty_list, ent) { 838 if (region_ent->slave_dst == ent->src) 839 break; 840 } 841 } 842 843 region = dirty_region(region_ent); 844 845 if (RegionNotEmpty(region)) { 846 xf86CrtcPtr crtc = radeon_prime_dirty_to_crtc(ent); 847 drmmode_crtc_private_ptr drmmode_crtc = NULL; 848 849 if (crtc) 850 drmmode_crtc = crtc->driver_private; 851 852 if (drmmode_crtc && drmmode_crtc->tear_free) 853 radeon_prime_scanout_flip(ent); 854 else 855 radeon_prime_scanout_update(ent); 856 } else { 857 DamageEmpty(region_ent->damage); 858 } 859 860 RegionDestroy(region); 861 } else { 862 if (slave_has_sync_shared_pixmap(scrn, ent)) 863 continue; 864 865 region = dirty_region(ent); 866 redisplay_dirty(ent, region); 867 RegionDestroy(region); 868 } 869 } 870} 871#endif 872 873Bool 874radeon_scanout_do_update(xf86CrtcPtr xf86_crtc, int scanout_id) 875{ 876 drmmode_crtc_private_ptr drmmode_crtc = xf86_crtc->driver_private; 877 RegionPtr pRegion = DamageRegion(drmmode_crtc->scanout_damage); 878 ScrnInfoPtr scrn = xf86_crtc->scrn; 879 ScreenPtr pScreen = scrn->pScreen; 880 RADEONInfoPtr info = RADEONPTR(scrn); 881 DrawablePtr pDraw; 882 BoxRec extents; 883 Bool force; 884 885 if (!xf86_crtc->enabled || 886 !drmmode_crtc->scanout[scanout_id].pixmap) 887 return FALSE; 888 889 if (!RegionNotEmpty(pRegion)) 890 return FALSE; 891 892 pDraw = &drmmode_crtc->scanout[scanout_id].pixmap->drawable; 893 extents = *RegionExtents(pRegion); 894 if (!radeon_scanout_extents_intersect(xf86_crtc, &extents)) 895 return FALSE; 896 897 if (drmmode_crtc->tear_free) { 898 radeon_sync_scanout_pixmaps(xf86_crtc, pRegion, scanout_id); 899 RegionCopy(&drmmode_crtc->scanout_last_region, pRegion); 900 } 901 RegionEmpty(pRegion); 902 903 force = info->accel_state->force; 904 info->accel_state->force = TRUE; 905 906#if XF86_CRTC_VERSION >= 4 907 if (xf86_crtc->driverIsPerformingTransform) { 908 SourceValidateProcPtr SourceValidate = pScreen->SourceValidate; 909 PictFormatPtr format = PictureWindowFormat(pScreen->root); 910 int error; 911 PicturePtr src, dst; 912 XID include_inferiors = IncludeInferiors; 913 914 src = CreatePicture(None, 915 &pScreen->root->drawable, 916 format, 917 CPSubwindowMode, 918 &include_inferiors, serverClient, &error); 919 if (!src) { 920 ErrorF("Failed to create source picture for transformed scanout " 921 "update\n"); 922 goto out; 923 } 924 925 dst = CreatePicture(None, pDraw, format, 0L, NULL, serverClient, &error); 926 if (!dst) { 927 ErrorF("Failed to create destination picture for transformed scanout " 928 "update\n"); 929 goto free_src; 930 } 931 932 error = SetPictureTransform(src, &xf86_crtc->crtc_to_framebuffer); 933 if (error) { 934 ErrorF("SetPictureTransform failed for transformed scanout " 935 "update\n"); 936 goto free_dst; 937 } 938 939 if (xf86_crtc->filter) 940 SetPicturePictFilter(src, xf86_crtc->filter, xf86_crtc->params, 941 xf86_crtc->nparams); 942 943 pScreen->SourceValidate = NULL; 944 CompositePicture(PictOpSrc, 945 src, NULL, dst, 946 extents.x1, extents.y1, 0, 0, extents.x1, 947 extents.y1, extents.x2 - extents.x1, 948 extents.y2 - extents.y1); 949 pScreen->SourceValidate = SourceValidate; 950 951 free_dst: 952 FreePicture(dst, None); 953 free_src: 954 FreePicture(src, None); 955 } else 956 out: 957#endif /* XF86_CRTC_VERSION >= 4 */ 958 { 959 GCPtr gc = GetScratchGC(pDraw->depth, pScreen); 960 961 ValidateGC(pDraw, gc); 962 (*gc->ops->CopyArea)(&pScreen->GetScreenPixmap(pScreen)->drawable, 963 pDraw, gc, 964 xf86_crtc->x + extents.x1, xf86_crtc->y + extents.y1, 965 extents.x2 - extents.x1, extents.y2 - extents.y1, 966 extents.x1, extents.y1); 967 FreeScratchGC(gc); 968 } 969 970 radeon_cs_flush_indirect(scrn); 971 972 info->accel_state->force = force; 973 974 return TRUE; 975} 976 977static void 978radeon_scanout_update_abort(xf86CrtcPtr crtc, void *event_data) 979{ 980 drmmode_crtc_private_ptr drmmode_crtc = event_data; 981 982 drmmode_crtc->scanout_update_pending = FALSE; 983} 984 985static void 986radeon_scanout_update_handler(xf86CrtcPtr crtc, uint32_t frame, uint64_t usec, 987 void *event_data) 988{ 989 radeon_scanout_do_update(crtc, 0); 990 991 radeon_scanout_update_abort(crtc, event_data); 992} 993 994static void 995radeon_scanout_update(xf86CrtcPtr xf86_crtc) 996{ 997 drmmode_crtc_private_ptr drmmode_crtc = xf86_crtc->driver_private; 998 uintptr_t drm_queue_seq; 999 ScrnInfoPtr scrn; 1000 drmVBlank vbl; 1001 DamagePtr pDamage; 1002 RegionPtr pRegion; 1003 BoxRec extents; 1004 1005 if (!xf86_crtc->enabled || 1006 drmmode_crtc->scanout_update_pending || 1007 !drmmode_crtc->scanout[0].pixmap || 1008 drmmode_crtc->pending_dpms_mode != DPMSModeOn) 1009 return; 1010 1011 pDamage = drmmode_crtc->scanout_damage; 1012 if (!pDamage) 1013 return; 1014 1015 pRegion = DamageRegion(pDamage); 1016 if (!RegionNotEmpty(pRegion)) 1017 return; 1018 1019 extents = *RegionExtents(pRegion); 1020 if (!radeon_scanout_extents_intersect(xf86_crtc, &extents)) { 1021 RegionEmpty(pRegion); 1022 return; 1023 } 1024 1025 scrn = xf86_crtc->scrn; 1026 drm_queue_seq = radeon_drm_queue_alloc(xf86_crtc, 1027 RADEON_DRM_QUEUE_CLIENT_DEFAULT, 1028 RADEON_DRM_QUEUE_ID_DEFAULT, 1029 drmmode_crtc, 1030 radeon_scanout_update_handler, 1031 radeon_scanout_update_abort); 1032 if (drm_queue_seq == RADEON_DRM_QUEUE_ERROR) { 1033 xf86DrvMsg(scrn->scrnIndex, X_WARNING, 1034 "radeon_drm_queue_alloc failed for scanout update\n"); 1035 return; 1036 } 1037 1038 vbl.request.type = DRM_VBLANK_RELATIVE | DRM_VBLANK_EVENT; 1039 vbl.request.type |= radeon_populate_vbl_request_type(xf86_crtc); 1040 vbl.request.sequence = 1; 1041 vbl.request.signal = drm_queue_seq; 1042 if (drmWaitVBlank(RADEONPTR(scrn)->dri2.drm_fd, &vbl)) { 1043 xf86DrvMsg(scrn->scrnIndex, X_WARNING, 1044 "drmWaitVBlank failed for scanout update: %s\n", 1045 strerror(errno)); 1046 radeon_drm_abort_entry(drm_queue_seq); 1047 return; 1048 } 1049 1050 drmmode_crtc->scanout_update_pending = TRUE; 1051} 1052 1053static void 1054radeon_scanout_flip_abort(xf86CrtcPtr crtc, void *event_data) 1055{ 1056 drmmode_crtc_private_ptr drmmode_crtc = event_data; 1057 1058 drmmode_crtc->scanout_update_pending = FALSE; 1059 drmmode_clear_pending_flip(crtc); 1060} 1061 1062static void 1063radeon_scanout_flip(ScreenPtr pScreen, RADEONInfoPtr info, 1064 xf86CrtcPtr xf86_crtc) 1065{ 1066 drmmode_crtc_private_ptr drmmode_crtc = xf86_crtc->driver_private; 1067 ScrnInfoPtr scrn = xf86_crtc->scrn; 1068 RADEONEntPtr pRADEONEnt = RADEONEntPriv(scrn); 1069 uintptr_t drm_queue_seq; 1070 unsigned scanout_id; 1071 1072 if (drmmode_crtc->scanout_update_pending || 1073 drmmode_crtc->pending_dpms_mode != DPMSModeOn) 1074 return; 1075 1076 scanout_id = drmmode_crtc->scanout_id ^ 1; 1077 if (!radeon_scanout_do_update(xf86_crtc, scanout_id)) 1078 return; 1079 1080 drm_queue_seq = radeon_drm_queue_alloc(xf86_crtc, 1081 RADEON_DRM_QUEUE_CLIENT_DEFAULT, 1082 RADEON_DRM_QUEUE_ID_DEFAULT, 1083 drmmode_crtc, NULL, 1084 radeon_scanout_flip_abort); 1085 if (drm_queue_seq == RADEON_DRM_QUEUE_ERROR) { 1086 xf86DrvMsg(scrn->scrnIndex, X_WARNING, 1087 "Allocating DRM event queue entry failed.\n"); 1088 return; 1089 } 1090 1091 if (drmmode_page_flip_target_relative(pRADEONEnt, drmmode_crtc, 1092 drmmode_crtc->scanout[scanout_id].fb_id, 1093 0, drm_queue_seq, 0) != 0) { 1094 xf86DrvMsg(scrn->scrnIndex, X_WARNING, "flip queue failed in %s: %s\n", 1095 __func__, strerror(errno)); 1096 radeon_drm_abort_entry(drm_queue_seq); 1097 return; 1098 } 1099 1100 drmmode_crtc->scanout_id = scanout_id; 1101 drmmode_crtc->scanout_update_pending = TRUE; 1102 drmmode_crtc->flip_pending = TRUE; 1103} 1104 1105static void RADEONBlockHandler_KMS(BLOCKHANDLER_ARGS_DECL) 1106{ 1107 SCREEN_PTR(arg); 1108 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); 1109 RADEONInfoPtr info = RADEONPTR(pScrn); 1110 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 1111 int c; 1112 1113 pScreen->BlockHandler = info->BlockHandler; 1114 (*pScreen->BlockHandler) (BLOCKHANDLER_ARGS); 1115 pScreen->BlockHandler = RADEONBlockHandler_KMS; 1116 1117 if (!radeon_is_gpu_screen(pScreen)) 1118 { 1119 for (c = 0; c < xf86_config->num_crtc; c++) { 1120 xf86CrtcPtr crtc = xf86_config->crtc[c]; 1121 drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; 1122 1123 if (drmmode_crtc->tear_free) 1124 radeon_scanout_flip(pScreen, info, crtc); 1125 else if (info->shadow_primary 1126#if XF86_CRTC_VERSION >= 4 1127 || crtc->driverIsPerformingTransform 1128#endif 1129 ) 1130 radeon_scanout_update(crtc); 1131 } 1132 } 1133 1134 radeon_cs_flush_indirect(pScrn); 1135 1136#ifdef RADEON_PIXMAP_SHARING 1137 radeon_dirty_update(pScrn); 1138#endif 1139} 1140 1141static Bool RADEONIsFastFBWorking(ScrnInfoPtr pScrn) 1142{ 1143 RADEONInfoPtr info = RADEONPTR(pScrn); 1144 struct drm_radeon_info ginfo; 1145 int r; 1146 uint32_t tmp = 0; 1147 1148 memset(&ginfo, 0, sizeof(ginfo)); 1149 ginfo.request = RADEON_INFO_FASTFB_WORKING; 1150 ginfo.value = (uintptr_t)&tmp; 1151 r = drmCommandWriteRead(info->dri2.drm_fd, DRM_RADEON_INFO, &ginfo, sizeof(ginfo)); 1152 if (r) { 1153 return FALSE; 1154 } 1155 if (tmp == 1) 1156 return TRUE; 1157 return FALSE; 1158} 1159 1160static Bool RADEONIsFusionGARTWorking(ScrnInfoPtr pScrn) 1161{ 1162 RADEONInfoPtr info = RADEONPTR(pScrn); 1163 struct drm_radeon_info ginfo; 1164 int r; 1165 uint32_t tmp; 1166 1167 memset(&ginfo, 0, sizeof(ginfo)); 1168 ginfo.request = RADEON_INFO_FUSION_GART_WORKING; 1169 ginfo.value = (uintptr_t)&tmp; 1170 r = drmCommandWriteRead(info->dri2.drm_fd, DRM_RADEON_INFO, &ginfo, sizeof(ginfo)); 1171 if (r) { 1172 return FALSE; 1173 } 1174 if (tmp == 1) 1175 return TRUE; 1176 return FALSE; 1177} 1178 1179static Bool RADEONIsAccelWorking(ScrnInfoPtr pScrn) 1180{ 1181 RADEONInfoPtr info = RADEONPTR(pScrn); 1182 struct drm_radeon_info ginfo; 1183 int r; 1184 uint32_t tmp; 1185 1186 memset(&ginfo, 0, sizeof(ginfo)); 1187 if (info->dri2.pKernelDRMVersion->version_minor >= 5) 1188 ginfo.request = RADEON_INFO_ACCEL_WORKING2; 1189 else 1190 ginfo.request = RADEON_INFO_ACCEL_WORKING; 1191 ginfo.value = (uintptr_t)&tmp; 1192 r = drmCommandWriteRead(info->dri2.drm_fd, DRM_RADEON_INFO, &ginfo, sizeof(ginfo)); 1193 if (r) { 1194 /* If kernel is too old before 2.6.32 than assume accel is working */ 1195 if (r == -EINVAL) { 1196 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Kernel too old missing accel " 1197 "information, assuming accel is working\n"); 1198 return TRUE; 1199 } 1200 return FALSE; 1201 } 1202 if (info->ChipFamily == CHIP_FAMILY_HAWAII) { 1203 if (tmp == 2 || tmp == 3) 1204 return TRUE; 1205 } else if (tmp) { 1206 return TRUE; 1207 } 1208 return FALSE; 1209} 1210 1211/* This is called by RADEONPreInit to set up the default visual */ 1212static Bool RADEONPreInitVisual(ScrnInfoPtr pScrn) 1213{ 1214 RADEONInfoPtr info = RADEONPTR(pScrn); 1215 1216 if (!xf86SetDepthBpp(pScrn, 0, 0, 0, Support32bppFb)) 1217 return FALSE; 1218 1219 switch (pScrn->depth) { 1220 case 8: 1221 case 15: 1222 case 16: 1223 case 24: 1224 break; 1225 1226 default: 1227 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1228 "Given depth (%d) is not supported by %s driver\n", 1229 pScrn->depth, RADEON_DRIVER_NAME); 1230 return FALSE; 1231 } 1232 1233 xf86PrintDepthBpp(pScrn); 1234 1235 info->pix24bpp = xf86GetBppFromDepth(pScrn, 1236 pScrn->depth); 1237 info->pixel_bytes = pScrn->bitsPerPixel / 8; 1238 1239 if (info->pix24bpp == 24) { 1240 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1241 "Radeon does NOT support 24bpp\n"); 1242 return FALSE; 1243 } 1244 1245 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1246 "Pixel depth = %d bits stored in %d byte%s (%d bpp pixmaps)\n", 1247 pScrn->depth, 1248 info->pixel_bytes, 1249 info->pixel_bytes > 1 ? "s" : "", 1250 info->pix24bpp); 1251 1252 if (!xf86SetDefaultVisual(pScrn, -1)) return FALSE; 1253 1254 if (pScrn->depth > 8 && pScrn->defaultVisual != TrueColor) { 1255 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1256 "Default visual (%s) is not supported at depth %d\n", 1257 xf86GetVisualName(pScrn->defaultVisual), pScrn->depth); 1258 return FALSE; 1259 } 1260 return TRUE; 1261} 1262 1263/* This is called by RADEONPreInit to handle all color weight issues */ 1264static Bool RADEONPreInitWeight(ScrnInfoPtr pScrn) 1265{ 1266 RADEONInfoPtr info = RADEONPTR(pScrn); 1267 1268 /* Save flag for 6 bit DAC to use for 1269 setting CRTC registers. Otherwise use 1270 an 8 bit DAC, even if xf86SetWeight sets 1271 pScrn->rgbBits to some value other than 1272 8. */ 1273 info->dac6bits = FALSE; 1274 1275 if (pScrn->depth > 8) { 1276 rgb defaultWeight = { 0, 0, 0 }; 1277 1278 if (!xf86SetWeight(pScrn, defaultWeight, defaultWeight)) return FALSE; 1279 } else { 1280 pScrn->rgbBits = 8; 1281 } 1282 1283 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1284 "Using %d bits per RGB (%d bit DAC)\n", 1285 pScrn->rgbBits, info->dac6bits ? 6 : 8); 1286 1287 return TRUE; 1288} 1289 1290static Bool RADEONPreInitAccel_KMS(ScrnInfoPtr pScrn) 1291{ 1292 RADEONInfoPtr info = RADEONPTR(pScrn); 1293 1294 if (!(info->accel_state = calloc(1, sizeof(struct radeon_accel_state)))) { 1295 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unable to allocate accel_state rec!\n"); 1296 return FALSE; 1297 } 1298 1299 /* Check whether direct mapping is used for fast fb access*/ 1300 if (RADEONIsFastFBWorking(pScrn)) { 1301 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct mapping of fb aperture is enabled for fast fb access.\n"); 1302 info->is_fast_fb = TRUE; 1303 } 1304 1305 if (!xf86ReturnOptValBool(info->Options, OPTION_ACCEL, TRUE) || 1306 (!RADEONIsAccelWorking(pScrn))) { 1307 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1308 "GPU accel disabled or not working, using shadowfb for KMS\n"); 1309shadowfb: 1310 info->r600_shadow_fb = TRUE; 1311 if (!xf86LoadSubModule(pScrn, "shadow")) 1312 info->r600_shadow_fb = FALSE; 1313 return TRUE; 1314 } 1315 1316#ifdef DRI2 1317 info->dri2.available = !!xf86LoadSubModule(pScrn, "dri2"); 1318#endif 1319 1320 if (radeon_glamor_pre_init(pScrn)) 1321 return TRUE; 1322 1323 if (info->ChipFamily >= CHIP_FAMILY_TAHITI) { 1324 goto shadowfb; 1325 } else if (info->ChipFamily == CHIP_FAMILY_PALM) { 1326 info->accel_state->allowHWDFS = RADEONIsFusionGARTWorking(pScrn); 1327 } else 1328 info->accel_state->allowHWDFS = TRUE; 1329 1330 if ((info->ChipFamily == CHIP_FAMILY_RS100) || 1331 (info->ChipFamily == CHIP_FAMILY_RS200) || 1332 (info->ChipFamily == CHIP_FAMILY_RS300) || 1333 (info->ChipFamily == CHIP_FAMILY_RS400) || 1334 (info->ChipFamily == CHIP_FAMILY_RS480) || 1335 (info->ChipFamily == CHIP_FAMILY_RS600) || 1336 (info->ChipFamily == CHIP_FAMILY_RS690) || 1337 (info->ChipFamily == CHIP_FAMILY_RS740)) 1338 info->accel_state->has_tcl = FALSE; 1339 else { 1340 info->accel_state->has_tcl = TRUE; 1341 } 1342 1343 { 1344 int errmaj = 0, errmin = 0; 1345 info->exaReq.majorversion = EXA_VERSION_MAJOR; 1346 info->exaReq.minorversion = EXA_VERSION_MINOR; 1347 if (!LoadSubModule(pScrn->module, "exa", NULL, NULL, NULL, 1348 &info->exaReq, &errmaj, &errmin)) { 1349 LoaderErrorMsg(NULL, "exa", errmaj, errmin); 1350 return FALSE; 1351 } 1352 } 1353 1354 return TRUE; 1355} 1356 1357static Bool RADEONPreInitChipType_KMS(ScrnInfoPtr pScrn) 1358{ 1359 RADEONInfoPtr info = RADEONPTR(pScrn); 1360 int i; 1361 1362 info->Chipset = PCI_DEV_DEVICE_ID(info->PciInfo); 1363 pScrn->chipset = (char *)xf86TokenToString(RADEONChipsets, info->Chipset); 1364 if (!pScrn->chipset) { 1365 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1366 "ChipID 0x%04x is not recognized\n", info->Chipset); 1367 return FALSE; 1368 } 1369 1370 if (info->Chipset < 0) { 1371 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1372 "Chipset \"%s\" is not recognized\n", pScrn->chipset); 1373 return FALSE; 1374 } 1375 xf86DrvMsg(pScrn->scrnIndex, X_PROBED, 1376 "Chipset: \"%s\" (ChipID = 0x%04x)\n", 1377 pScrn->chipset, 1378 info->Chipset); 1379 1380 for (i = 0; i < sizeof(RADEONCards) / sizeof(RADEONCardInfo); i++) { 1381 if (info->Chipset == RADEONCards[i].pci_device_id) { 1382 RADEONCardInfo *card = &RADEONCards[i]; 1383 info->ChipFamily = card->chip_family; 1384 break; 1385 } 1386 } 1387 1388#ifdef RENDER 1389 info->RenderAccel = xf86ReturnOptValBool(info->Options, OPTION_RENDER_ACCEL, 1390 info->Chipset != PCI_CHIP_RN50_515E && 1391 info->Chipset != PCI_CHIP_RN50_5969); 1392#endif 1393 return TRUE; 1394} 1395 1396static int radeon_get_drm_master_fd(ScrnInfoPtr pScrn) 1397{ 1398 RADEONInfoPtr info = RADEONPTR(pScrn); 1399#ifdef XF86_PDEV_SERVER_FD 1400 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 1401#endif 1402 struct pci_device *dev = info->PciInfo; 1403 char *busid; 1404 int fd; 1405 1406#ifdef XF86_PDEV_SERVER_FD 1407 if (pRADEONEnt->platform_dev) { 1408 fd = xf86_get_platform_device_int_attrib(pRADEONEnt->platform_dev, 1409 ODEV_ATTRIB_FD, -1); 1410 if (fd != -1) 1411 return fd; 1412 } 1413#endif 1414 1415 XNFasprintf(&busid, "pci:%04x:%02x:%02x.%d", 1416 dev->domain, dev->bus, dev->dev, dev->func); 1417 1418 fd = drmOpen(NULL, busid); 1419 if (fd == -1) 1420 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1421 "[drm] Failed to open DRM device for %s: %s\n", 1422 busid, strerror(errno)); 1423 1424 free(busid); 1425 return fd; 1426} 1427 1428static Bool radeon_open_drm_master(ScrnInfoPtr pScrn) 1429{ 1430 RADEONInfoPtr info = RADEONPTR(pScrn); 1431 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 1432 drmSetVersion sv; 1433 int err; 1434 1435 if (pRADEONEnt->fd) { 1436 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1437 " reusing fd for second head\n"); 1438 1439 info->drmmode.fd = info->dri2.drm_fd = pRADEONEnt->fd; 1440 pRADEONEnt->fd_ref++; 1441 return TRUE; 1442 } 1443 1444 info->dri2.drm_fd = radeon_get_drm_master_fd(pScrn); 1445 if (info->dri2.drm_fd == -1) 1446 return FALSE; 1447 1448 /* Check that what we opened was a master or a master-capable FD, 1449 * by setting the version of the interface we'll use to talk to it. 1450 * (see DRIOpenDRMMaster() in DRI1) 1451 */ 1452 sv.drm_di_major = 1; 1453 sv.drm_di_minor = 1; 1454 sv.drm_dd_major = -1; 1455 sv.drm_dd_minor = -1; 1456 err = drmSetInterfaceVersion(info->dri2.drm_fd, &sv); 1457 if (err != 0) { 1458 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1459 "[drm] failed to set drm interface version.\n"); 1460 drmClose(info->dri2.drm_fd); 1461 info->dri2.drm_fd = -1; 1462 1463 return FALSE; 1464 } 1465 1466 pRADEONEnt->fd = info->dri2.drm_fd; 1467 pRADEONEnt->fd_ref = 1; 1468 info->drmmode.fd = info->dri2.drm_fd; 1469 return TRUE; 1470} 1471 1472static Bool r600_get_tile_config(ScrnInfoPtr pScrn) 1473{ 1474 RADEONInfoPtr info = RADEONPTR(pScrn); 1475 struct drm_radeon_info ginfo; 1476 int r; 1477 uint32_t tmp; 1478 1479 if (info->ChipFamily < CHIP_FAMILY_R600) 1480 return FALSE; 1481 1482 memset(&ginfo, 0, sizeof(ginfo)); 1483 ginfo.request = RADEON_INFO_TILING_CONFIG; 1484 ginfo.value = (uintptr_t)&tmp; 1485 r = drmCommandWriteRead(info->dri2.drm_fd, DRM_RADEON_INFO, &ginfo, sizeof(ginfo)); 1486 if (r) 1487 return FALSE; 1488 1489 info->tile_config = tmp; 1490 info->r7xx_bank_op = 0; 1491 if (info->ChipFamily >= CHIP_FAMILY_CEDAR) { 1492 if (info->dri2.pKernelDRMVersion->version_minor >= 7) { 1493 switch (info->tile_config & 0xf) { 1494 case 0: 1495 info->num_channels = 1; 1496 break; 1497 case 1: 1498 info->num_channels = 2; 1499 break; 1500 case 2: 1501 info->num_channels = 4; 1502 break; 1503 case 3: 1504 info->num_channels = 8; 1505 break; 1506 default: 1507 return FALSE; 1508 } 1509 1510 switch((info->tile_config & 0xf0) >> 4) { 1511 case 0: 1512 info->num_banks = 4; 1513 break; 1514 case 1: 1515 info->num_banks = 8; 1516 break; 1517 case 2: 1518 info->num_banks = 16; 1519 break; 1520 default: 1521 return FALSE; 1522 } 1523 1524 switch ((info->tile_config & 0xf00) >> 8) { 1525 case 0: 1526 info->group_bytes = 256; 1527 break; 1528 case 1: 1529 info->group_bytes = 512; 1530 break; 1531 default: 1532 return FALSE; 1533 } 1534 } else 1535 return FALSE; 1536 } else { 1537 switch((info->tile_config & 0xe) >> 1) { 1538 case 0: 1539 info->num_channels = 1; 1540 break; 1541 case 1: 1542 info->num_channels = 2; 1543 break; 1544 case 2: 1545 info->num_channels = 4; 1546 break; 1547 case 3: 1548 info->num_channels = 8; 1549 break; 1550 default: 1551 return FALSE; 1552 } 1553 switch((info->tile_config & 0x30) >> 4) { 1554 case 0: 1555 info->num_banks = 4; 1556 break; 1557 case 1: 1558 info->num_banks = 8; 1559 break; 1560 default: 1561 return FALSE; 1562 } 1563 switch((info->tile_config & 0xc0) >> 6) { 1564 case 0: 1565 info->group_bytes = 256; 1566 break; 1567 case 1: 1568 info->group_bytes = 512; 1569 break; 1570 default: 1571 return FALSE; 1572 } 1573 } 1574 1575 info->have_tiling_info = TRUE; 1576 return TRUE; 1577} 1578 1579static void RADEONSetupCapabilities(ScrnInfoPtr pScrn) 1580{ 1581#ifdef RADEON_PIXMAP_SHARING 1582 RADEONInfoPtr info = RADEONPTR(pScrn); 1583 uint64_t value; 1584 int ret; 1585 1586 pScrn->capabilities = 0; 1587 1588 /* PRIME offloading requires acceleration */ 1589 if (info->r600_shadow_fb) 1590 return; 1591 1592 ret = drmGetCap(info->dri2.drm_fd, DRM_CAP_PRIME, &value); 1593 if (ret == 0) { 1594 if (value & DRM_PRIME_CAP_EXPORT) 1595 pScrn->capabilities |= RR_Capability_SourceOutput | RR_Capability_SourceOffload; 1596 if (value & DRM_PRIME_CAP_IMPORT) { 1597 pScrn->capabilities |= RR_Capability_SinkOffload; 1598 if (info->drmmode.count_crtcs) 1599 pScrn->capabilities |= RR_Capability_SinkOutput; 1600 } 1601 } 1602#endif 1603} 1604 1605/* When the root window is created, initialize the screen contents from 1606 * console if -background none was specified on the command line 1607 */ 1608static Bool RADEONCreateWindow_oneshot(WindowPtr pWin) 1609{ 1610 ScreenPtr pScreen = pWin->drawable.pScreen; 1611 ScrnInfoPtr pScrn; 1612 RADEONInfoPtr info; 1613 Bool ret; 1614 1615 if (pWin != pScreen->root) 1616 ErrorF("%s called for non-root window %p\n", __func__, pWin); 1617 1618 pScrn = xf86ScreenToScrn(pScreen); 1619 info = RADEONPTR(pScrn); 1620 pScreen->CreateWindow = info->CreateWindow; 1621 ret = pScreen->CreateWindow(pWin); 1622 1623 if (ret) 1624 drmmode_copy_fb(pScrn, &info->drmmode); 1625 1626 return ret; 1627} 1628 1629/* When the root window is mapped, set the initial modes */ 1630static void RADEONWindowExposures_oneshot(WindowPtr pWin, RegionPtr pRegion 1631#if XORG_VERSION_CURRENT < XORG_VERSION_NUMERIC(1,16,99,901,0) 1632 , RegionPtr pBSRegion 1633#endif 1634 ) 1635{ 1636 ScreenPtr pScreen = pWin->drawable.pScreen; 1637 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); 1638 RADEONInfoPtr info = RADEONPTR(pScrn); 1639 1640 if (pWin != pScreen->root) 1641 ErrorF("%s called for non-root window %p\n", __func__, pWin); 1642 1643 pScreen->WindowExposures = info->WindowExposures; 1644#if XORG_VERSION_CURRENT < XORG_VERSION_NUMERIC(1,16,99,901,0) 1645 pScreen->WindowExposures(pWin, pRegion, pBSRegion); 1646#else 1647 pScreen->WindowExposures(pWin, pRegion); 1648#endif 1649 1650 radeon_cs_flush_indirect(pScrn); 1651 radeon_bo_wait(info->front_bo); 1652 drmmode_set_desired_modes(pScrn, &info->drmmode, TRUE); 1653} 1654 1655Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int flags) 1656{ 1657 RADEONInfoPtr info; 1658 RADEONEntPtr pRADEONEnt; 1659 MessageType from; 1660 DevUnion* pPriv; 1661 Gamma zeros = { 0.0, 0.0, 0.0 }; 1662 uint32_t tiling = 0; 1663 int cpp; 1664 1665 if (flags & PROBE_DETECT) 1666 return TRUE; 1667 1668 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 1669 "RADEONPreInit_KMS\n"); 1670 if (pScrn->numEntities != 1) return FALSE; 1671 if (!RADEONGetRec(pScrn)) return FALSE; 1672 1673 info = RADEONPTR(pScrn); 1674 info->IsSecondary = FALSE; 1675 info->pEnt = xf86GetEntityInfo(pScrn->entityList[pScrn->numEntities - 1]); 1676 if (info->pEnt->location.type != BUS_PCI 1677#ifdef XSERVER_PLATFORM_BUS 1678 && info->pEnt->location.type != BUS_PLATFORM 1679#endif 1680 ) 1681 goto fail; 1682 1683 pPriv = xf86GetEntityPrivate(pScrn->entityList[0], 1684 getRADEONEntityIndex()); 1685 pRADEONEnt = pPriv->ptr; 1686 1687 if(xf86IsEntityShared(pScrn->entityList[0])) 1688 { 1689 if(xf86IsPrimInitDone(pScrn->entityList[0])) 1690 { 1691 info->IsSecondary = TRUE; 1692 } 1693 else 1694 { 1695 xf86SetPrimInitDone(pScrn->entityList[0]); 1696 } 1697 } 1698 1699 if (info->IsSecondary) 1700 pRADEONEnt->secondary_scrn = pScrn; 1701 else 1702 pRADEONEnt->primary_scrn = pScrn; 1703 1704 info->PciInfo = xf86GetPciInfoForEntity(info->pEnt->index); 1705 pScrn->monitor = pScrn->confScreen->monitor; 1706 1707 if (!RADEONPreInitVisual(pScrn)) 1708 goto fail; 1709 1710 xf86CollectOptions(pScrn, NULL); 1711 if (!(info->Options = malloc(sizeof(RADEONOptions_KMS)))) 1712 goto fail; 1713 1714 memcpy(info->Options, RADEONOptions_KMS, sizeof(RADEONOptions_KMS)); 1715 xf86ProcessOptions(pScrn->scrnIndex, pScrn->options, info->Options); 1716 1717 if (!RADEONPreInitWeight(pScrn)) 1718 goto fail; 1719 1720 if (!RADEONPreInitChipType_KMS(pScrn)) 1721 goto fail; 1722 1723 if (radeon_open_drm_master(pScrn) == FALSE) { 1724 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Kernel modesetting setup failed\n"); 1725 goto fail; 1726 } 1727 1728 info->dri2.available = FALSE; 1729 info->dri2.enabled = FALSE; 1730 info->dri2.pKernelDRMVersion = drmGetVersion(info->dri2.drm_fd); 1731 if (info->dri2.pKernelDRMVersion == NULL) { 1732 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1733 "RADEONDRIGetVersion failed to get the DRM version\n"); 1734 goto fail; 1735 } 1736 1737 /* Get ScreenInit function */ 1738 if (!xf86LoadSubModule(pScrn, "fb")) 1739 return FALSE; 1740 1741 if (!RADEONPreInitAccel_KMS(pScrn)) goto fail; 1742 1743 radeon_drm_queue_init(); 1744 1745 info->allowColorTiling2D = FALSE; 1746 1747 /* don't enable tiling if accel is not enabled */ 1748 if (!info->r600_shadow_fb) { 1749 Bool colorTilingDefault = 1750 info->ChipFamily >= CHIP_FAMILY_R300 && 1751 /* this check could be removed sometime after a big mesa release 1752 * with proper bit, in the meantime you need to set tiling option in 1753 * xorg configuration files 1754 */ 1755 info->ChipFamily <= CHIP_FAMILY_MULLINS && 1756 !info->is_fast_fb; 1757 1758 /* 2D color tiling */ 1759 if (info->ChipFamily >= CHIP_FAMILY_R600) { 1760 info->allowColorTiling2D = xf86ReturnOptValBool(info->Options, OPTION_COLOR_TILING_2D, 1761 info->ChipFamily <= CHIP_FAMILY_MULLINS); 1762 } 1763 1764 if (info->ChipFamily >= CHIP_FAMILY_R600) { 1765 /* set default group bytes, overridden by kernel info below */ 1766 info->group_bytes = 256; 1767 info->have_tiling_info = FALSE; 1768 if (info->dri2.pKernelDRMVersion->version_minor >= 6) { 1769 if (r600_get_tile_config(pScrn)) { 1770 info->allowColorTiling = xf86ReturnOptValBool(info->Options, 1771 OPTION_COLOR_TILING, colorTilingDefault); 1772 if (!info->use_glamor) { 1773 /* need working DFS for tiling */ 1774 if (info->ChipFamily == CHIP_FAMILY_PALM && 1775 !info->accel_state->allowHWDFS) 1776 info->allowColorTiling = FALSE; 1777 } 1778 } else 1779 info->allowColorTiling = FALSE; 1780 } else 1781 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1782 "R6xx+ KMS Color Tiling requires radeon drm 2.6.0 or newer\n"); 1783 } else 1784 info->allowColorTiling = xf86ReturnOptValBool(info->Options, 1785 OPTION_COLOR_TILING, colorTilingDefault); 1786 } else 1787 info->allowColorTiling = FALSE; 1788 1789 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1790 "KMS Color Tiling: %sabled\n", info->allowColorTiling ? "en" : "dis"); 1791 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1792 "KMS Color Tiling 2D: %sabled\n", info->allowColorTiling2D ? "en" : "dis"); 1793 1794#if USE_GLAMOR 1795 if (info->use_glamor) { 1796 info->shadow_primary = xf86ReturnOptValBool(info->Options, 1797 OPTION_SHADOW_PRIMARY, FALSE); 1798 1799 if (info->shadow_primary) 1800 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "ShadowPrimary enabled\n"); 1801 } 1802#endif 1803 1804 if (!info->r600_shadow_fb) { 1805 from = X_DEFAULT; 1806 1807 info->tear_free = 2; 1808 if (xf86GetOptValBool(info->Options, OPTION_TEAR_FREE, 1809 &info->tear_free)) 1810 from = X_CONFIG; 1811 xf86DrvMsg(pScrn->scrnIndex, from, "TearFree property default: %s\n", 1812 info->tear_free == 2 ? "auto" : (info->tear_free ? "on" : "off")); 1813 } 1814 1815 if (!radeon_is_gpu_scrn(pScrn)) { 1816 if (info->dri2.pKernelDRMVersion->version_minor >= 8) { 1817 Bool sw_cursor = xf86ReturnOptValBool(info->Options, 1818 OPTION_SW_CURSOR, FALSE); 1819 1820 info->allowPageFlip = xf86ReturnOptValBool(info->Options, 1821 OPTION_PAGE_FLIP, TRUE); 1822 1823 if (sw_cursor || info->shadow_primary) { 1824 xf86DrvMsg(pScrn->scrnIndex, 1825 info->allowPageFlip ? X_WARNING : X_DEFAULT, 1826 "KMS Pageflipping: disabled%s\n", 1827 info->allowPageFlip ? 1828 (sw_cursor ? " because of SWcursor" : 1829 " because of ShadowPrimary") : ""); 1830 info->allowPageFlip = FALSE; 1831 } else { 1832 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1833 "KMS Pageflipping: %sabled\n", 1834 info->allowPageFlip ? "en" : "dis"); 1835 } 1836 } 1837 1838 if (!info->use_glamor) { 1839 info->swapBuffersWait = 1840 xf86ReturnOptValBool(info->Options, OPTION_SWAPBUFFERS_WAIT, TRUE); 1841 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1842 "SwapBuffers wait for vsync: %sabled\n", 1843 info->swapBuffersWait ? "en" : "dis"); 1844 } 1845 } 1846 1847 if (xf86ReturnOptValBool(info->Options, OPTION_DELETE_DP12, FALSE)) { 1848 info->drmmode.delete_dp_12_displays = TRUE; 1849 } 1850 1851 if (drmmode_pre_init(pScrn, &info->drmmode, pScrn->bitsPerPixel / 8) == FALSE) { 1852 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Kernel modesetting setup failed\n"); 1853 goto fail; 1854 } 1855 1856 RADEONSetupCapabilities(pScrn); 1857 1858 if (info->drmmode.count_crtcs == 1) 1859 pRADEONEnt->HasCRTC2 = FALSE; 1860 else 1861 pRADEONEnt->HasCRTC2 = TRUE; 1862 1863 1864 /* fix up cloning on rn50 cards 1865 * since they only have one crtc sometimes the xserver doesn't assign 1866 * a crtc to one of the outputs even though both outputs have common modes 1867 * which results in only one monitor being enabled. Assign a crtc here so 1868 * that both outputs light up. 1869 */ 1870 if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2) { 1871 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 1872 int i; 1873 1874 for (i = 0; i < xf86_config->num_output; i++) { 1875 xf86OutputPtr output = xf86_config->output[i]; 1876 1877 /* XXX: double check crtc mode */ 1878 if ((output->probed_modes != NULL) && (output->crtc == NULL)) 1879 output->crtc = xf86_config->crtc[0]; 1880 } 1881 } 1882 1883 /* set cursor size */ 1884 if (info->ChipFamily >= CHIP_FAMILY_BONAIRE) { 1885 info->cursor_w = CURSOR_WIDTH_CIK; 1886 info->cursor_h = CURSOR_HEIGHT_CIK; 1887 } else { 1888 info->cursor_w = CURSOR_WIDTH; 1889 info->cursor_h = CURSOR_HEIGHT; 1890 } 1891 1892 { 1893 struct drm_radeon_gem_info mminfo; 1894 1895 if (!drmCommandWriteRead(info->dri2.drm_fd, DRM_RADEON_GEM_INFO, &mminfo, sizeof(mminfo))) 1896 { 1897 info->vram_size = mminfo.vram_visible; 1898 info->gart_size = mminfo.gart_size; 1899 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1900 "mem size init: gart size :%llx vram size: s:%llx visible:%llx\n", 1901 (unsigned long long)mminfo.gart_size, 1902 (unsigned long long)mminfo.vram_size, 1903 (unsigned long long)mminfo.vram_visible); 1904 } 1905 } 1906 1907 if (!info->use_glamor) { 1908 info->exa_pixmaps = xf86ReturnOptValBool(info->Options, 1909 OPTION_EXA_PIXMAPS, 1910 (info->vram_size > (32 * 1024 * 1024) && 1911 info->RenderAccel && 1912 !info->is_fast_fb)); 1913 if (info->exa_pixmaps) 1914 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1915 "EXA: Driver will allow EXA pixmaps in VRAM\n"); 1916 else 1917 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1918 "EXA: Driver will not allow EXA pixmaps in VRAM\n"); 1919 } 1920 1921 /* no tiled scanout on r6xx+ yet */ 1922 if (info->allowColorTiling) { 1923 if (info->ChipFamily >= CHIP_FAMILY_R600) 1924 tiling |= RADEON_TILING_MICRO; 1925 else 1926 tiling |= RADEON_TILING_MACRO; 1927 } 1928 cpp = pScrn->bitsPerPixel / 8; 1929 pScrn->displayWidth = 1930 RADEON_ALIGN(pScrn->virtualX, drmmode_get_pitch_align(pScrn, cpp, tiling)); 1931 1932 /* Set display resolution */ 1933 xf86SetDpi(pScrn, 0, 0); 1934 1935 if (!xf86SetGamma(pScrn, zeros)) return FALSE; 1936 1937 if (!xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) { 1938 if (!xf86LoadSubModule(pScrn, "ramdac")) return FALSE; 1939 } 1940 1941 if (pScrn->modes == NULL 1942#ifdef XSERVER_PLATFORM_BUS 1943 && !pScrn->is_gpu 1944#endif 1945 ) { 1946 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No modes.\n"); 1947 goto fail; 1948 } 1949 1950 return TRUE; 1951 fail: 1952 RADEONFreeRec(pScrn); 1953 return FALSE; 1954 1955} 1956 1957static Bool RADEONCursorInit_KMS(ScreenPtr pScreen) 1958{ 1959 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); 1960 RADEONInfoPtr info = RADEONPTR(pScrn); 1961 1962 return xf86_cursors_init (pScreen, info->cursor_w, info->cursor_h, 1963 (HARDWARE_CURSOR_TRUECOLOR_AT_8BPP | 1964 HARDWARE_CURSOR_AND_SOURCE_WITH_MASK | 1965 HARDWARE_CURSOR_SOURCE_MASK_INTERLEAVE_1 | 1966 HARDWARE_CURSOR_UPDATE_UNHIDDEN | 1967 HARDWARE_CURSOR_ARGB)); 1968} 1969 1970void 1971RADEONBlank(ScrnInfoPtr pScrn) 1972{ 1973 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 1974 xf86OutputPtr output; 1975 xf86CrtcPtr crtc; 1976 int o, c; 1977 1978 for (c = 0; c < xf86_config->num_crtc; c++) { 1979 crtc = xf86_config->crtc[c]; 1980 for (o = 0; o < xf86_config->num_output; o++) { 1981 output = xf86_config->output[o]; 1982 if (output->crtc != crtc) 1983 continue; 1984 1985 output->funcs->dpms(output, DPMSModeOff); 1986 } 1987 crtc->funcs->dpms(crtc, DPMSModeOff); 1988 } 1989} 1990 1991void 1992RADEONUnblank(ScrnInfoPtr pScrn) 1993{ 1994 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 1995 xf86OutputPtr output; 1996 xf86CrtcPtr crtc; 1997 int o, c; 1998 for (c = 0; c < xf86_config->num_crtc; c++) { 1999 crtc = xf86_config->crtc[c]; 2000 if(!crtc->enabled) 2001 continue; 2002 crtc->funcs->dpms(crtc, DPMSModeOn); 2003 for (o = 0; o < xf86_config->num_output; o++) { 2004 output = xf86_config->output[o]; 2005 if (output->crtc != crtc) 2006 continue; 2007 output->funcs->dpms(output, DPMSModeOn); 2008 } 2009 } 2010} 2011 2012 2013static Bool RADEONSaveScreen_KMS(ScreenPtr pScreen, int mode) 2014{ 2015 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); 2016 Bool unblank; 2017 2018 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 2019 "RADEONSaveScreen(%d)\n", mode); 2020 2021 unblank = xf86IsUnblank(mode); 2022 if (unblank) SetTimeSinceLastInputEvent(); 2023 2024 if ((pScrn != NULL) && pScrn->vtSema) { 2025 if (unblank) 2026 RADEONUnblank(pScrn); 2027 else 2028 RADEONBlank(pScrn); 2029 } 2030 return TRUE; 2031} 2032 2033static Bool radeon_set_drm_master(ScrnInfoPtr pScrn) 2034{ 2035 RADEONInfoPtr info = RADEONPTR(pScrn); 2036#ifdef XF86_PDEV_SERVER_FD 2037 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 2038#endif 2039 int err; 2040 2041#ifdef XF86_PDEV_SERVER_FD 2042 if (pRADEONEnt->platform_dev && 2043 (pRADEONEnt->platform_dev->flags & XF86_PDEV_SERVER_FD)) 2044 return TRUE; 2045#endif 2046 2047 err = drmSetMaster(info->dri2.drm_fd); 2048 if (err) 2049 ErrorF("Unable to retrieve master\n"); 2050 2051 return err == 0; 2052} 2053 2054static void radeon_drop_drm_master(ScrnInfoPtr pScrn) 2055{ 2056 RADEONInfoPtr info = RADEONPTR(pScrn); 2057#ifdef XF86_PDEV_SERVER_FD 2058 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 2059 2060 if (pRADEONEnt->platform_dev && 2061 (pRADEONEnt->platform_dev->flags & XF86_PDEV_SERVER_FD)) 2062 return; 2063#endif 2064 2065 drmDropMaster(info->dri2.drm_fd); 2066} 2067 2068/* Called at the end of each server generation. Restore the original 2069 * text mode, unmap video memory, and unwrap and call the saved 2070 * CloseScreen function. 2071 */ 2072static Bool RADEONCloseScreen_KMS(CLOSE_SCREEN_ARGS_DECL) 2073{ 2074 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); 2075 RADEONInfoPtr info = RADEONPTR(pScrn); 2076 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 2077 2078 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 2079 "RADEONCloseScreen\n"); 2080 2081 /* Clear mask of assigned crtc's in this generation */ 2082 pRADEONEnt->assigned_crtcs = 0; 2083 2084 drmmode_uevent_fini(pScrn, &info->drmmode); 2085 radeon_drm_queue_close(pScrn); 2086 radeon_cs_flush_indirect(pScrn); 2087 2088 if (info->callback_event_type != -1) { 2089 DeleteCallback(&EventCallback, radeon_event_callback, pScrn); 2090 DeleteCallback(&FlushCallback, radeon_flush_callback, pScrn); 2091 } 2092 2093 if (info->accel_state->exa) { 2094 exaDriverFini(pScreen); 2095 free(info->accel_state->exa); 2096 info->accel_state->exa = NULL; 2097 } 2098 2099 radeon_sync_close(pScreen); 2100 2101 if (info->accel_state->use_vbos) 2102 radeon_vbo_free_lists(pScrn); 2103 2104 radeon_drop_drm_master(pScrn); 2105 2106 drmmode_fini(pScrn, &info->drmmode); 2107 if (info->dri2.enabled) 2108 radeon_dri2_close_screen(pScreen); 2109 2110 radeon_glamor_fini(pScreen); 2111 2112 pScrn->vtSema = FALSE; 2113 xf86ClearPrimInitDone(info->pEnt->index); 2114 pScreen->BlockHandler = info->BlockHandler; 2115 pScreen->CloseScreen = info->CloseScreen; 2116 return (*pScreen->CloseScreen)(CLOSE_SCREEN_ARGS); 2117} 2118 2119 2120void RADEONFreeScreen_KMS(FREE_SCREEN_ARGS_DECL) 2121{ 2122 SCRN_INFO_PTR(arg); 2123 RADEONInfoPtr info = RADEONPTR(pScrn); 2124 2125 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 2126 "RADEONFreeScreen\n"); 2127 2128 /* when server quits at PreInit, we don't need do this anymore*/ 2129 if (!info) return; 2130 2131 RADEONFreeRec(pScrn); 2132} 2133 2134Bool RADEONScreenInit_KMS(SCREEN_INIT_ARGS_DECL) 2135{ 2136 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); 2137 RADEONInfoPtr info = RADEONPTR(pScrn); 2138 int subPixelOrder = SubPixelUnknown; 2139 MessageType from; 2140 Bool value; 2141 int driLevel; 2142 const char *s; 2143 void *front_ptr; 2144 2145 pScrn->fbOffset = 0; 2146 2147 miClearVisualTypes(); 2148 if (!miSetVisualTypes(pScrn->depth, 2149 miGetDefaultVisualMask(pScrn->depth), 2150 pScrn->rgbBits, 2151 pScrn->defaultVisual)) return FALSE; 2152 miSetPixmapDepths (); 2153 2154 if (!radeon_set_drm_master(pScrn)) 2155 return FALSE; 2156 2157 info->directRenderingEnabled = FALSE; 2158 if (info->r600_shadow_fb == FALSE) 2159 info->directRenderingEnabled = radeon_dri2_screen_init(pScreen); 2160 2161 info->surf_man = radeon_surface_manager_new(info->dri2.drm_fd); 2162 if (!info->bufmgr) 2163 info->bufmgr = radeon_bo_manager_gem_ctor(info->dri2.drm_fd); 2164 if (!info->bufmgr) { 2165 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2166 "failed to initialise GEM buffer manager"); 2167 return FALSE; 2168 } 2169 drmmode_set_bufmgr(pScrn, &info->drmmode, info->bufmgr); 2170 2171 if (!info->csm) 2172 info->csm = radeon_cs_manager_gem_ctor(info->dri2.drm_fd); 2173 if (!info->csm) { 2174 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2175 "failed to initialise command submission manager"); 2176 return FALSE; 2177 } 2178 2179 if (!info->cs) 2180 info->cs = radeon_cs_create(info->csm, RADEON_BUFFER_SIZE/4); 2181 if (!info->cs) { 2182 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2183 "failed to initialise command submission buffer"); 2184 return FALSE; 2185 } 2186 2187 radeon_cs_set_limit(info->cs, RADEON_GEM_DOMAIN_GTT, info->gart_size); 2188 radeon_cs_space_set_flush(info->cs, (void(*)(void *))radeon_cs_flush_indirect, pScrn); 2189 2190 if (!radeon_setup_kernel_mem(pScreen)) { 2191 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "radeon_setup_kernel_mem failed\n"); 2192 return FALSE; 2193 } 2194 front_ptr = info->front_bo->ptr; 2195 2196 if (info->r600_shadow_fb) { 2197 info->fb_shadow = calloc(1, 2198 pScrn->displayWidth * pScrn->virtualY * 2199 ((pScrn->bitsPerPixel + 7) >> 3)); 2200 if (info->fb_shadow == NULL) { 2201 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2202 "Failed to allocate shadow framebuffer\n"); 2203 info->r600_shadow_fb = FALSE; 2204 } else { 2205 if (!fbScreenInit(pScreen, info->fb_shadow, 2206 pScrn->virtualX, pScrn->virtualY, 2207 pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth, 2208 pScrn->bitsPerPixel)) 2209 return FALSE; 2210 } 2211 } 2212 2213 if (info->r600_shadow_fb == FALSE) { 2214 /* Init fb layer */ 2215 if (!fbScreenInit(pScreen, front_ptr, 2216 pScrn->virtualX, pScrn->virtualY, 2217 pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth, 2218 pScrn->bitsPerPixel)) 2219 return FALSE; 2220 } 2221 2222 xf86SetBlackWhitePixels(pScreen); 2223 2224 if (pScrn->bitsPerPixel > 8) { 2225 VisualPtr visual; 2226 2227 visual = pScreen->visuals + pScreen->numVisuals; 2228 while (--visual >= pScreen->visuals) { 2229 if ((visual->class | DynamicClass) == DirectColor) { 2230 visual->offsetRed = pScrn->offset.red; 2231 visual->offsetGreen = pScrn->offset.green; 2232 visual->offsetBlue = pScrn->offset.blue; 2233 visual->redMask = pScrn->mask.red; 2234 visual->greenMask = pScrn->mask.green; 2235 visual->blueMask = pScrn->mask.blue; 2236 } 2237 } 2238 } 2239 2240 /* Must be after RGB order fixed */ 2241 fbPictureInit (pScreen, 0, 0); 2242 2243#ifdef RENDER 2244 if ((s = xf86GetOptValString(info->Options, OPTION_SUBPIXEL_ORDER))) { 2245 if (strcmp(s, "RGB") == 0) subPixelOrder = SubPixelHorizontalRGB; 2246 else if (strcmp(s, "BGR") == 0) subPixelOrder = SubPixelHorizontalBGR; 2247 else if (strcmp(s, "NONE") == 0) subPixelOrder = SubPixelNone; 2248 PictureSetSubpixelOrder (pScreen, subPixelOrder); 2249 } 2250#endif 2251 2252 if (!radeon_is_gpu_screen(pScreen)) { 2253 if (xorgGetVersion() >= XORG_VERSION_NUMERIC(1,18,3,0,0)) 2254 value = info->use_glamor; 2255 else 2256 value = FALSE; 2257 from = X_DEFAULT; 2258 2259 if (!info->r600_shadow_fb) { 2260 if (xf86GetOptValBool(info->Options, OPTION_DRI3, &value)) 2261 from = X_CONFIG; 2262 2263 if (xf86GetOptValInteger(info->Options, OPTION_DRI, &driLevel) && 2264 (driLevel == 2 || driLevel == 3)) { 2265 from = X_CONFIG; 2266 value = driLevel == 3; 2267 } 2268 } 2269 2270 if (value) { 2271 value = radeon_sync_init(pScreen) && 2272 radeon_present_screen_init(pScreen) && 2273 radeon_dri3_screen_init(pScreen); 2274 2275 if (!value) 2276 from = X_WARNING; 2277 } 2278 2279 xf86DrvMsg(pScrn->scrnIndex, from, "DRI3 %sabled\n", value ? "en" : "dis"); 2280 } 2281 2282 pScrn->vtSema = TRUE; 2283 xf86SetBackingStore(pScreen); 2284 2285 if (info->directRenderingEnabled) { 2286 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct rendering enabled\n"); 2287 } else { 2288 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 2289 "Direct rendering disabled\n"); 2290 } 2291 2292 if (info->r600_shadow_fb) { 2293 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Acceleration disabled\n"); 2294 info->accelOn = FALSE; 2295 } else { 2296 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 2297 "Initializing Acceleration\n"); 2298 if (RADEONAccelInit(pScreen)) { 2299 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Acceleration enabled\n"); 2300 info->accelOn = TRUE; 2301 } else { 2302 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2303 "Acceleration initialization failed\n"); 2304 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Acceleration disabled\n"); 2305 info->accelOn = FALSE; 2306 } 2307 } 2308 2309 /* Init DPMS */ 2310 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 2311 "Initializing DPMS\n"); 2312 xf86DPMSInit(pScreen, xf86DPMSSet, 0); 2313 2314 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 2315 "Initializing Cursor\n"); 2316 2317 /* Set Silken Mouse */ 2318 xf86SetSilkenMouse(pScreen); 2319 2320 /* Cursor setup */ 2321 miDCInitialize(pScreen, xf86GetPointerScreenFuncs()); 2322 2323 if (!xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) { 2324 if (RADEONCursorInit_KMS(pScreen)) { 2325 } 2326 } 2327 2328 /* DGA setup */ 2329#ifdef XFreeXDGA 2330 /* DGA is dangerous on kms as the base and framebuffer location may change: 2331 * http://lists.freedesktop.org/archives/xorg-devel/2009-September/002113.html 2332 */ 2333 /* xf86DiDGAInit(pScreen, info->LinearAddr + pScrn->fbOffset); */ 2334#endif 2335 if (info->r600_shadow_fb == FALSE && 2336 !radeon_is_gpu_screen(pScreen)) { 2337 /* Init Xv */ 2338 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 2339 "Initializing Xv\n"); 2340 RADEONInitVideo(pScreen); 2341 } 2342 2343 if (info->r600_shadow_fb == TRUE) { 2344 if (!shadowSetup(pScreen)) { 2345 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2346 "Shadowfb initialization failed\n"); 2347 return FALSE; 2348 } 2349 } 2350 pScrn->pScreen = pScreen; 2351 2352 if (!radeon_is_gpu_screen(pScreen)) { 2353 if (serverGeneration == 1 && bgNoneRoot && info->accelOn) { 2354 info->CreateWindow = pScreen->CreateWindow; 2355 pScreen->CreateWindow = RADEONCreateWindow_oneshot; 2356 } 2357 info->WindowExposures = pScreen->WindowExposures; 2358 pScreen->WindowExposures = RADEONWindowExposures_oneshot; 2359 } 2360 2361 /* Provide SaveScreen & wrap BlockHandler and CloseScreen */ 2362 /* Wrap CloseScreen */ 2363 info->CloseScreen = pScreen->CloseScreen; 2364 pScreen->CloseScreen = RADEONCloseScreen_KMS; 2365 pScreen->SaveScreen = RADEONSaveScreen_KMS; 2366 info->BlockHandler = pScreen->BlockHandler; 2367 pScreen->BlockHandler = RADEONBlockHandler_KMS; 2368 2369 info->CreateScreenResources = pScreen->CreateScreenResources; 2370 pScreen->CreateScreenResources = RADEONCreateScreenResources_KMS; 2371 2372#ifdef RADEON_PIXMAP_SHARING 2373 pScreen->StartPixmapTracking = PixmapStartDirtyTracking; 2374 pScreen->StopPixmapTracking = PixmapStopDirtyTracking; 2375#if HAS_SYNC_SHARED_PIXMAP 2376 pScreen->SyncSharedPixmap = radeon_sync_shared_pixmap; 2377#endif 2378#endif 2379 2380 if (!xf86CrtcScreenInit (pScreen)) 2381 return FALSE; 2382 2383 /* Wrap pointer motion to flip touch screen around */ 2384// info->PointerMoved = pScrn->PointerMoved; 2385// pScrn->PointerMoved = RADEONPointerMoved; 2386 2387 if (!drmmode_setup_colormap(pScreen, pScrn)) 2388 return FALSE; 2389 2390 /* Note unused options */ 2391 if (serverGeneration == 1) 2392 xf86ShowUnusedOptions(pScrn->scrnIndex, pScrn->options); 2393 2394 drmmode_init(pScrn, &info->drmmode); 2395 2396 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 2397 "RADEONScreenInit finished\n"); 2398 2399 info->accel_state->XInited3D = FALSE; 2400 info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN; 2401 2402 return TRUE; 2403} 2404 2405Bool RADEONEnterVT_KMS(VT_FUNC_ARGS_DECL) 2406{ 2407 SCRN_INFO_PTR(arg); 2408 RADEONInfoPtr info = RADEONPTR(pScrn); 2409 2410 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 2411 "RADEONEnterVT_KMS\n"); 2412 2413 radeon_set_drm_master(pScrn); 2414 2415 info->accel_state->XInited3D = FALSE; 2416 info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN; 2417 2418 pScrn->vtSema = TRUE; 2419 2420 if (!drmmode_set_desired_modes(pScrn, &info->drmmode, TRUE)) 2421 return FALSE; 2422 2423 return TRUE; 2424} 2425 2426 2427void RADEONLeaveVT_KMS(VT_FUNC_ARGS_DECL) 2428{ 2429 SCRN_INFO_PTR(arg); 2430 RADEONInfoPtr info = RADEONPTR(pScrn); 2431 2432 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 2433 "RADEONLeaveVT_KMS\n"); 2434 2435 radeon_drop_drm_master(pScrn); 2436 2437 xf86RotateFreeShadow(pScrn); 2438 drmmode_scanout_free(pScrn); 2439 2440 xf86_hide_cursors (pScrn); 2441 info->accel_state->XInited3D = FALSE; 2442 info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN; 2443 2444 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 2445 "Ok, leaving now...\n"); 2446} 2447 2448 2449Bool RADEONSwitchMode_KMS(SWITCH_MODE_ARGS_DECL) 2450{ 2451 SCRN_INFO_PTR(arg); 2452 Bool ret; 2453 ret = xf86SetSingleMode (pScrn, mode, RR_Rotate_0); 2454 return ret; 2455 2456} 2457 2458void RADEONAdjustFrame_KMS(ADJUST_FRAME_ARGS_DECL) 2459{ 2460 SCRN_INFO_PTR(arg); 2461 RADEONInfoPtr info = RADEONPTR(pScrn); 2462 drmmode_adjust_frame(pScrn, &info->drmmode, x, y); 2463 return; 2464} 2465 2466static Bool radeon_setup_kernel_mem(ScreenPtr pScreen) 2467{ 2468 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); 2469 RADEONInfoPtr info = RADEONPTR(pScrn); 2470 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 2471 int cpp = info->pixel_bytes; 2472 uint32_t screen_size; 2473 int pitch, base_align; 2474 uint32_t tiling_flags = 0; 2475 struct radeon_surface surface; 2476 2477 if (info->accel_state->exa != NULL) { 2478 xf86DrvMsg(pScreen->myNum, X_ERROR, "Memory map already initialized\n"); 2479 return FALSE; 2480 } 2481 if (!info->use_glamor && info->r600_shadow_fb == FALSE) { 2482 info->accel_state->exa = exaDriverAlloc(); 2483 if (info->accel_state->exa == NULL) { 2484 xf86DrvMsg(pScreen->myNum, X_ERROR, "exaDriverAlloc failed\n"); 2485 return FALSE; 2486 } 2487 } 2488 2489 if (info->allowColorTiling && !info->shadow_primary) { 2490 if (info->ChipFamily >= CHIP_FAMILY_R600) { 2491 if (info->allowColorTiling2D) { 2492 tiling_flags |= RADEON_TILING_MACRO; 2493 } else { 2494 tiling_flags |= RADEON_TILING_MICRO; 2495 } 2496 } else 2497 tiling_flags |= RADEON_TILING_MACRO; 2498 } 2499 pitch = RADEON_ALIGN(pScrn->virtualX, drmmode_get_pitch_align(pScrn, cpp, tiling_flags)) * cpp; 2500 screen_size = RADEON_ALIGN(pScrn->virtualY, drmmode_get_height_align(pScrn, tiling_flags)) * pitch; 2501 base_align = drmmode_get_base_align(pScrn, cpp, tiling_flags); 2502 if (info->ChipFamily >= CHIP_FAMILY_R600) { 2503 if(!info->surf_man) { 2504 xf86DrvMsg(pScreen->myNum, X_ERROR, 2505 "failed to initialise surface manager\n"); 2506 return FALSE; 2507 } 2508 memset(&surface, 0, sizeof(struct radeon_surface)); 2509 surface.npix_x = pScrn->virtualX; 2510 surface.npix_y = pScrn->virtualY; 2511 surface.npix_z = 1; 2512 surface.blk_w = 1; 2513 surface.blk_h = 1; 2514 surface.blk_d = 1; 2515 surface.array_size = 1; 2516 surface.last_level = 0; 2517 surface.bpe = cpp; 2518 surface.nsamples = 1; 2519 surface.flags = RADEON_SURF_SCANOUT; 2520 /* we are requiring a recent enough libdrm version */ 2521 surface.flags |= RADEON_SURF_HAS_TILE_MODE_INDEX; 2522 surface.flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE); 2523 surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE); 2524 if (tiling_flags & RADEON_TILING_MICRO) { 2525 surface.flags = RADEON_SURF_CLR(surface.flags, MODE); 2526 surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE); 2527 } 2528 if (tiling_flags & RADEON_TILING_MACRO) { 2529 surface.flags = RADEON_SURF_CLR(surface.flags, MODE); 2530 surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE); 2531 } 2532 if (radeon_surface_best(info->surf_man, &surface)) { 2533 xf86DrvMsg(pScreen->myNum, X_ERROR, 2534 "radeon_surface_best failed\n"); 2535 return FALSE; 2536 } 2537 if (radeon_surface_init(info->surf_man, &surface)) { 2538 xf86DrvMsg(pScreen->myNum, X_ERROR, 2539 "radeon_surface_init failed\n"); 2540 return FALSE; 2541 } 2542 pitch = surface.level[0].pitch_bytes; 2543 screen_size = surface.bo_size; 2544 base_align = surface.bo_alignment; 2545 tiling_flags = 0; 2546 switch (surface.level[0].mode) { 2547 case RADEON_SURF_MODE_2D: 2548 tiling_flags |= RADEON_TILING_MACRO; 2549 tiling_flags |= surface.bankw << RADEON_TILING_EG_BANKW_SHIFT; 2550 tiling_flags |= surface.bankh << RADEON_TILING_EG_BANKH_SHIFT; 2551 tiling_flags |= surface.mtilea << RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT; 2552 if (surface.tile_split) 2553 tiling_flags |= eg_tile_split(surface.tile_split) 2554 << RADEON_TILING_EG_TILE_SPLIT_SHIFT; 2555 break; 2556 case RADEON_SURF_MODE_1D: 2557 tiling_flags |= RADEON_TILING_MICRO; 2558 break; 2559 default: 2560 break; 2561 } 2562 info->front_surface = surface; 2563 } 2564 { 2565 int cursor_size; 2566 int c; 2567 2568 cursor_size = info->cursor_w * info->cursor_h * 4; 2569 cursor_size = RADEON_ALIGN(cursor_size, RADEON_GPU_PAGE_SIZE); 2570 for (c = 0; c < xf86_config->num_crtc; c++) { 2571 /* cursor objects */ 2572 if (info->cursor_bo[c] == NULL) { 2573 info->cursor_bo[c] = radeon_bo_open(info->bufmgr, 0, 2574 cursor_size, 0, 2575 RADEON_GEM_DOMAIN_VRAM, 0); 2576 if (!info->cursor_bo[c]) { 2577 ErrorF("Failed to allocate cursor buffer memory\n"); 2578 return FALSE; 2579 } 2580 2581 if (radeon_bo_map(info->cursor_bo[c], 1)) { 2582 ErrorF("Failed to map cursor buffer memory\n"); 2583 } 2584 2585 drmmode_set_cursor(pScrn, &info->drmmode, c, info->cursor_bo[c]); 2586 } 2587 } 2588 } 2589 2590 screen_size = RADEON_ALIGN(screen_size, RADEON_GPU_PAGE_SIZE); 2591 2592 if (info->front_bo == NULL) { 2593 info->front_bo = radeon_bo_open(info->bufmgr, 0, screen_size, 2594 base_align, 2595 info->shadow_primary ? 2596 RADEON_GEM_DOMAIN_GTT : 2597 RADEON_GEM_DOMAIN_VRAM, 2598 tiling_flags ? RADEON_GEM_NO_CPU_ACCESS : 0); 2599 if (info->r600_shadow_fb == TRUE) { 2600 if (radeon_bo_map(info->front_bo, 1)) { 2601 ErrorF("Failed to map cursor buffer memory\n"); 2602 } 2603 } 2604#if X_BYTE_ORDER == X_BIG_ENDIAN 2605 switch (cpp) { 2606 case 4: 2607 tiling_flags |= RADEON_TILING_SWAP_32BIT; 2608 break; 2609 case 2: 2610 tiling_flags |= RADEON_TILING_SWAP_16BIT; 2611 break; 2612 } 2613 if (info->ChipFamily < CHIP_FAMILY_R600 && 2614 info->r600_shadow_fb && tiling_flags) 2615 tiling_flags |= RADEON_TILING_SURFACE; 2616#endif 2617 if (tiling_flags) 2618 radeon_bo_set_tiling(info->front_bo, tiling_flags, pitch); 2619 } 2620 2621 pScrn->displayWidth = pitch / cpp; 2622 2623 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Front buffer size: %dK\n", info->front_bo->size/1024); 2624 radeon_kms_update_vram_limit(pScrn, screen_size); 2625 return TRUE; 2626} 2627 2628void radeon_kms_update_vram_limit(ScrnInfoPtr pScrn, uint32_t new_fb_size) 2629{ 2630 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 2631 RADEONInfoPtr info = RADEONPTR(pScrn); 2632 uint64_t remain_size_bytes; 2633 int c; 2634 2635 for (c = 0; c < xf86_config->num_crtc; c++) { 2636 if (info->cursor_bo[c] != NULL) { 2637 new_fb_size += (64 * 4 * 64); 2638 } 2639 } 2640 2641 remain_size_bytes = info->vram_size - new_fb_size; 2642 remain_size_bytes = (remain_size_bytes / 10) * 9; 2643 if (remain_size_bytes > 0xffffffff) 2644 remain_size_bytes = 0xffffffff; 2645 radeon_cs_set_limit(info->cs, RADEON_GEM_DOMAIN_VRAM, 2646 (uint32_t)remain_size_bytes); 2647 2648 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "VRAM usage limit set to %uK\n", 2649 (uint32_t)remain_size_bytes / 1024); 2650} 2651 2652/* Used to disallow modes that are not supported by the hardware */ 2653ModeStatus RADEONValidMode(SCRN_ARG_TYPE arg, DisplayModePtr mode, 2654 Bool verbose, int flag) 2655{ 2656 SCRN_INFO_PTR(arg); 2657 RADEONInfoPtr info = RADEONPTR(pScrn); 2658 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 2659 2660 /* 2661 * RN50 has effective maximum mode bandwidth of about 300MiB/s. 2662 * XXX should really do this for all chips by properly computing 2663 * memory bandwidth and an overhead factor. 2664 */ 2665 if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2) { 2666 if (xf86ModeBandwidth(mode, pScrn->bitsPerPixel) > 300) 2667 return MODE_BANDWIDTH; 2668 } 2669 /* There are problems with double scan mode at high clocks 2670 * They're likely related PLL and display buffer settings. 2671 * Disable these modes for now. 2672 */ 2673 if (mode->Flags & V_DBLSCAN) { 2674 if ((mode->CrtcHDisplay >= 1024) || (mode->CrtcVDisplay >= 768)) 2675 return MODE_CLOCK_RANGE; 2676 } 2677 return MODE_OK; 2678} 2679