radeon_kms.c revision 5748e6ec
1/* 2 * Copyright © 2009 Red Hat, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Dave Airlie <airlied@redhat.com> 25 * 26 */ 27#ifdef HAVE_CONFIG_H 28#include "config.h" 29#endif 30 31#include <errno.h> 32#include <sys/ioctl.h> 33/* Driver data structures */ 34#include "radeon.h" 35#include "radeon_bo_helper.h" 36#include "radeon_drm_queue.h" 37#include "radeon_glamor.h" 38#include "radeon_reg.h" 39#include "radeon_probe.h" 40#include "micmap.h" 41#include "mipointrst.h" 42 43#include "radeon_version.h" 44#include "shadow.h" 45#include <xf86Priv.h> 46 47#include "atipciids.h" 48 49#if HAVE_PRESENT_H 50#include <present.h> 51#endif 52 53/* DPMS */ 54#ifdef HAVE_XEXTPROTO_71 55#include <X11/extensions/dpmsconst.h> 56#else 57#define DPMS_SERVER 58#include <X11/extensions/dpms.h> 59#endif 60 61#include <X11/extensions/damageproto.h> 62 63#include "radeon_chipinfo_gen.h" 64 65#include "radeon_bo_gem.h" 66#include "radeon_cs_gem.h" 67#include "radeon_vbo.h" 68 69static DevScreenPrivateKeyRec radeon_client_private_key; 70DevScreenPrivateKeyRec radeon_device_private_key; 71 72extern SymTabRec RADEONChipsets[]; 73static Bool radeon_setup_kernel_mem(ScreenPtr pScreen); 74 75const OptionInfoRec RADEONOptions_KMS[] = { 76 { OPTION_ACCEL, "Accel", OPTV_BOOLEAN, {0}, FALSE }, 77 { OPTION_SW_CURSOR, "SWcursor", OPTV_BOOLEAN, {0}, FALSE }, 78 { OPTION_PAGE_FLIP, "EnablePageFlip", OPTV_BOOLEAN, {0}, FALSE }, 79 { OPTION_COLOR_TILING, "ColorTiling", OPTV_BOOLEAN, {0}, FALSE }, 80 { OPTION_COLOR_TILING_2D,"ColorTiling2D", OPTV_BOOLEAN, {0}, FALSE }, 81 { OPTION_RENDER_ACCEL, "RenderAccel", OPTV_BOOLEAN, {0}, FALSE }, 82 { OPTION_SUBPIXEL_ORDER, "SubPixelOrder", OPTV_ANYSTR, {0}, FALSE }, 83#ifdef USE_GLAMOR 84 { OPTION_ACCELMETHOD, "AccelMethod", OPTV_STRING, {0}, FALSE }, 85 { OPTION_SHADOW_PRIMARY, "ShadowPrimary", OPTV_BOOLEAN, {0}, FALSE }, 86#endif 87 { OPTION_EXA_VSYNC, "EXAVSync", OPTV_BOOLEAN, {0}, FALSE }, 88 { OPTION_EXA_PIXMAPS, "EXAPixmaps", OPTV_BOOLEAN, {0}, FALSE }, 89 { OPTION_ZAPHOD_HEADS, "ZaphodHeads", OPTV_STRING, {0}, FALSE }, 90 { OPTION_SWAPBUFFERS_WAIT,"SwapbuffersWait", OPTV_BOOLEAN, {0}, FALSE }, 91 { OPTION_DELETE_DP12, "DeleteUnusedDP12Displays", OPTV_BOOLEAN, {0}, FALSE}, 92 { OPTION_DRI3, "DRI3", OPTV_BOOLEAN, {0}, FALSE }, 93 { OPTION_DRI, "DRI", OPTV_INTEGER, {0}, FALSE }, 94 { OPTION_TEAR_FREE, "TearFree", OPTV_BOOLEAN, {0}, FALSE }, 95 { -1, NULL, OPTV_NONE, {0}, FALSE } 96}; 97 98const OptionInfoRec *RADEONOptionsWeak(void) { return RADEONOptions_KMS; } 99 100void radeon_cs_flush_indirect(ScrnInfoPtr pScrn) 101{ 102 RADEONInfoPtr info = RADEONPTR(pScrn); 103 struct radeon_accel_state *accel_state; 104 int ret; 105 106 info->gpu_flushed++; 107 108#ifdef USE_GLAMOR 109 if (info->use_glamor) { 110 glamor_block_handler(pScrn->pScreen); 111 return; 112 } 113#endif 114 115 if (!info->cs->cdw) 116 return; 117 118 accel_state = info->accel_state; 119 120 /* release the current VBO so we don't block on mapping it later */ 121 if (info->accel_state->vbo.vb_offset && info->accel_state->vbo.vb_bo) { 122 radeon_vbo_put(pScrn, &info->accel_state->vbo); 123 info->accel_state->vbo.vb_start_op = -1; 124 } 125 126 /* release the current VBO so we don't block on mapping it later */ 127 if (info->accel_state->cbuf.vb_bo) { 128 radeon_vbo_put(pScrn, &info->accel_state->cbuf); 129 info->accel_state->cbuf.vb_start_op = -1; 130 } 131 132 radeon_cs_emit(info->cs); 133 radeon_cs_erase(info->cs); 134 135 if (accel_state->use_vbos) 136 radeon_vbo_flush_bos(pScrn); 137 138 ret = radeon_cs_space_check_with_bo(info->cs, 139 accel_state->vbo.vb_bo, 140 RADEON_GEM_DOMAIN_GTT, 0); 141 if (ret) 142 ErrorF("space check failed in flush\n"); 143 144 if (info->reemit_current2d && info->state_2d.op) 145 info->reemit_current2d(pScrn, info->state_2d.op); 146 147 if (info->dri2.enabled) { 148 info->accel_state->XInited3D = FALSE; 149 info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN; 150 } 151 152} 153 154void radeon_ddx_cs_start(ScrnInfoPtr pScrn, 155 int n, const char *file, 156 const char *func, int line) 157{ 158 RADEONInfoPtr info = RADEONPTR(pScrn); 159 160 if (info->cs->cdw + n > info->cs->ndw) { 161 radeon_cs_flush_indirect(pScrn); 162 163 } 164 radeon_cs_begin(info->cs, n, file, func, line); 165} 166 167 168extern _X_EXPORT int gRADEONEntityIndex; 169 170static int getRADEONEntityIndex(void) 171{ 172 return gRADEONEntityIndex; 173} 174 175 176RADEONEntPtr RADEONEntPriv(ScrnInfoPtr pScrn) 177{ 178 DevUnion *pPriv; 179 RADEONInfoPtr info = RADEONPTR(pScrn); 180 pPriv = xf86GetEntityPrivate(info->pEnt->index, 181 getRADEONEntityIndex()); 182 return pPriv->ptr; 183} 184 185/* Allocate our private RADEONInfoRec */ 186static Bool RADEONGetRec(ScrnInfoPtr pScrn) 187{ 188 if (pScrn->driverPrivate) return TRUE; 189 190 pScrn->driverPrivate = xnfcalloc(sizeof(RADEONInfoRec), 1); 191 return TRUE; 192} 193 194/* Free our private RADEONInfoRec */ 195static void RADEONFreeRec(ScrnInfoPtr pScrn) 196{ 197 DevUnion *pPriv; 198 RADEONEntPtr pRADEONEnt; 199 RADEONInfoPtr info; 200 EntityInfoPtr pEnt; 201 202 if (!pScrn) 203 return; 204 205 pEnt = xf86GetEntityInfo(pScrn->entityList[pScrn->numEntities - 1]); 206 pPriv = xf86GetEntityPrivate(pEnt->index, gRADEONEntityIndex); 207 pRADEONEnt = pPriv->ptr; 208 209 info = RADEONPTR(pScrn); 210 if (info) { 211 if (info->fbcon_pixmap) 212 pScrn->pScreen->DestroyPixmap(info->fbcon_pixmap); 213 214 if (info->accel_state) { 215 free(info->accel_state); 216 info->accel_state = NULL; 217 } 218 219#ifdef USE_GLAMOR 220 if (info->gbm) 221 gbm_device_destroy(info->gbm); 222#endif 223 224 pRADEONEnt->scrn[info->instance_id] = NULL; 225 pRADEONEnt->num_scrns--; 226 free(pScrn->driverPrivate); 227 pScrn->driverPrivate = NULL; 228 } 229 230 if (pRADEONEnt->fd > 0) { 231 DevUnion *pPriv; 232 RADEONEntPtr pRADEONEnt; 233 pPriv = xf86GetEntityPrivate(pScrn->entityList[0], 234 getRADEONEntityIndex()); 235 236 pRADEONEnt = pPriv->ptr; 237 pRADEONEnt->fd_ref--; 238 if (!pRADEONEnt->fd_ref) { 239#ifdef XF86_PDEV_SERVER_FD 240 if (!(pRADEONEnt->platform_dev && 241 pRADEONEnt->platform_dev->flags & XF86_PDEV_SERVER_FD)) 242#endif 243 drmClose(pRADEONEnt->fd); 244 free(pPriv->ptr); 245 pPriv->ptr = NULL; 246 } 247 } 248 249 free(pEnt); 250} 251 252static void * 253radeonShadowWindow(ScreenPtr screen, CARD32 row, CARD32 offset, int mode, 254 CARD32 *size, void *closure) 255{ 256 ScrnInfoPtr pScrn = xf86ScreenToScrn(screen); 257 RADEONInfoPtr info = RADEONPTR(pScrn); 258 int stride; 259 260 stride = (pScrn->displayWidth * pScrn->bitsPerPixel) / 8; 261 *size = stride; 262 263 return ((uint8_t *)info->front_buffer->bo.radeon->ptr + row * stride + offset); 264} 265 266static void 267radeonUpdatePacked(ScreenPtr pScreen, shadowBufPtr pBuf) 268{ 269 shadowUpdatePacked(pScreen, pBuf); 270} 271 272static Bool 273callback_needs_flush(RADEONInfoPtr info, struct radeon_client_priv *client_priv) 274{ 275 return (int)(client_priv->needs_flush - info->gpu_flushed) > 0; 276} 277 278static void 279radeon_event_callback(CallbackListPtr *list, 280 pointer user_data, pointer call_data) 281{ 282 EventInfoRec *eventinfo = call_data; 283 ScrnInfoPtr pScrn = user_data; 284 ScreenPtr pScreen = pScrn->pScreen; 285 struct radeon_client_priv *client_priv = 286 dixLookupScreenPrivate(&eventinfo->client->devPrivates, 287 &radeon_client_private_key, pScreen); 288 struct radeon_client_priv *server_priv = 289 dixLookupScreenPrivate(&serverClient->devPrivates, 290 &radeon_client_private_key, pScreen); 291 RADEONInfoPtr info = RADEONPTR(pScrn); 292 int i; 293 294 if (callback_needs_flush(info, client_priv) || 295 callback_needs_flush(info, server_priv)) 296 return; 297 298 /* Don't let gpu_flushed get too far ahead of needs_flush, in order 299 * to prevent false positives in callback_needs_flush() 300 */ 301 client_priv->needs_flush = info->gpu_flushed; 302 server_priv->needs_flush = info->gpu_flushed; 303 304 for (i = 0; i < eventinfo->count; i++) { 305 if (eventinfo->events[i].u.u.type == info->callback_event_type) { 306 client_priv->needs_flush++; 307 server_priv->needs_flush++; 308 return; 309 } 310 } 311} 312 313static void 314radeon_flush_callback(CallbackListPtr *list, 315 pointer user_data, pointer call_data) 316{ 317 ScrnInfoPtr pScrn = user_data; 318 ScreenPtr pScreen = pScrn->pScreen; 319 ClientPtr client = call_data ? call_data : serverClient; 320 struct radeon_client_priv *client_priv = 321 dixLookupScreenPrivate(&client->devPrivates, 322 &radeon_client_private_key, pScreen); 323 RADEONInfoPtr info = RADEONPTR(pScrn); 324 325 if (pScrn->vtSema && callback_needs_flush(info, client_priv)) 326 radeon_cs_flush_indirect(pScrn); 327} 328 329static Bool RADEONCreateScreenResources_KMS(ScreenPtr pScreen) 330{ 331 ExtensionEntry *damage_ext; 332 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); 333 RADEONInfoPtr info = RADEONPTR(pScrn); 334 PixmapPtr pixmap; 335 336 pScreen->CreateScreenResources = info->CreateScreenResources; 337 if (!(*pScreen->CreateScreenResources)(pScreen)) 338 return FALSE; 339 pScreen->CreateScreenResources = RADEONCreateScreenResources_KMS; 340 341 /* Set the RandR primary output if Xorg hasn't */ 342 if (dixPrivateKeyRegistered(rrPrivKey)) { 343 rrScrPrivPtr rrScrPriv = rrGetScrPriv(pScreen); 344 345 if (!pScreen->isGPU && !rrScrPriv->primaryOutput) { 346 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 347 348 rrScrPriv->primaryOutput = xf86_config->output[0]->randr_output; 349 RROutputChanged(rrScrPriv->primaryOutput, FALSE); 350 rrScrPriv->layoutChanged = TRUE; 351 } 352 353 drmmode_uevent_init(pScrn, &info->drmmode); 354 } 355 356 if (!drmmode_set_desired_modes(pScrn, &info->drmmode, pScreen->isGPU)) 357 return FALSE; 358 359 if (info->r600_shadow_fb) { 360 pixmap = pScreen->GetScreenPixmap(pScreen); 361 362 if (!shadowAdd(pScreen, pixmap, radeonUpdatePacked, 363 radeonShadowWindow, 0, NULL)) 364 return FALSE; 365 } 366 367 if (info->dri2.enabled || info->use_glamor) { 368 if (info->front_buffer) { 369 PixmapPtr pPix = pScreen->GetScreenPixmap(pScreen); 370 if (!radeon_set_pixmap_bo(pPix, info->front_buffer)) 371 return FALSE; 372 373 if (info->surf_man && !info->use_glamor) 374 *radeon_get_pixmap_surface(pPix) = info->front_surface; 375 } 376 } 377 378 if (info->use_glamor) 379 radeon_glamor_create_screen_resources(pScreen); 380 381 info->callback_event_type = -1; 382 if (!pScreen->isGPU && (damage_ext = CheckExtension("DAMAGE"))) { 383 info->callback_event_type = damage_ext->eventBase + XDamageNotify; 384 385 if (!AddCallback(&FlushCallback, radeon_flush_callback, pScrn)) 386 return FALSE; 387 388 if (!AddCallback(&EventCallback, radeon_event_callback, pScrn)) { 389 DeleteCallback(&FlushCallback, radeon_flush_callback, pScrn); 390 return FALSE; 391 } 392 393 if (!dixRegisterScreenPrivateKey(&radeon_client_private_key, pScreen, 394 PRIVATE_CLIENT, sizeof(struct radeon_client_priv))) { 395 DeleteCallback(&FlushCallback, radeon_flush_callback, pScrn); 396 DeleteCallback(&EventCallback, radeon_event_callback, pScrn); 397 return FALSE; 398 } 399 } 400 401 return TRUE; 402} 403 404static Bool 405radeon_scanout_extents_intersect(xf86CrtcPtr xf86_crtc, BoxPtr extents) 406{ 407 if (xf86_crtc->scrn->is_gpu) { 408 extents->x1 -= xf86_crtc->x; 409 extents->y1 -= xf86_crtc->y; 410 extents->x2 -= xf86_crtc->x; 411 extents->y2 -= xf86_crtc->y; 412 } else { 413 extents->x1 -= xf86_crtc->filter_width >> 1; 414 extents->x2 += xf86_crtc->filter_width >> 1; 415 extents->y1 -= xf86_crtc->filter_height >> 1; 416 extents->y2 += xf86_crtc->filter_height >> 1; 417 pixman_f_transform_bounds(&xf86_crtc->f_framebuffer_to_crtc, extents); 418 } 419 420 extents->x1 = max(extents->x1, 0); 421 extents->y1 = max(extents->y1, 0); 422 extents->x2 = min(extents->x2, xf86_crtc->mode.HDisplay); 423 extents->y2 = min(extents->y2, xf86_crtc->mode.VDisplay); 424 425 return (extents->x1 < extents->x2 && extents->y1 < extents->y2); 426} 427 428static RegionPtr 429transform_region(RegionPtr region, struct pict_f_transform *transform, 430 int w, int h) 431{ 432 BoxPtr boxes = RegionRects(region); 433 int nboxes = RegionNumRects(region); 434 xRectanglePtr rects = malloc(nboxes * sizeof(*rects)); 435 RegionPtr transformed; 436 int nrects = 0; 437 BoxRec box; 438 int i; 439 440 for (i = 0; i < nboxes; i++) { 441 box.x1 = boxes[i].x1; 442 box.x2 = boxes[i].x2; 443 box.y1 = boxes[i].y1; 444 box.y2 = boxes[i].y2; 445 pixman_f_transform_bounds(transform, &box); 446 447 box.x1 = max(box.x1, 0); 448 box.y1 = max(box.y1, 0); 449 box.x2 = min(box.x2, w); 450 box.y2 = min(box.y2, h); 451 if (box.x1 >= box.x2 || box.y1 >= box.y2) 452 continue; 453 454 rects[nrects].x = box.x1; 455 rects[nrects].y = box.y1; 456 rects[nrects].width = box.x2 - box.x1; 457 rects[nrects].height = box.y2 - box.y1; 458 nrects++; 459 } 460 461 transformed = RegionFromRects(nrects, rects, CT_UNSORTED); 462 free(rects); 463 return transformed; 464} 465 466static void 467radeon_sync_scanout_pixmaps(xf86CrtcPtr xf86_crtc, RegionPtr new_region, 468 int scanout_id) 469{ 470 drmmode_crtc_private_ptr drmmode_crtc = xf86_crtc->driver_private; 471 DrawablePtr dst = &drmmode_crtc->scanout[scanout_id].pixmap->drawable; 472 DrawablePtr src = &drmmode_crtc->scanout[scanout_id ^ 1].pixmap->drawable; 473 RegionPtr last_region = &drmmode_crtc->scanout_last_region; 474 ScrnInfoPtr scrn = xf86_crtc->scrn; 475 ScreenPtr pScreen = scrn->pScreen; 476 RADEONInfoPtr info = RADEONPTR(scrn); 477 RegionRec remaining; 478 RegionPtr sync_region = NULL; 479 BoxRec extents; 480 Bool force; 481 GCPtr gc; 482 483 if (RegionNil(last_region)) 484 return; 485 486 RegionNull(&remaining); 487 RegionSubtract(&remaining, last_region, new_region); 488 if (RegionNil(&remaining)) 489 goto uninit; 490 491 extents = *RegionExtents(&remaining); 492 if (!radeon_scanout_extents_intersect(xf86_crtc, &extents)) 493 goto uninit; 494 495 if (xf86_crtc->driverIsPerformingTransform) { 496 sync_region = transform_region(&remaining, 497 &xf86_crtc->f_framebuffer_to_crtc, 498 dst->width, dst->height); 499 } else { 500 sync_region = RegionDuplicate(&remaining); 501 RegionTranslate(sync_region, -xf86_crtc->x, -xf86_crtc->y); 502 } 503 504 force = info->accel_state->force; 505 info->accel_state->force = TRUE; 506 507 gc = GetScratchGC(dst->depth, pScreen); 508 if (gc) { 509 gc->funcs->ChangeClip(gc, CT_REGION, sync_region, 0); 510 ValidateGC(dst, gc); 511 sync_region = NULL; 512 gc->ops->CopyArea(src, dst, gc, 0, 0, dst->width, dst->height, 0, 0); 513 FreeScratchGC(gc); 514 } 515 516 info->accel_state->force = force; 517 518 uninit: 519 if (sync_region) 520 RegionDestroy(sync_region); 521 RegionUninit(&remaining); 522} 523 524static void 525radeon_scanout_flip_abort(xf86CrtcPtr crtc, void *event_data) 526{ 527 RADEONEntPtr pRADEONEnt = RADEONEntPriv(crtc->scrn); 528 drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; 529 struct drmmode_fb *fb = event_data; 530 531 drmmode_crtc->scanout_update_pending = 0; 532 533 if (drmmode_crtc->flip_pending == fb) { 534 drmmode_fb_reference(pRADEONEnt->fd, &drmmode_crtc->flip_pending, 535 NULL); 536 } 537} 538 539static void 540radeon_scanout_flip_handler(xf86CrtcPtr crtc, uint32_t msc, uint64_t usec, 541 void *event_data) 542{ 543 RADEONEntPtr pRADEONEnt = RADEONEntPriv(crtc->scrn); 544 drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; 545 struct drmmode_fb *fb = event_data; 546 547 drmmode_fb_reference(pRADEONEnt->fd, &drmmode_crtc->fb, fb); 548 radeon_scanout_flip_abort(crtc, event_data); 549} 550 551 552static RegionPtr 553dirty_region(PixmapDirtyUpdatePtr dirty) 554{ 555 RegionPtr damageregion = DamageRegion(dirty->damage); 556 RegionPtr dstregion; 557 558#ifdef HAS_DIRTYTRACKING_ROTATION 559 if (dirty->rotation != RR_Rotate_0) { 560 dstregion = transform_region(damageregion, 561 &dirty->f_inverse, 562 dirty->slave_dst->drawable.width, 563 dirty->slave_dst->drawable.height); 564 } else 565#endif 566 { 567 RegionRec pixregion; 568 569 dstregion = RegionDuplicate(damageregion); 570 RegionTranslate(dstregion, -dirty->x, -dirty->y); 571 PixmapRegionInit(&pixregion, dirty->slave_dst); 572 RegionIntersect(dstregion, dstregion, &pixregion); 573 RegionUninit(&pixregion); 574 } 575 576 return dstregion; 577} 578 579static void 580redisplay_dirty(PixmapDirtyUpdatePtr dirty, RegionPtr region) 581{ 582 ScrnInfoPtr src_scrn = 583 xf86ScreenToScrn(radeon_dirty_src_drawable(dirty)->pScreen); 584 585 if (RegionNil(region)) 586 goto out; 587 588 if (dirty->slave_dst->master_pixmap) 589 DamageRegionAppend(&dirty->slave_dst->drawable, region); 590 591#ifdef HAS_DIRTYTRACKING_ROTATION 592 PixmapSyncDirtyHelper(dirty); 593#else 594 PixmapSyncDirtyHelper(dirty, region); 595#endif 596 597 radeon_cs_flush_indirect(src_scrn); 598 if (dirty->slave_dst->master_pixmap) 599 DamageRegionProcessPending(&dirty->slave_dst->drawable); 600 601out: 602 DamageEmpty(dirty->damage); 603} 604 605static void 606radeon_prime_scanout_update_abort(xf86CrtcPtr crtc, void *event_data) 607{ 608 drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; 609 610 drmmode_crtc->scanout_update_pending = 0; 611} 612 613void 614radeon_sync_shared_pixmap(PixmapDirtyUpdatePtr dirty) 615{ 616 ScreenPtr master_screen = radeon_dirty_master(dirty); 617 PixmapDirtyUpdatePtr ent; 618 RegionPtr region; 619 620 xorg_list_for_each_entry(ent, &master_screen->pixmap_dirty_list, ent) { 621 if (!radeon_dirty_src_equals(dirty, ent->slave_dst)) 622 continue; 623 624 region = dirty_region(ent); 625 redisplay_dirty(ent, region); 626 RegionDestroy(region); 627 } 628} 629 630 631#if HAS_SYNC_SHARED_PIXMAP 632 633static Bool 634master_has_sync_shared_pixmap(ScrnInfoPtr scrn, PixmapDirtyUpdatePtr dirty) 635{ 636 ScreenPtr master_screen = radeon_dirty_master(dirty); 637 638 return !!master_screen->SyncSharedPixmap; 639} 640 641static Bool 642slave_has_sync_shared_pixmap(ScrnInfoPtr scrn, PixmapDirtyUpdatePtr dirty) 643{ 644 ScreenPtr slave_screen = dirty->slave_dst->drawable.pScreen; 645 646 return !!slave_screen->SyncSharedPixmap; 647} 648 649static void 650call_sync_shared_pixmap(PixmapDirtyUpdatePtr dirty) 651{ 652 ScreenPtr master_screen = radeon_dirty_master(dirty); 653 654 master_screen->SyncSharedPixmap(dirty); 655} 656 657#else /* !HAS_SYNC_SHARED_PIXMAP */ 658 659static Bool 660master_has_sync_shared_pixmap(ScrnInfoPtr scrn, PixmapDirtyUpdatePtr dirty) 661{ 662 ScrnInfoPtr master_scrn = xf86ScreenToScrn(radeon_dirty_master(dirty)); 663 664 return master_scrn->driverName == scrn->driverName; 665} 666 667static Bool 668slave_has_sync_shared_pixmap(ScrnInfoPtr scrn, PixmapDirtyUpdatePtr dirty) 669{ 670 ScrnInfoPtr slave_scrn = xf86ScreenToScrn(dirty->slave_dst->drawable.pScreen); 671 672 return slave_scrn->driverName == scrn->driverName; 673} 674 675static void 676call_sync_shared_pixmap(PixmapDirtyUpdatePtr dirty) 677{ 678 radeon_sync_shared_pixmap(dirty); 679} 680 681#endif /* HAS_SYNC_SHARED_PIXMAPS */ 682 683 684static xf86CrtcPtr 685radeon_prime_dirty_to_crtc(PixmapDirtyUpdatePtr dirty) 686{ 687 ScreenPtr screen = dirty->slave_dst->drawable.pScreen; 688 ScrnInfoPtr scrn = xf86ScreenToScrn(screen); 689 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(scrn); 690 int c; 691 692 /* Find the CRTC which is scanning out from this slave pixmap */ 693 for (c = 0; c < xf86_config->num_crtc; c++) { 694 xf86CrtcPtr xf86_crtc = xf86_config->crtc[c]; 695 drmmode_crtc_private_ptr drmmode_crtc = xf86_crtc->driver_private; 696 697 if (radeon_dirty_src_equals(dirty, drmmode_crtc->prime_scanout_pixmap)) 698 return xf86_crtc; 699 } 700 701 return NULL; 702} 703 704static Bool 705radeon_prime_scanout_do_update(xf86CrtcPtr crtc, unsigned scanout_id) 706{ 707 ScrnInfoPtr scrn = crtc->scrn; 708 ScreenPtr screen = scrn->pScreen; 709 drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; 710 PixmapDirtyUpdatePtr dirty; 711 Bool ret = FALSE; 712 713 xorg_list_for_each_entry(dirty, &screen->pixmap_dirty_list, ent) { 714 if (radeon_dirty_src_equals(dirty, drmmode_crtc->prime_scanout_pixmap)) { 715 RegionPtr region; 716 717 if (master_has_sync_shared_pixmap(scrn, dirty)) 718 call_sync_shared_pixmap(dirty); 719 720 region = dirty_region(dirty); 721 if (RegionNil(region)) 722 goto destroy; 723 724 if (drmmode_crtc->tear_free) { 725 RegionTranslate(region, crtc->x, crtc->y); 726 radeon_sync_scanout_pixmaps(crtc, region, scanout_id); 727 radeon_cs_flush_indirect(scrn); 728 RegionCopy(&drmmode_crtc->scanout_last_region, region); 729 RegionTranslate(region, -crtc->x, -crtc->y); 730 dirty->slave_dst = drmmode_crtc->scanout[scanout_id].pixmap; 731 } 732 733 redisplay_dirty(dirty, region); 734 ret = TRUE; 735 destroy: 736 RegionDestroy(region); 737 break; 738 } 739 } 740 741 return ret; 742} 743 744static void 745radeon_prime_scanout_update_handler(xf86CrtcPtr crtc, uint32_t frame, uint64_t usec, 746 void *event_data) 747{ 748 drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; 749 750 radeon_prime_scanout_do_update(crtc, 0); 751 drmmode_crtc->scanout_update_pending = 0; 752} 753 754static void 755radeon_prime_scanout_update(PixmapDirtyUpdatePtr dirty) 756{ 757 ScreenPtr screen = dirty->slave_dst->drawable.pScreen; 758 ScrnInfoPtr scrn = xf86ScreenToScrn(screen); 759 RADEONEntPtr pRADEONEnt = RADEONEntPriv(scrn); 760 xf86CrtcPtr xf86_crtc = radeon_prime_dirty_to_crtc(dirty); 761 drmmode_crtc_private_ptr drmmode_crtc; 762 uintptr_t drm_queue_seq; 763 764 if (!xf86_crtc || !xf86_crtc->enabled) 765 return; 766 767 drmmode_crtc = xf86_crtc->driver_private; 768 if (drmmode_crtc->scanout_update_pending || 769 !drmmode_crtc->scanout[drmmode_crtc->scanout_id].pixmap || 770 drmmode_crtc->dpms_mode != DPMSModeOn) 771 return; 772 773 drm_queue_seq = radeon_drm_queue_alloc(xf86_crtc, 774 RADEON_DRM_QUEUE_CLIENT_DEFAULT, 775 RADEON_DRM_QUEUE_ID_DEFAULT, NULL, 776 radeon_prime_scanout_update_handler, 777 radeon_prime_scanout_update_abort, 778 FALSE); 779 if (drm_queue_seq == RADEON_DRM_QUEUE_ERROR) { 780 xf86DrvMsg(scrn->scrnIndex, X_WARNING, 781 "radeon_drm_queue_alloc failed for PRIME update\n"); 782 radeon_prime_scanout_update_handler(xf86_crtc, 0, 0, NULL); 783 return; 784 } 785 786 drmmode_crtc->scanout_update_pending = drm_queue_seq; 787 788 if (!drmmode_wait_vblank(xf86_crtc, DRM_VBLANK_RELATIVE | DRM_VBLANK_EVENT, 789 1, drm_queue_seq, NULL, NULL)) { 790 if (!(drmmode_crtc->scanout_status & DRMMODE_SCANOUT_VBLANK_FAILED)) { 791 xf86DrvMsg(scrn->scrnIndex, X_WARNING, 792 "drmmode_wait_vblank failed for PRIME update: %s\n", 793 strerror(errno)); 794 drmmode_crtc->scanout_status |= DRMMODE_SCANOUT_VBLANK_FAILED; 795 } 796 797 drmmode_crtc->drmmode->event_context.vblank_handler(pRADEONEnt->fd, 798 0, 0, 0, 799 (void*)drm_queue_seq); 800 drmmode_crtc->wait_flip_nesting_level++; 801 radeon_drm_queue_handle_deferred(xf86_crtc); 802 return; 803 } 804 805 if (drmmode_crtc->scanout_status == 806 (DRMMODE_SCANOUT_FLIP_FAILED | DRMMODE_SCANOUT_VBLANK_FAILED)) { 807 /* The page flip and vblank ioctls failed before, but the vblank 808 * ioctl is working again, so we can try re-enabling TearFree 809 */ 810 xf86_crtc->funcs->set_mode_major(xf86_crtc, &xf86_crtc->mode, 811 xf86_crtc->rotation, 812 xf86_crtc->x, xf86_crtc->y); 813 } 814 815 drmmode_crtc->scanout_status &= ~DRMMODE_SCANOUT_VBLANK_FAILED; 816} 817 818static void 819radeon_prime_scanout_flip(PixmapDirtyUpdatePtr ent) 820{ 821 ScreenPtr screen = ent->slave_dst->drawable.pScreen; 822 ScrnInfoPtr scrn = xf86ScreenToScrn(screen); 823 RADEONEntPtr pRADEONEnt = RADEONEntPriv(scrn); 824 xf86CrtcPtr crtc = radeon_prime_dirty_to_crtc(ent); 825 drmmode_crtc_private_ptr drmmode_crtc; 826 uintptr_t drm_queue_seq; 827 unsigned scanout_id; 828 struct drmmode_fb *fb; 829 830 if (!crtc || !crtc->enabled) 831 return; 832 833 drmmode_crtc = crtc->driver_private; 834 scanout_id = drmmode_crtc->scanout_id ^ 1; 835 if (drmmode_crtc->scanout_update_pending || 836 !drmmode_crtc->scanout[scanout_id].pixmap || 837 drmmode_crtc->dpms_mode != DPMSModeOn) 838 return; 839 840 if (!radeon_prime_scanout_do_update(crtc, scanout_id)) 841 return; 842 843 fb = radeon_pixmap_get_fb(drmmode_crtc->scanout[scanout_id].pixmap); 844 if (!fb) { 845 xf86DrvMsg(scrn->scrnIndex, X_WARNING, 846 "Failed to get FB for PRIME flip.\n"); 847 return; 848 } 849 850 drm_queue_seq = radeon_drm_queue_alloc(crtc, 851 RADEON_DRM_QUEUE_CLIENT_DEFAULT, 852 RADEON_DRM_QUEUE_ID_DEFAULT, fb, 853 radeon_scanout_flip_handler, 854 radeon_scanout_flip_abort, TRUE); 855 if (drm_queue_seq == RADEON_DRM_QUEUE_ERROR) { 856 xf86DrvMsg(scrn->scrnIndex, X_WARNING, 857 "Allocating DRM event queue entry failed for PRIME flip.\n"); 858 return; 859 } 860 861 if (drmmode_page_flip_target_relative(pRADEONEnt, drmmode_crtc, 862 fb->handle, 0, drm_queue_seq, 1) 863 != 0) { 864 if (!(drmmode_crtc->scanout_status & DRMMODE_SCANOUT_FLIP_FAILED)) { 865 xf86DrvMsg(scrn->scrnIndex, X_WARNING, 866 "flip queue failed in %s: %s, TearFree inactive\n", 867 __func__, strerror(errno)); 868 drmmode_crtc->scanout_status |= DRMMODE_SCANOUT_FLIP_FAILED; 869 } 870 871 radeon_drm_abort_entry(drm_queue_seq); 872 return; 873 } 874 875 if (drmmode_crtc->scanout_status & DRMMODE_SCANOUT_FLIP_FAILED) { 876 xf86DrvMsg(scrn->scrnIndex, X_INFO, "TearFree active again\n"); 877 drmmode_crtc->scanout_status &= ~DRMMODE_SCANOUT_FLIP_FAILED; 878 } 879 880 drmmode_crtc->scanout_id = scanout_id; 881 drmmode_crtc->scanout_update_pending = drm_queue_seq; 882 drmmode_fb_reference(pRADEONEnt->fd, &drmmode_crtc->flip_pending, fb); 883} 884 885static void 886radeon_dirty_update(ScrnInfoPtr scrn) 887{ 888 ScreenPtr screen = scrn->pScreen; 889 PixmapDirtyUpdatePtr ent; 890 RegionPtr region; 891 892 xorg_list_for_each_entry(ent, &screen->pixmap_dirty_list, ent) { 893 if (screen->isGPU) { 894 PixmapDirtyUpdatePtr region_ent = ent; 895 896 if (master_has_sync_shared_pixmap(scrn, ent)) { 897 ScreenPtr master_screen = radeon_dirty_master(ent); 898 899 xorg_list_for_each_entry(region_ent, &master_screen->pixmap_dirty_list, ent) { 900 if (radeon_dirty_src_equals(ent, region_ent->slave_dst)) 901 break; 902 } 903 } 904 905 region = dirty_region(region_ent); 906 907 if (RegionNotEmpty(region)) { 908 xf86CrtcPtr crtc = radeon_prime_dirty_to_crtc(ent); 909 drmmode_crtc_private_ptr drmmode_crtc = NULL; 910 911 if (crtc) 912 drmmode_crtc = crtc->driver_private; 913 914 if (drmmode_crtc && drmmode_crtc->tear_free) 915 radeon_prime_scanout_flip(ent); 916 else 917 radeon_prime_scanout_update(ent); 918 } else { 919 DamageEmpty(region_ent->damage); 920 } 921 922 RegionDestroy(region); 923 } else { 924 if (slave_has_sync_shared_pixmap(scrn, ent)) 925 continue; 926 927 region = dirty_region(ent); 928 redisplay_dirty(ent, region); 929 RegionDestroy(region); 930 } 931 } 932} 933 934 935Bool 936radeon_scanout_do_update(xf86CrtcPtr xf86_crtc, int scanout_id, 937 PixmapPtr src_pix, BoxRec extents) 938{ 939 drmmode_crtc_private_ptr drmmode_crtc = xf86_crtc->driver_private; 940 RegionRec region = { .extents = extents, .data = NULL }; 941 ScrnInfoPtr scrn = xf86_crtc->scrn; 942 ScreenPtr pScreen = scrn->pScreen; 943 RADEONInfoPtr info = RADEONPTR(scrn); 944 DrawablePtr pDraw; 945 Bool force; 946 947 if (!xf86_crtc->enabled || 948 !drmmode_crtc->scanout[scanout_id].pixmap || 949 extents.x1 >= extents.x2 || extents.y1 >= extents.y2) 950 return FALSE; 951 952 pDraw = &drmmode_crtc->scanout[scanout_id].pixmap->drawable; 953 if (!radeon_scanout_extents_intersect(xf86_crtc, &extents)) 954 return FALSE; 955 956 if (drmmode_crtc->tear_free) { 957 radeon_sync_scanout_pixmaps(xf86_crtc, ®ion, scanout_id); 958 RegionCopy(&drmmode_crtc->scanout_last_region, ®ion); 959 } 960 961 force = info->accel_state->force; 962 info->accel_state->force = TRUE; 963 964 if (xf86_crtc->driverIsPerformingTransform) { 965 SourceValidateProcPtr SourceValidate = pScreen->SourceValidate; 966 PictFormatPtr format = PictureWindowFormat(pScreen->root); 967 int error; 968 PicturePtr src, dst; 969 970 src = CreatePicture(None, &src_pix->drawable, format, 0L, NULL, 971 serverClient, &error); 972 if (!src) { 973 ErrorF("Failed to create source picture for transformed scanout " 974 "update\n"); 975 goto out; 976 } 977 978 dst = CreatePicture(None, pDraw, format, 0L, NULL, serverClient, &error); 979 if (!dst) { 980 ErrorF("Failed to create destination picture for transformed scanout " 981 "update\n"); 982 goto free_src; 983 } 984 985 error = SetPictureTransform(src, &xf86_crtc->crtc_to_framebuffer); 986 if (error) { 987 ErrorF("SetPictureTransform failed for transformed scanout " 988 "update\n"); 989 goto free_dst; 990 } 991 992 if (xf86_crtc->filter) 993 SetPicturePictFilter(src, xf86_crtc->filter, xf86_crtc->params, 994 xf86_crtc->nparams); 995 996 pScreen->SourceValidate = NULL; 997 CompositePicture(PictOpSrc, 998 src, NULL, dst, 999 extents.x1, extents.y1, 0, 0, extents.x1, 1000 extents.y1, extents.x2 - extents.x1, 1001 extents.y2 - extents.y1); 1002 pScreen->SourceValidate = SourceValidate; 1003 1004 free_dst: 1005 FreePicture(dst, None); 1006 free_src: 1007 FreePicture(src, None); 1008 } else 1009 out: 1010 { 1011 GCPtr gc = GetScratchGC(pDraw->depth, pScreen); 1012 1013 ValidateGC(pDraw, gc); 1014 (*gc->ops->CopyArea)(&src_pix->drawable, pDraw, gc, 1015 xf86_crtc->x + extents.x1, xf86_crtc->y + extents.y1, 1016 extents.x2 - extents.x1, extents.y2 - extents.y1, 1017 extents.x1, extents.y1); 1018 FreeScratchGC(gc); 1019 } 1020 1021 info->accel_state->force = force; 1022 1023 return TRUE; 1024} 1025 1026static void 1027radeon_scanout_update_abort(xf86CrtcPtr crtc, void *event_data) 1028{ 1029 drmmode_crtc_private_ptr drmmode_crtc = event_data; 1030 1031 drmmode_crtc->scanout_update_pending = 0; 1032} 1033 1034static void 1035radeon_scanout_update_handler(xf86CrtcPtr crtc, uint32_t frame, uint64_t usec, 1036 void *event_data) 1037{ 1038 drmmode_crtc_private_ptr drmmode_crtc = event_data; 1039 ScreenPtr screen = crtc->scrn->pScreen; 1040 RegionPtr region = DamageRegion(drmmode_crtc->scanout_damage); 1041 1042 if (crtc->enabled && 1043 !drmmode_crtc->flip_pending && 1044 drmmode_crtc->dpms_mode == DPMSModeOn) { 1045 if (radeon_scanout_do_update(crtc, drmmode_crtc->scanout_id, 1046 screen->GetWindowPixmap(screen->root), 1047 region->extents)) { 1048 radeon_cs_flush_indirect(crtc->scrn); 1049 RegionEmpty(region); 1050 } 1051 } 1052 1053 radeon_scanout_update_abort(crtc, event_data); 1054} 1055 1056static void 1057radeon_scanout_update(xf86CrtcPtr xf86_crtc) 1058{ 1059 drmmode_crtc_private_ptr drmmode_crtc = xf86_crtc->driver_private; 1060 ScrnInfoPtr scrn = xf86_crtc->scrn; 1061 RADEONEntPtr pRADEONEnt = RADEONEntPriv(scrn); 1062 uintptr_t drm_queue_seq; 1063 DamagePtr pDamage; 1064 RegionPtr pRegion; 1065 BoxRec extents; 1066 1067 if (!xf86_crtc->enabled || 1068 drmmode_crtc->scanout_update_pending || 1069 drmmode_crtc->flip_pending || 1070 drmmode_crtc->dpms_mode != DPMSModeOn) 1071 return; 1072 1073 pDamage = drmmode_crtc->scanout_damage; 1074 if (!pDamage) 1075 return; 1076 1077 pRegion = DamageRegion(pDamage); 1078 if (!RegionNotEmpty(pRegion)) 1079 return; 1080 1081 extents = *RegionExtents(pRegion); 1082 if (!radeon_scanout_extents_intersect(xf86_crtc, &extents)) { 1083 RegionEmpty(pRegion); 1084 return; 1085 } 1086 1087 drm_queue_seq = radeon_drm_queue_alloc(xf86_crtc, 1088 RADEON_DRM_QUEUE_CLIENT_DEFAULT, 1089 RADEON_DRM_QUEUE_ID_DEFAULT, 1090 drmmode_crtc, 1091 radeon_scanout_update_handler, 1092 radeon_scanout_update_abort, 1093 FALSE); 1094 if (drm_queue_seq == RADEON_DRM_QUEUE_ERROR) { 1095 xf86DrvMsg(scrn->scrnIndex, X_WARNING, 1096 "radeon_drm_queue_alloc failed for scanout update\n"); 1097 radeon_scanout_update_handler(xf86_crtc, 0, 0, drmmode_crtc); 1098 return; 1099 } 1100 1101 drmmode_crtc->scanout_update_pending = drm_queue_seq; 1102 1103 if (!drmmode_wait_vblank(xf86_crtc, DRM_VBLANK_RELATIVE | DRM_VBLANK_EVENT, 1104 1, drm_queue_seq, NULL, NULL)) { 1105 if (!(drmmode_crtc->scanout_status & DRMMODE_SCANOUT_VBLANK_FAILED)) { 1106 xf86DrvMsg(scrn->scrnIndex, X_WARNING, 1107 "drmmode_wait_vblank failed for scanout update: %s\n", 1108 strerror(errno)); 1109 drmmode_crtc->scanout_status |= DRMMODE_SCANOUT_VBLANK_FAILED; 1110 } 1111 1112 drmmode_crtc->drmmode->event_context.vblank_handler(pRADEONEnt->fd, 1113 0, 0, 0, 1114 (void*)drm_queue_seq); 1115 drmmode_crtc->wait_flip_nesting_level++; 1116 radeon_drm_queue_handle_deferred(xf86_crtc); 1117 return; 1118 } 1119 1120 if (drmmode_crtc->scanout_status == 1121 (DRMMODE_SCANOUT_FLIP_FAILED | DRMMODE_SCANOUT_VBLANK_FAILED)) { 1122 /* The page flip and vblank ioctls failed before, but the vblank 1123 * ioctl is working again, so we can try re-enabling TearFree 1124 */ 1125 xf86_crtc->funcs->set_mode_major(xf86_crtc, &xf86_crtc->mode, 1126 xf86_crtc->rotation, 1127 xf86_crtc->x, xf86_crtc->y); 1128 } 1129 1130 drmmode_crtc->scanout_status &= ~DRMMODE_SCANOUT_VBLANK_FAILED; 1131} 1132 1133static void 1134radeon_scanout_flip(ScreenPtr pScreen, RADEONInfoPtr info, 1135 xf86CrtcPtr xf86_crtc) 1136{ 1137 drmmode_crtc_private_ptr drmmode_crtc = xf86_crtc->driver_private; 1138 RegionPtr region = DamageRegion(drmmode_crtc->scanout_damage); 1139 ScrnInfoPtr scrn = xf86_crtc->scrn; 1140 RADEONEntPtr pRADEONEnt = RADEONEntPriv(scrn); 1141 uintptr_t drm_queue_seq; 1142 unsigned scanout_id; 1143 struct drmmode_fb *fb; 1144 1145 if (drmmode_crtc->scanout_update_pending || 1146 drmmode_crtc->flip_pending || 1147 drmmode_crtc->dpms_mode != DPMSModeOn) 1148 return; 1149 1150 scanout_id = drmmode_crtc->scanout_id ^ 1; 1151 if (!radeon_scanout_do_update(xf86_crtc, scanout_id, 1152 pScreen->GetWindowPixmap(pScreen->root), 1153 region->extents)) 1154 return; 1155 1156 radeon_cs_flush_indirect(scrn); 1157 RegionEmpty(region); 1158 1159 fb = radeon_pixmap_get_fb(drmmode_crtc->scanout[scanout_id].pixmap); 1160 if (!fb) { 1161 xf86DrvMsg(scrn->scrnIndex, X_WARNING, 1162 "Failed to get FB for scanout flip.\n"); 1163 return; 1164 } 1165 1166 drm_queue_seq = radeon_drm_queue_alloc(xf86_crtc, 1167 RADEON_DRM_QUEUE_CLIENT_DEFAULT, 1168 RADEON_DRM_QUEUE_ID_DEFAULT, fb, 1169 radeon_scanout_flip_handler, 1170 radeon_scanout_flip_abort, TRUE); 1171 if (drm_queue_seq == RADEON_DRM_QUEUE_ERROR) { 1172 xf86DrvMsg(scrn->scrnIndex, X_WARNING, 1173 "Allocating DRM event queue entry failed.\n"); 1174 return; 1175 } 1176 1177 if (drmmode_page_flip_target_relative(pRADEONEnt, drmmode_crtc, 1178 fb->handle, 0, drm_queue_seq, 1) 1179 != 0) { 1180 if (!(drmmode_crtc->scanout_status & DRMMODE_SCANOUT_FLIP_FAILED)) { 1181 xf86DrvMsg(scrn->scrnIndex, X_WARNING, 1182 "flip queue failed in %s: %s, TearFree inactive\n", 1183 __func__, strerror(errno)); 1184 drmmode_crtc->scanout_status |= DRMMODE_SCANOUT_FLIP_FAILED; 1185 } 1186 1187 radeon_drm_abort_entry(drm_queue_seq); 1188 RegionCopy(DamageRegion(drmmode_crtc->scanout_damage), 1189 &drmmode_crtc->scanout_last_region); 1190 RegionEmpty(&drmmode_crtc->scanout_last_region); 1191 radeon_scanout_update(xf86_crtc); 1192 drmmode_crtc_scanout_destroy(drmmode_crtc->drmmode, 1193 &drmmode_crtc->scanout[scanout_id]); 1194 drmmode_crtc->tear_free = FALSE; 1195 return; 1196 } 1197 1198 if (drmmode_crtc->scanout_status & DRMMODE_SCANOUT_FLIP_FAILED) { 1199 xf86DrvMsg(scrn->scrnIndex, X_INFO, "TearFree active again\n"); 1200 drmmode_crtc->scanout_status &= ~DRMMODE_SCANOUT_FLIP_FAILED; 1201 } 1202 1203 drmmode_crtc->scanout_id = scanout_id; 1204 drmmode_crtc->scanout_update_pending = drm_queue_seq; 1205 drmmode_fb_reference(pRADEONEnt->fd, &drmmode_crtc->flip_pending, fb); 1206} 1207 1208static void RADEONBlockHandler_KMS(BLOCKHANDLER_ARGS_DECL) 1209{ 1210 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); 1211 RADEONInfoPtr info = RADEONPTR(pScrn); 1212 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 1213 int c; 1214 1215 pScreen->BlockHandler = info->BlockHandler; 1216 (*pScreen->BlockHandler) (BLOCKHANDLER_ARGS); 1217 pScreen->BlockHandler = RADEONBlockHandler_KMS; 1218 1219 if (!xf86ScreenToScrn(radeon_master_screen(pScreen))->vtSema) 1220 return; 1221 1222 if (!pScreen->isGPU) 1223 { 1224 for (c = 0; c < xf86_config->num_crtc; c++) { 1225 xf86CrtcPtr crtc = xf86_config->crtc[c]; 1226 drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; 1227 1228 if (drmmode_crtc->rotate.pixmap) 1229 continue; 1230 1231 if (drmmode_crtc->tear_free) 1232 radeon_scanout_flip(pScreen, info, crtc); 1233 else if (drmmode_crtc->scanout[drmmode_crtc->scanout_id].pixmap) 1234 radeon_scanout_update(crtc); 1235 } 1236 } 1237 1238 radeon_cs_flush_indirect(pScrn); 1239 1240 radeon_dirty_update(pScrn); 1241} 1242 1243static Bool RADEONIsFastFBWorking(ScrnInfoPtr pScrn) 1244{ 1245 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 1246 struct drm_radeon_info ginfo; 1247 int r; 1248 uint32_t tmp = 0; 1249 1250 memset(&ginfo, 0, sizeof(ginfo)); 1251 ginfo.request = RADEON_INFO_FASTFB_WORKING; 1252 ginfo.value = (uintptr_t)&tmp; 1253 r = drmCommandWriteRead(pRADEONEnt->fd, DRM_RADEON_INFO, &ginfo, sizeof(ginfo)); 1254 if (r) { 1255 return FALSE; 1256 } 1257 if (tmp == 1) 1258 return TRUE; 1259 return FALSE; 1260} 1261 1262static Bool RADEONIsFusionGARTWorking(ScrnInfoPtr pScrn) 1263{ 1264 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 1265 struct drm_radeon_info ginfo; 1266 int r; 1267 uint32_t tmp; 1268 1269 memset(&ginfo, 0, sizeof(ginfo)); 1270 ginfo.request = RADEON_INFO_FUSION_GART_WORKING; 1271 ginfo.value = (uintptr_t)&tmp; 1272 r = drmCommandWriteRead(pRADEONEnt->fd, DRM_RADEON_INFO, &ginfo, sizeof(ginfo)); 1273 if (r) { 1274 return FALSE; 1275 } 1276 if (tmp == 1) 1277 return TRUE; 1278 return FALSE; 1279} 1280 1281static Bool RADEONIsAccelWorking(ScrnInfoPtr pScrn) 1282{ 1283 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 1284 RADEONInfoPtr info = RADEONPTR(pScrn); 1285 struct drm_radeon_info ginfo; 1286 int r; 1287 uint32_t tmp; 1288 1289 memset(&ginfo, 0, sizeof(ginfo)); 1290 if (info->dri2.pKernelDRMVersion->version_minor >= 5) 1291 ginfo.request = RADEON_INFO_ACCEL_WORKING2; 1292 else 1293 ginfo.request = RADEON_INFO_ACCEL_WORKING; 1294 ginfo.value = (uintptr_t)&tmp; 1295 r = drmCommandWriteRead(pRADEONEnt->fd, DRM_RADEON_INFO, &ginfo, sizeof(ginfo)); 1296 if (r) { 1297 /* If kernel is too old before 2.6.32 than assume accel is working */ 1298 if (r == -EINVAL) { 1299 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Kernel too old missing accel " 1300 "information, assuming accel is working\n"); 1301 return TRUE; 1302 } 1303 return FALSE; 1304 } 1305 if (info->ChipFamily == CHIP_FAMILY_HAWAII) { 1306 if (tmp == 2 || tmp == 3) 1307 return TRUE; 1308 } else if (tmp) { 1309 return TRUE; 1310 } 1311 return FALSE; 1312} 1313 1314/* This is called by RADEONPreInit to set up the default visual */ 1315static Bool RADEONPreInitVisual(ScrnInfoPtr pScrn) 1316{ 1317 RADEONInfoPtr info = RADEONPTR(pScrn); 1318 1319 if (!xf86SetDepthBpp(pScrn, 0, 0, 0, Support32bppFb)) 1320 return FALSE; 1321 1322 switch (pScrn->depth) { 1323 case 8: 1324 case 15: 1325 case 16: 1326 case 24: 1327 case 30: 1328 break; 1329 1330 default: 1331 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1332 "Given depth (%d) is not supported by %s driver\n", 1333 pScrn->depth, RADEON_DRIVER_NAME); 1334 return FALSE; 1335 } 1336 1337 xf86PrintDepthBpp(pScrn); 1338 1339 info->pix24bpp = xf86GetBppFromDepth(pScrn, 1340 pScrn->depth); 1341 info->pixel_bytes = pScrn->bitsPerPixel / 8; 1342 1343 if (info->pix24bpp == 24) { 1344 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1345 "Radeon does NOT support 24bpp\n"); 1346 return FALSE; 1347 } 1348 1349 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1350 "Pixel depth = %d bits stored in %d byte%s (%d bpp pixmaps)\n", 1351 pScrn->depth, 1352 info->pixel_bytes, 1353 info->pixel_bytes > 1 ? "s" : "", 1354 info->pix24bpp); 1355 1356 if (!xf86SetDefaultVisual(pScrn, -1)) return FALSE; 1357 1358 if (pScrn->depth > 8 && pScrn->defaultVisual != TrueColor) { 1359 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1360 "Default visual (%s) is not supported at depth %d\n", 1361 xf86GetVisualName(pScrn->defaultVisual), pScrn->depth); 1362 return FALSE; 1363 } 1364 return TRUE; 1365} 1366 1367/* This is called by RADEONPreInit to handle all color weight issues */ 1368static Bool RADEONPreInitWeight(ScrnInfoPtr pScrn) 1369{ 1370 RADEONInfoPtr info = RADEONPTR(pScrn); 1371 1372 /* Save flag for 6 bit DAC to use for 1373 setting CRTC registers. Otherwise use 1374 an 8 bit DAC, even if xf86SetWeight sets 1375 pScrn->rgbBits to some value other than 1376 8. */ 1377 info->dac6bits = FALSE; 1378 1379 if (pScrn->depth > 8) { 1380 rgb defaultWeight = { 0, 0, 0 }; 1381 1382 if (!xf86SetWeight(pScrn, defaultWeight, defaultWeight)) return FALSE; 1383 } else { 1384 pScrn->rgbBits = 8; 1385 } 1386 1387 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1388 "Using %d bits per RGB (%d bit DAC)\n", 1389 pScrn->rgbBits, info->dac6bits ? 6 : 8); 1390 1391 return TRUE; 1392} 1393 1394static Bool RADEONPreInitAccel_KMS(ScrnInfoPtr pScrn) 1395{ 1396 RADEONInfoPtr info = RADEONPTR(pScrn); 1397 1398 if (!(info->accel_state = calloc(1, sizeof(struct radeon_accel_state)))) { 1399 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unable to allocate accel_state rec!\n"); 1400 return FALSE; 1401 } 1402 1403 /* Check whether direct mapping is used for fast fb access*/ 1404 if (RADEONIsFastFBWorking(pScrn)) { 1405 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct mapping of fb aperture is enabled for fast fb access.\n"); 1406 info->is_fast_fb = TRUE; 1407 } 1408 1409 if (!xf86ReturnOptValBool(info->Options, OPTION_ACCEL, TRUE) || 1410 (!RADEONIsAccelWorking(pScrn))) { 1411 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1412 "GPU accel disabled or not working, using shadowfb for KMS\n"); 1413shadowfb: 1414 if (!xf86LoadSubModule(pScrn, "shadow")) 1415 return FALSE; 1416 1417 info->r600_shadow_fb = TRUE; 1418 return TRUE; 1419 } 1420 1421#ifdef DRI2 1422 info->dri2.available = !!xf86LoadSubModule(pScrn, "dri2"); 1423#endif 1424 1425 if (radeon_glamor_pre_init(pScrn)) 1426 return TRUE; 1427 1428 if (info->ChipFamily >= CHIP_FAMILY_TAHITI) { 1429 goto shadowfb; 1430 } else if (info->ChipFamily == CHIP_FAMILY_PALM) { 1431 info->accel_state->allowHWDFS = RADEONIsFusionGARTWorking(pScrn); 1432 } else 1433 info->accel_state->allowHWDFS = TRUE; 1434 1435 if ((info->ChipFamily == CHIP_FAMILY_RS100) || 1436 (info->ChipFamily == CHIP_FAMILY_RS200) || 1437 (info->ChipFamily == CHIP_FAMILY_RS300) || 1438 (info->ChipFamily == CHIP_FAMILY_RS400) || 1439 (info->ChipFamily == CHIP_FAMILY_RS480) || 1440 (info->ChipFamily == CHIP_FAMILY_RS600) || 1441 (info->ChipFamily == CHIP_FAMILY_RS690) || 1442 (info->ChipFamily == CHIP_FAMILY_RS740)) 1443 info->accel_state->has_tcl = FALSE; 1444 else { 1445 info->accel_state->has_tcl = TRUE; 1446 } 1447 1448 { 1449 int errmaj = 0, errmin = 0; 1450 info->exaReq.majorversion = EXA_VERSION_MAJOR; 1451 info->exaReq.minorversion = EXA_VERSION_MINOR; 1452 if (!LoadSubModule(pScrn->module, "exa", NULL, NULL, NULL, 1453 &info->exaReq, &errmaj, &errmin)) { 1454 LoaderErrorMsg(NULL, "exa", errmaj, errmin); 1455 return FALSE; 1456 } 1457 } 1458 1459 return TRUE; 1460} 1461 1462static Bool RADEONPreInitChipType_KMS(ScrnInfoPtr pScrn) 1463{ 1464 RADEONInfoPtr info = RADEONPTR(pScrn); 1465 int i; 1466 1467 info->Chipset = PCI_DEV_DEVICE_ID(info->PciInfo); 1468 pScrn->chipset = (char *)xf86TokenToString(RADEONChipsets, info->Chipset); 1469 if (!pScrn->chipset) { 1470 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1471 "ChipID 0x%04x is not recognized\n", info->Chipset); 1472 return FALSE; 1473 } 1474 1475 if (info->Chipset < 0) { 1476 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1477 "Chipset \"%s\" is not recognized\n", pScrn->chipset); 1478 return FALSE; 1479 } 1480 xf86DrvMsg(pScrn->scrnIndex, X_PROBED, 1481 "Chipset: \"%s\" (ChipID = 0x%04x)\n", 1482 pScrn->chipset, 1483 info->Chipset); 1484 1485 for (i = 0; i < sizeof(RADEONCards) / sizeof(RADEONCardInfo); i++) { 1486 if (info->Chipset == RADEONCards[i].pci_device_id) { 1487 RADEONCardInfo *card = &RADEONCards[i]; 1488 info->ChipFamily = card->chip_family; 1489 break; 1490 } 1491 } 1492 1493#ifdef RENDER 1494 info->RenderAccel = xf86ReturnOptValBool(info->Options, OPTION_RENDER_ACCEL, 1495 info->Chipset != PCI_CHIP_RN50_515E && 1496 info->Chipset != PCI_CHIP_RN50_5969); 1497#endif 1498 return TRUE; 1499} 1500 1501static int radeon_get_drm_master_fd(ScrnInfoPtr pScrn) 1502{ 1503 RADEONInfoPtr info = RADEONPTR(pScrn); 1504#ifdef XF86_PDEV_SERVER_FD 1505 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 1506#endif 1507 struct pci_device *dev = info->PciInfo; 1508 char *busid; 1509 int fd; 1510 1511#ifdef XF86_PDEV_SERVER_FD 1512 if (pRADEONEnt->platform_dev) { 1513 fd = xf86_get_platform_device_int_attrib(pRADEONEnt->platform_dev, 1514 ODEV_ATTRIB_FD, -1); 1515 if (fd != -1) 1516 return fd; 1517 } 1518#endif 1519 1520 XNFasprintf(&busid, "pci:%04x:%02x:%02x.%d", 1521 dev->domain, dev->bus, dev->dev, dev->func); 1522 1523 fd = drmOpen(NULL, busid); 1524 if (fd == -1) 1525 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1526 "[drm] Failed to open DRM device for %s: %s\n", 1527 busid, strerror(errno)); 1528 1529 free(busid); 1530 return fd; 1531} 1532 1533static Bool radeon_open_drm_master(ScrnInfoPtr pScrn) 1534{ 1535 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 1536 drmSetVersion sv; 1537 int err; 1538 1539 if (pRADEONEnt->fd) { 1540 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1541 " reusing fd for second head\n"); 1542 pRADEONEnt->fd_ref++; 1543 return TRUE; 1544 } 1545 1546 pRADEONEnt->fd = radeon_get_drm_master_fd(pScrn); 1547 if (pRADEONEnt->fd == -1) 1548 return FALSE; 1549 1550 /* Check that what we opened was a master or a master-capable FD, 1551 * by setting the version of the interface we'll use to talk to it. 1552 * (see DRIOpenDRMMaster() in DRI1) 1553 */ 1554 sv.drm_di_major = 1; 1555 sv.drm_di_minor = 1; 1556 sv.drm_dd_major = -1; 1557 sv.drm_dd_minor = -1; 1558 err = drmSetInterfaceVersion(pRADEONEnt->fd, &sv); 1559 if (err != 0) { 1560 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1561 "[drm] failed to set drm interface version.\n"); 1562 drmClose(pRADEONEnt->fd); 1563 pRADEONEnt->fd = -1; 1564 1565 return FALSE; 1566 } 1567 1568 pRADEONEnt->fd_ref = 1; 1569 return TRUE; 1570} 1571 1572static Bool r600_get_tile_config(ScrnInfoPtr pScrn) 1573{ 1574 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 1575 RADEONInfoPtr info = RADEONPTR(pScrn); 1576 struct drm_radeon_info ginfo; 1577 int r; 1578 uint32_t tmp; 1579 1580 if (info->ChipFamily < CHIP_FAMILY_R600) 1581 return FALSE; 1582 1583 memset(&ginfo, 0, sizeof(ginfo)); 1584 ginfo.request = RADEON_INFO_TILING_CONFIG; 1585 ginfo.value = (uintptr_t)&tmp; 1586 r = drmCommandWriteRead(pRADEONEnt->fd, DRM_RADEON_INFO, &ginfo, sizeof(ginfo)); 1587 if (r) 1588 return FALSE; 1589 1590 info->tile_config = tmp; 1591 info->r7xx_bank_op = 0; 1592 if (info->ChipFamily >= CHIP_FAMILY_CEDAR) { 1593 if (info->dri2.pKernelDRMVersion->version_minor >= 7) { 1594 switch (info->tile_config & 0xf) { 1595 case 0: 1596 info->num_channels = 1; 1597 break; 1598 case 1: 1599 info->num_channels = 2; 1600 break; 1601 case 2: 1602 info->num_channels = 4; 1603 break; 1604 case 3: 1605 info->num_channels = 8; 1606 break; 1607 default: 1608 return FALSE; 1609 } 1610 1611 switch((info->tile_config & 0xf0) >> 4) { 1612 case 0: 1613 info->num_banks = 4; 1614 break; 1615 case 1: 1616 info->num_banks = 8; 1617 break; 1618 case 2: 1619 info->num_banks = 16; 1620 break; 1621 default: 1622 return FALSE; 1623 } 1624 1625 switch ((info->tile_config & 0xf00) >> 8) { 1626 case 0: 1627 info->group_bytes = 256; 1628 break; 1629 case 1: 1630 info->group_bytes = 512; 1631 break; 1632 default: 1633 return FALSE; 1634 } 1635 } else 1636 return FALSE; 1637 } else { 1638 switch((info->tile_config & 0xe) >> 1) { 1639 case 0: 1640 info->num_channels = 1; 1641 break; 1642 case 1: 1643 info->num_channels = 2; 1644 break; 1645 case 2: 1646 info->num_channels = 4; 1647 break; 1648 case 3: 1649 info->num_channels = 8; 1650 break; 1651 default: 1652 return FALSE; 1653 } 1654 switch((info->tile_config & 0x30) >> 4) { 1655 case 0: 1656 info->num_banks = 4; 1657 break; 1658 case 1: 1659 info->num_banks = 8; 1660 break; 1661 default: 1662 return FALSE; 1663 } 1664 switch((info->tile_config & 0xc0) >> 6) { 1665 case 0: 1666 info->group_bytes = 256; 1667 break; 1668 case 1: 1669 info->group_bytes = 512; 1670 break; 1671 default: 1672 return FALSE; 1673 } 1674 } 1675 1676 info->have_tiling_info = TRUE; 1677 return TRUE; 1678} 1679 1680static void RADEONSetupCapabilities(ScrnInfoPtr pScrn) 1681{ 1682 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 1683 RADEONInfoPtr info = RADEONPTR(pScrn); 1684 uint64_t value; 1685 int ret; 1686 1687 pScrn->capabilities = 0; 1688 1689 /* PRIME offloading requires acceleration */ 1690 if (info->r600_shadow_fb) 1691 return; 1692 1693 ret = drmGetCap(pRADEONEnt->fd, DRM_CAP_PRIME, &value); 1694 if (ret == 0) { 1695 if (value & DRM_PRIME_CAP_EXPORT) 1696 pScrn->capabilities |= RR_Capability_SourceOutput | RR_Capability_SourceOffload; 1697 if (value & DRM_PRIME_CAP_IMPORT) { 1698 pScrn->capabilities |= RR_Capability_SinkOffload; 1699 if (info->drmmode.count_crtcs) 1700 pScrn->capabilities |= RR_Capability_SinkOutput; 1701 } 1702 } 1703} 1704 1705/* When the root window is created, initialize the screen contents from 1706 * console if -background none was specified on the command line 1707 */ 1708static Bool RADEONCreateWindow_oneshot(WindowPtr pWin) 1709{ 1710 ScreenPtr pScreen = pWin->drawable.pScreen; 1711 ScrnInfoPtr pScrn; 1712 RADEONInfoPtr info; 1713 Bool ret; 1714 1715 if (pWin != pScreen->root) 1716 ErrorF("%s called for non-root window %p\n", __func__, pWin); 1717 1718 pScrn = xf86ScreenToScrn(pScreen); 1719 info = RADEONPTR(pScrn); 1720 pScreen->CreateWindow = info->CreateWindow; 1721 ret = pScreen->CreateWindow(pWin); 1722 1723 if (ret) 1724 drmmode_copy_fb(pScrn, &info->drmmode); 1725 1726 return ret; 1727} 1728 1729/* When the root window is mapped, set the initial modes */ 1730void RADEONWindowExposures_oneshot(WindowPtr pWin, RegionPtr pRegion 1731#if XORG_VERSION_CURRENT < XORG_VERSION_NUMERIC(1,16,99,901,0) 1732 , RegionPtr pBSRegion 1733#endif 1734 ) 1735{ 1736 ScreenPtr pScreen = pWin->drawable.pScreen; 1737 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); 1738 RADEONInfoPtr info = RADEONPTR(pScrn); 1739 1740 if (pWin != pScreen->root) 1741 ErrorF("%s called for non-root window %p\n", __func__, pWin); 1742 1743 pScreen->WindowExposures = info->WindowExposures; 1744#if XORG_VERSION_CURRENT < XORG_VERSION_NUMERIC(1,16,99,901,0) 1745 pScreen->WindowExposures(pWin, pRegion, pBSRegion); 1746#else 1747 pScreen->WindowExposures(pWin, pRegion); 1748#endif 1749 1750 radeon_finish(pScrn, info->front_buffer); 1751 drmmode_set_desired_modes(pScrn, &info->drmmode, TRUE); 1752} 1753 1754Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int flags) 1755{ 1756 RADEONInfoPtr info; 1757 RADEONEntPtr pRADEONEnt; 1758 MessageType from; 1759 Gamma zeros = { 0.0, 0.0, 0.0 }; 1760 uint32_t tiling = 0; 1761 int cpp; 1762 1763 if (flags & PROBE_DETECT) 1764 return TRUE; 1765 1766 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 1767 "RADEONPreInit_KMS\n"); 1768 if (pScrn->numEntities != 1) return FALSE; 1769 1770 pRADEONEnt = xf86GetEntityPrivate(pScrn->entityList[0], 1771 getRADEONEntityIndex())->ptr; 1772 if (pRADEONEnt->num_scrns == ARRAY_SIZE(pRADEONEnt->scrn)) { 1773 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1774 "Only up to %u Zaphod instances supported\n", 1775 (unsigned)ARRAY_SIZE(pRADEONEnt->scrn)); 1776 return FALSE; 1777 } 1778 1779 if (!RADEONGetRec(pScrn)) return FALSE; 1780 1781 info = RADEONPTR(pScrn); 1782 1783 info->instance_id = pRADEONEnt->num_scrns++; 1784 pRADEONEnt->scrn[info->instance_id] = pScrn; 1785 1786 info->pEnt = xf86GetEntityInfo(pScrn->entityList[pScrn->numEntities - 1]); 1787 if (info->pEnt->location.type != BUS_PCI 1788#ifdef XSERVER_PLATFORM_BUS 1789 && info->pEnt->location.type != BUS_PLATFORM 1790#endif 1791 ) 1792 return FALSE; 1793 1794 if (xf86IsEntityShared(pScrn->entityList[0]) && 1795 info->instance_id == 0) { 1796 xf86SetPrimInitDone(pScrn->entityList[0]); 1797 } 1798 1799 info->PciInfo = xf86GetPciInfoForEntity(info->pEnt->index); 1800 pScrn->monitor = pScrn->confScreen->monitor; 1801 1802 if (!RADEONPreInitVisual(pScrn)) 1803 return FALSE; 1804 1805 xf86CollectOptions(pScrn, NULL); 1806 if (!(info->Options = malloc(sizeof(RADEONOptions_KMS)))) 1807 return FALSE; 1808 1809 memcpy(info->Options, RADEONOptions_KMS, sizeof(RADEONOptions_KMS)); 1810 xf86ProcessOptions(pScrn->scrnIndex, pScrn->options, info->Options); 1811 1812 if (!RADEONPreInitWeight(pScrn)) 1813 return FALSE; 1814 1815 if (!RADEONPreInitChipType_KMS(pScrn)) 1816 return FALSE; 1817 1818 if (radeon_open_drm_master(pScrn) == FALSE) { 1819 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Kernel modesetting setup failed\n"); 1820 return FALSE; 1821 } 1822 1823 info->dri2.available = FALSE; 1824 info->dri2.enabled = FALSE; 1825 info->dri2.pKernelDRMVersion = drmGetVersion(pRADEONEnt->fd); 1826 if (!info->dri2.pKernelDRMVersion) { 1827 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1828 "RADEONDRIGetVersion failed to get the DRM version\n"); 1829 return FALSE; 1830 } 1831 1832 /* Get ScreenInit function */ 1833 if (!xf86LoadSubModule(pScrn, "fb")) 1834 return FALSE; 1835 1836 if (!RADEONPreInitAccel_KMS(pScrn)) 1837 return FALSE; 1838 1839 /* Depth 30 only supported since Linux 3.16 / kms driver minor version 39 */ 1840 if (pScrn->depth == 30 && info->dri2.pKernelDRMVersion->version_minor < 39) { 1841 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1842 "Depth 30 is not supported. Kernel too old. Needs Linux 3.16+\n"); 1843 return FALSE; 1844 } 1845 1846 radeon_drm_queue_init(pScrn); 1847 1848 info->allowColorTiling2D = FALSE; 1849 1850 /* don't enable tiling if accel is not enabled */ 1851 if (!info->r600_shadow_fb) { 1852 Bool colorTilingDefault = 1853 info->ChipFamily >= CHIP_FAMILY_R300 && 1854 /* this check could be removed sometime after a big mesa release 1855 * with proper bit, in the meantime you need to set tiling option in 1856 * xorg configuration files 1857 */ 1858 info->ChipFamily <= CHIP_FAMILY_MULLINS && 1859 !info->is_fast_fb; 1860 1861 /* 2D color tiling */ 1862 if (info->ChipFamily >= CHIP_FAMILY_R600) { 1863 info->allowColorTiling2D = xf86ReturnOptValBool(info->Options, OPTION_COLOR_TILING_2D, 1864 info->ChipFamily <= CHIP_FAMILY_MULLINS); 1865 } 1866 1867 if (info->ChipFamily >= CHIP_FAMILY_R600) { 1868 /* set default group bytes, overridden by kernel info below */ 1869 info->group_bytes = 256; 1870 info->have_tiling_info = FALSE; 1871 if (info->dri2.pKernelDRMVersion->version_minor >= 6) { 1872 if (r600_get_tile_config(pScrn)) { 1873 info->allowColorTiling = xf86ReturnOptValBool(info->Options, 1874 OPTION_COLOR_TILING, colorTilingDefault); 1875 if (!info->use_glamor) { 1876 /* need working DFS for tiling */ 1877 if (info->ChipFamily == CHIP_FAMILY_PALM && 1878 !info->accel_state->allowHWDFS) 1879 info->allowColorTiling = FALSE; 1880 } 1881 } else 1882 info->allowColorTiling = FALSE; 1883 } else 1884 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1885 "R6xx+ KMS Color Tiling requires radeon drm 2.6.0 or newer\n"); 1886 } else 1887 info->allowColorTiling = xf86ReturnOptValBool(info->Options, 1888 OPTION_COLOR_TILING, colorTilingDefault); 1889 } else 1890 info->allowColorTiling = FALSE; 1891 1892 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1893 "KMS Color Tiling: %sabled\n", info->allowColorTiling ? "en" : "dis"); 1894 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1895 "KMS Color Tiling 2D: %sabled\n", info->allowColorTiling2D ? "en" : "dis"); 1896 1897#if USE_GLAMOR 1898 if (info->use_glamor) { 1899 info->shadow_primary = xf86ReturnOptValBool(info->Options, 1900 OPTION_SHADOW_PRIMARY, FALSE); 1901 1902 if (info->shadow_primary) 1903 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "ShadowPrimary enabled\n"); 1904 } 1905#endif 1906 1907 if (!info->r600_shadow_fb) { 1908 from = X_DEFAULT; 1909 1910 info->tear_free = 2; 1911 if (xf86GetOptValBool(info->Options, OPTION_TEAR_FREE, 1912 &info->tear_free)) 1913 from = X_CONFIG; 1914 xf86DrvMsg(pScrn->scrnIndex, from, "TearFree property default: %s\n", 1915 info->tear_free == 2 ? "auto" : (info->tear_free ? "on" : "off")); 1916 } 1917 1918 if (!pScrn->is_gpu) { 1919 if (info->dri2.pKernelDRMVersion->version_minor >= 8) { 1920 info->allowPageFlip = xf86ReturnOptValBool(info->Options, 1921 OPTION_PAGE_FLIP, TRUE); 1922 1923 if (info->shadow_primary) { 1924 xf86DrvMsg(pScrn->scrnIndex, 1925 info->allowPageFlip ? X_WARNING : X_DEFAULT, 1926 "KMS Pageflipping: disabled%s\n", 1927 info->allowPageFlip ? 1928 " because of ShadowPrimary" : ""); 1929 info->allowPageFlip = FALSE; 1930 } else { 1931 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1932 "KMS Pageflipping: %sabled\n", 1933 info->allowPageFlip ? "en" : "dis"); 1934 } 1935 } 1936 1937 if (!info->use_glamor) { 1938 info->swapBuffersWait = 1939 xf86ReturnOptValBool(info->Options, OPTION_SWAPBUFFERS_WAIT, TRUE); 1940 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1941 "SwapBuffers wait for vsync: %sabled\n", 1942 info->swapBuffersWait ? "en" : "dis"); 1943 } 1944 } 1945 1946 if (xf86ReturnOptValBool(info->Options, OPTION_DELETE_DP12, FALSE)) { 1947 info->drmmode.delete_dp_12_displays = TRUE; 1948 } 1949 1950 if (drmmode_pre_init(pScrn, &info->drmmode, pScrn->bitsPerPixel / 8) == FALSE) { 1951 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Kernel modesetting setup failed\n"); 1952 return FALSE; 1953 } 1954 1955 RADEONSetupCapabilities(pScrn); 1956 1957 if (info->drmmode.count_crtcs == 1) 1958 pRADEONEnt->HasCRTC2 = FALSE; 1959 else 1960 pRADEONEnt->HasCRTC2 = TRUE; 1961 1962 1963 /* fix up cloning on rn50 cards 1964 * since they only have one crtc sometimes the xserver doesn't assign 1965 * a crtc to one of the outputs even though both outputs have common modes 1966 * which results in only one monitor being enabled. Assign a crtc here so 1967 * that both outputs light up. 1968 */ 1969 if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2) { 1970 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 1971 int i; 1972 1973 for (i = 0; i < xf86_config->num_output; i++) { 1974 xf86OutputPtr output = xf86_config->output[i]; 1975 1976 /* XXX: double check crtc mode */ 1977 if (output->probed_modes && !output->crtc) 1978 output->crtc = xf86_config->crtc[0]; 1979 } 1980 } 1981 1982 /* set cursor size */ 1983 if (info->ChipFamily >= CHIP_FAMILY_BONAIRE) { 1984 info->cursor_w = CURSOR_WIDTH_CIK; 1985 info->cursor_h = CURSOR_HEIGHT_CIK; 1986 } else { 1987 info->cursor_w = CURSOR_WIDTH; 1988 info->cursor_h = CURSOR_HEIGHT; 1989 } 1990 1991 { 1992 struct drm_radeon_gem_info mminfo; 1993 1994 if (!drmCommandWriteRead(pRADEONEnt->fd, DRM_RADEON_GEM_INFO, &mminfo, sizeof(mminfo))) 1995 { 1996 info->vram_size = mminfo.vram_visible; 1997 info->gart_size = mminfo.gart_size; 1998 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1999 "mem size init: gart size :%llx vram size: s:%llx visible:%llx\n", 2000 (unsigned long long)mminfo.gart_size, 2001 (unsigned long long)mminfo.vram_size, 2002 (unsigned long long)mminfo.vram_visible); 2003 } 2004 } 2005 2006 if (!info->use_glamor) { 2007 info->exa_pixmaps = xf86ReturnOptValBool(info->Options, 2008 OPTION_EXA_PIXMAPS, 2009 (info->vram_size > (32 * 1024 * 1024) && 2010 info->RenderAccel && 2011 !info->is_fast_fb)); 2012 if (info->exa_pixmaps) 2013 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 2014 "EXA: Driver will allow EXA pixmaps in VRAM\n"); 2015 else 2016 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 2017 "EXA: Driver will not allow EXA pixmaps in VRAM\n"); 2018 } 2019 2020 /* no tiled scanout on r6xx+ yet */ 2021 if (info->allowColorTiling) { 2022 if (info->ChipFamily >= CHIP_FAMILY_R600) 2023 tiling |= RADEON_TILING_MICRO; 2024 else 2025 tiling |= RADEON_TILING_MACRO; 2026 } 2027 cpp = pScrn->bitsPerPixel / 8; 2028 pScrn->displayWidth = 2029 RADEON_ALIGN(pScrn->virtualX, drmmode_get_pitch_align(pScrn, cpp, tiling)); 2030 2031 /* Set display resolution */ 2032 xf86SetDpi(pScrn, 0, 0); 2033 2034 if (!xf86SetGamma(pScrn, zeros)) return FALSE; 2035 2036 if (!xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) { 2037 if (!xf86LoadSubModule(pScrn, "ramdac")) return FALSE; 2038 } 2039 2040 if (!pScrn->modes 2041#ifdef XSERVER_PLATFORM_BUS 2042 && !pScrn->is_gpu 2043#endif 2044 ) { 2045 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No modes.\n"); 2046 return FALSE; 2047 } 2048 2049 return TRUE; 2050} 2051 2052static Bool RADEONCursorInit_KMS(ScreenPtr pScreen) 2053{ 2054 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); 2055 RADEONInfoPtr info = RADEONPTR(pScrn); 2056 2057 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 2058 "Initializing Cursor\n"); 2059 2060 /* Set Silken Mouse */ 2061 xf86SetSilkenMouse(pScreen); 2062 2063 /* Cursor setup */ 2064 miDCInitialize(pScreen, xf86GetPointerScreenFuncs()); 2065 2066 if (info->allowPageFlip) { 2067 miPointerScreenPtr PointPriv = 2068 dixLookupPrivate(&pScreen->devPrivates, miPointerScreenKey); 2069 2070 if (!dixRegisterScreenPrivateKey(&radeon_device_private_key, pScreen, 2071 PRIVATE_DEVICE, 2072 sizeof(struct radeon_device_priv))) { 2073 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "dixRegisterScreenPrivateKey failed\n"); 2074 return FALSE; 2075 } 2076 2077 info->SpriteFuncs = PointPriv->spriteFuncs; 2078 PointPriv->spriteFuncs = &drmmode_sprite_funcs; 2079 } 2080 2081 if (xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) 2082 return TRUE; 2083 2084 if (!xf86_cursors_init(pScreen, info->cursor_w, info->cursor_h, 2085 HARDWARE_CURSOR_TRUECOLOR_AT_8BPP | 2086 HARDWARE_CURSOR_AND_SOURCE_WITH_MASK | 2087 HARDWARE_CURSOR_SOURCE_MASK_INTERLEAVE_1 | 2088 HARDWARE_CURSOR_UPDATE_UNHIDDEN | 2089 HARDWARE_CURSOR_ARGB)) { 2090 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "xf86_cursors_init failed\n"); 2091 return FALSE; 2092 } 2093 2094 return TRUE; 2095} 2096 2097void 2098RADEONBlank(ScrnInfoPtr pScrn) 2099{ 2100 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 2101 xf86OutputPtr output; 2102 xf86CrtcPtr crtc; 2103 int o, c; 2104 2105 for (c = 0; c < xf86_config->num_crtc; c++) { 2106 crtc = xf86_config->crtc[c]; 2107 for (o = 0; o < xf86_config->num_output; o++) { 2108 output = xf86_config->output[o]; 2109 if (output->crtc != crtc) 2110 continue; 2111 2112 output->funcs->dpms(output, DPMSModeOff); 2113 } 2114 crtc->funcs->dpms(crtc, DPMSModeOff); 2115 } 2116} 2117 2118void 2119RADEONUnblank(ScrnInfoPtr pScrn) 2120{ 2121 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 2122 xf86OutputPtr output; 2123 xf86CrtcPtr crtc; 2124 int o, c; 2125 for (c = 0; c < xf86_config->num_crtc; c++) { 2126 crtc = xf86_config->crtc[c]; 2127 if(!crtc->enabled) 2128 continue; 2129 crtc->funcs->dpms(crtc, DPMSModeOn); 2130 for (o = 0; o < xf86_config->num_output; o++) { 2131 output = xf86_config->output[o]; 2132 if (output->crtc != crtc) 2133 continue; 2134 output->funcs->dpms(output, DPMSModeOn); 2135 } 2136 } 2137} 2138 2139 2140static Bool RADEONSaveScreen_KMS(ScreenPtr pScreen, int mode) 2141{ 2142 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); 2143 Bool unblank; 2144 2145 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 2146 "RADEONSaveScreen(%d)\n", mode); 2147 2148 unblank = xf86IsUnblank(mode); 2149 if (unblank) SetTimeSinceLastInputEvent(); 2150 2151 if (pScrn && pScrn->vtSema) { 2152 if (unblank) 2153 RADEONUnblank(pScrn); 2154 else 2155 RADEONBlank(pScrn); 2156 } 2157 return TRUE; 2158} 2159 2160static Bool radeon_set_drm_master(ScrnInfoPtr pScrn) 2161{ 2162 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 2163 int err; 2164 2165#ifdef XF86_PDEV_SERVER_FD 2166 if (pRADEONEnt->platform_dev && 2167 (pRADEONEnt->platform_dev->flags & XF86_PDEV_SERVER_FD)) 2168 return TRUE; 2169#endif 2170 2171 err = drmSetMaster(pRADEONEnt->fd); 2172 if (err) 2173 ErrorF("Unable to retrieve master\n"); 2174 2175 return err == 0; 2176} 2177 2178static void radeon_drop_drm_master(ScrnInfoPtr pScrn) 2179{ 2180 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 2181 2182#ifdef XF86_PDEV_SERVER_FD 2183 if (pRADEONEnt->platform_dev && 2184 (pRADEONEnt->platform_dev->flags & XF86_PDEV_SERVER_FD)) 2185 return; 2186#endif 2187 2188 drmDropMaster(pRADEONEnt->fd); 2189} 2190 2191/* Called at the end of each server generation. Restore the original 2192 * text mode, unmap video memory, and unwrap and call the saved 2193 * CloseScreen function. 2194 */ 2195static Bool RADEONCloseScreen_KMS(ScreenPtr pScreen) 2196{ 2197 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); 2198 RADEONInfoPtr info = RADEONPTR(pScrn); 2199 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 2200 2201 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 2202 "RADEONCloseScreen\n"); 2203 2204 /* Clear mask of assigned crtc's in this generation */ 2205 pRADEONEnt->assigned_crtcs = 0; 2206 2207 drmmode_uevent_fini(pScrn, &info->drmmode); 2208 radeon_drm_queue_close(pScrn); 2209 radeon_cs_flush_indirect(pScrn); 2210 2211 if (info->callback_event_type != -1) { 2212 DeleteCallback(&EventCallback, radeon_event_callback, pScrn); 2213 DeleteCallback(&FlushCallback, radeon_flush_callback, pScrn); 2214 } 2215 2216 if (info->accel_state->exa) { 2217 exaDriverFini(pScreen); 2218 free(info->accel_state->exa); 2219 info->accel_state->exa = NULL; 2220 } 2221 2222 radeon_sync_close(pScreen); 2223 2224 if (info->accel_state->use_vbos) 2225 radeon_vbo_free_lists(pScrn); 2226 2227 radeon_drop_drm_master(pScrn); 2228 2229 drmmode_fini(pScrn, &info->drmmode); 2230 if (info->dri2.enabled) 2231 radeon_dri2_close_screen(pScreen); 2232 2233 radeon_glamor_fini(pScreen); 2234 2235 pScrn->vtSema = FALSE; 2236 xf86ClearPrimInitDone(info->pEnt->index); 2237 2238 if (info->allowPageFlip) { 2239 miPointerScreenPtr PointPriv = 2240 dixLookupPrivate(&pScreen->devPrivates, miPointerScreenKey); 2241 2242 if (PointPriv->spriteFuncs == &drmmode_sprite_funcs) 2243 PointPriv->spriteFuncs = info->SpriteFuncs; 2244 } 2245 2246 pScreen->BlockHandler = info->BlockHandler; 2247 pScreen->CloseScreen = info->CloseScreen; 2248 return pScreen->CloseScreen(pScreen); 2249} 2250 2251 2252void RADEONFreeScreen_KMS(ScrnInfoPtr pScrn) 2253{ 2254 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 2255 "RADEONFreeScreen\n"); 2256 2257 RADEONFreeRec(pScrn); 2258} 2259 2260Bool RADEONScreenInit_KMS(ScreenPtr pScreen, int argc, char **argv) 2261{ 2262 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); 2263 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 2264 RADEONInfoPtr info = RADEONPTR(pScrn); 2265 int subPixelOrder = SubPixelUnknown; 2266 MessageType from; 2267 Bool value; 2268 int driLevel; 2269 const char *s; 2270 void *front_ptr; 2271 2272 pScrn->fbOffset = 0; 2273 2274 miClearVisualTypes(); 2275 if (!miSetVisualTypes(pScrn->depth, 2276 miGetDefaultVisualMask(pScrn->depth), 2277 pScrn->rgbBits, 2278 pScrn->defaultVisual)) return FALSE; 2279 miSetPixmapDepths (); 2280 2281 if (!radeon_set_drm_master(pScrn)) 2282 return FALSE; 2283 2284 info->directRenderingEnabled = FALSE; 2285 if (info->r600_shadow_fb == FALSE) 2286 info->directRenderingEnabled = radeon_dri2_screen_init(pScreen); 2287 2288 if (info->ChipFamily >= CHIP_FAMILY_R600) { 2289 info->surf_man = radeon_surface_manager_new(pRADEONEnt->fd); 2290 2291 if (!info->surf_man) { 2292 xf86DrvMsg(pScreen->myNum, X_ERROR, 2293 "Failed to initialize surface manager\n"); 2294 return FALSE; 2295 } 2296 } 2297 2298 if (!info->bufmgr) 2299 info->bufmgr = radeon_bo_manager_gem_ctor(pRADEONEnt->fd); 2300 if (!info->bufmgr) { 2301 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2302 "failed to initialise GEM buffer manager"); 2303 return FALSE; 2304 } 2305 drmmode_set_bufmgr(pScrn, &info->drmmode, info->bufmgr); 2306 2307 if (!info->csm) 2308 info->csm = radeon_cs_manager_gem_ctor(pRADEONEnt->fd); 2309 if (!info->csm) { 2310 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2311 "failed to initialise command submission manager"); 2312 return FALSE; 2313 } 2314 2315 if (!info->cs) 2316 info->cs = radeon_cs_create(info->csm, RADEON_BUFFER_SIZE/4); 2317 if (!info->cs) { 2318 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2319 "failed to initialise command submission buffer"); 2320 return FALSE; 2321 } 2322 2323 radeon_cs_set_limit(info->cs, RADEON_GEM_DOMAIN_GTT, info->gart_size); 2324 radeon_cs_space_set_flush(info->cs, (void(*)(void *))radeon_cs_flush_indirect, pScrn); 2325 2326 if (!radeon_setup_kernel_mem(pScreen)) { 2327 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "radeon_setup_kernel_mem failed\n"); 2328 return FALSE; 2329 } 2330 2331 if (!(info->front_buffer->flags & RADEON_BO_FLAGS_GBM)) 2332 front_ptr = info->front_buffer->bo.radeon->ptr; 2333 else 2334 front_ptr = NULL; 2335 2336 if (info->r600_shadow_fb) { 2337 info->fb_shadow = calloc(1, 2338 pScrn->displayWidth * pScrn->virtualY * 2339 ((pScrn->bitsPerPixel + 7) >> 3)); 2340 if (!info->fb_shadow) { 2341 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2342 "Failed to allocate shadow framebuffer\n"); 2343 return FALSE; 2344 } else { 2345 if (!fbScreenInit(pScreen, info->fb_shadow, 2346 pScrn->virtualX, pScrn->virtualY, 2347 pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth, 2348 pScrn->bitsPerPixel)) 2349 return FALSE; 2350 } 2351 } 2352 2353 if (info->r600_shadow_fb == FALSE) { 2354 /* Init fb layer */ 2355 if (!fbScreenInit(pScreen, front_ptr, 2356 pScrn->virtualX, pScrn->virtualY, 2357 pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth, 2358 pScrn->bitsPerPixel)) 2359 return FALSE; 2360 } 2361 2362 xf86SetBlackWhitePixels(pScreen); 2363 2364 if (pScrn->bitsPerPixel > 8) { 2365 VisualPtr visual; 2366 2367 visual = pScreen->visuals + pScreen->numVisuals; 2368 while (--visual >= pScreen->visuals) { 2369 if ((visual->class | DynamicClass) == DirectColor) { 2370 visual->offsetRed = pScrn->offset.red; 2371 visual->offsetGreen = pScrn->offset.green; 2372 visual->offsetBlue = pScrn->offset.blue; 2373 visual->redMask = pScrn->mask.red; 2374 visual->greenMask = pScrn->mask.green; 2375 visual->blueMask = pScrn->mask.blue; 2376 } 2377 } 2378 } 2379 2380 /* Must be after RGB order fixed */ 2381 fbPictureInit (pScreen, 0, 0); 2382 2383#ifdef RENDER 2384 if ((s = xf86GetOptValString(info->Options, OPTION_SUBPIXEL_ORDER))) { 2385 if (strcmp(s, "RGB") == 0) subPixelOrder = SubPixelHorizontalRGB; 2386 else if (strcmp(s, "BGR") == 0) subPixelOrder = SubPixelHorizontalBGR; 2387 else if (strcmp(s, "NONE") == 0) subPixelOrder = SubPixelNone; 2388 PictureSetSubpixelOrder (pScreen, subPixelOrder); 2389 } 2390#endif 2391 2392 if (!pScreen->isGPU) { 2393 if (xorgGetVersion() >= XORG_VERSION_NUMERIC(1,18,3,0,0)) 2394 value = info->use_glamor; 2395 else 2396 value = FALSE; 2397 from = X_DEFAULT; 2398 2399 if (!info->r600_shadow_fb) { 2400 if (xf86GetOptValBool(info->Options, OPTION_DRI3, &value)) 2401 from = X_CONFIG; 2402 2403 if (xf86GetOptValInteger(info->Options, OPTION_DRI, &driLevel) && 2404 (driLevel == 2 || driLevel == 3)) { 2405 from = X_CONFIG; 2406 value = driLevel == 3; 2407 } 2408 } 2409 2410 if (value) { 2411 value = radeon_sync_init(pScreen) && 2412 radeon_present_screen_init(pScreen) && 2413 radeon_dri3_screen_init(pScreen); 2414 2415 if (!value) 2416 from = X_WARNING; 2417 } 2418 2419 xf86DrvMsg(pScrn->scrnIndex, from, "DRI3 %sabled\n", value ? "en" : "dis"); 2420 } 2421 2422 pScrn->vtSema = TRUE; 2423 xf86SetBackingStore(pScreen); 2424 2425 if (info->directRenderingEnabled) { 2426 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct rendering enabled\n"); 2427 } else { 2428 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 2429 "Direct rendering disabled\n"); 2430 } 2431 2432 if (info->r600_shadow_fb) { 2433 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Acceleration disabled\n"); 2434 info->accelOn = FALSE; 2435 } else { 2436 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 2437 "Initializing Acceleration\n"); 2438 if (RADEONAccelInit(pScreen)) { 2439 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Acceleration enabled\n"); 2440 info->accelOn = TRUE; 2441 } else { 2442 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2443 "Acceleration initialization failed\n"); 2444 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Acceleration disabled\n"); 2445 info->accelOn = FALSE; 2446 } 2447 } 2448 2449 /* Init DPMS */ 2450 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 2451 "Initializing DPMS\n"); 2452 xf86DPMSInit(pScreen, xf86DPMSSet, 0); 2453 2454 if (!RADEONCursorInit_KMS(pScreen)) 2455 return FALSE; 2456 2457 /* DGA setup */ 2458#ifdef XFreeXDGA 2459 /* DGA is dangerous on kms as the base and framebuffer location may change: 2460 * http://lists.freedesktop.org/archives/xorg-devel/2009-September/002113.html 2461 */ 2462 /* xf86DiDGAInit(pScreen, info->LinearAddr + pScrn->fbOffset); */ 2463#endif 2464 if (info->r600_shadow_fb == FALSE && !pScreen->isGPU) { 2465 /* Init Xv */ 2466 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 2467 "Initializing Xv\n"); 2468 RADEONInitVideo(pScreen); 2469 } 2470 2471 if (info->r600_shadow_fb == TRUE) { 2472 if (!shadowSetup(pScreen)) { 2473 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2474 "Shadowfb initialization failed\n"); 2475 return FALSE; 2476 } 2477 } 2478 pScrn->pScreen = pScreen; 2479 2480 if (!pScreen->isGPU) { 2481 if (serverGeneration == 1 && bgNoneRoot && info->accelOn) { 2482 info->CreateWindow = pScreen->CreateWindow; 2483 pScreen->CreateWindow = RADEONCreateWindow_oneshot; 2484 } 2485 info->WindowExposures = pScreen->WindowExposures; 2486 pScreen->WindowExposures = RADEONWindowExposures_oneshot; 2487 } 2488 2489 /* Provide SaveScreen & wrap BlockHandler and CloseScreen */ 2490 /* Wrap CloseScreen */ 2491 info->CloseScreen = pScreen->CloseScreen; 2492 pScreen->CloseScreen = RADEONCloseScreen_KMS; 2493 pScreen->SaveScreen = RADEONSaveScreen_KMS; 2494 info->BlockHandler = pScreen->BlockHandler; 2495 pScreen->BlockHandler = RADEONBlockHandler_KMS; 2496 2497 info->CreateScreenResources = pScreen->CreateScreenResources; 2498 pScreen->CreateScreenResources = RADEONCreateScreenResources_KMS; 2499 2500 pScreen->StartPixmapTracking = PixmapStartDirtyTracking; 2501 pScreen->StopPixmapTracking = PixmapStopDirtyTracking; 2502#if HAS_SYNC_SHARED_PIXMAP 2503 pScreen->SyncSharedPixmap = radeon_sync_shared_pixmap; 2504#endif 2505 2506 if (!xf86CrtcScreenInit (pScreen)) 2507 return FALSE; 2508 2509 /* Wrap pointer motion to flip touch screen around */ 2510// info->PointerMoved = pScrn->PointerMoved; 2511// pScrn->PointerMoved = RADEONPointerMoved; 2512 2513 if (!drmmode_setup_colormap(pScreen, pScrn)) 2514 return FALSE; 2515 2516 /* Note unused options */ 2517 if (serverGeneration == 1) 2518 xf86ShowUnusedOptions(pScrn->scrnIndex, pScrn->options); 2519 2520 drmmode_init(pScrn, &info->drmmode); 2521 2522 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 2523 "RADEONScreenInit finished\n"); 2524 2525 info->accel_state->XInited3D = FALSE; 2526 info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN; 2527 2528 return TRUE; 2529} 2530 2531Bool RADEONEnterVT_KMS(ScrnInfoPtr pScrn) 2532{ 2533 RADEONInfoPtr info = RADEONPTR(pScrn); 2534 2535 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 2536 "RADEONEnterVT_KMS\n"); 2537 2538 radeon_set_drm_master(pScrn); 2539 2540 if (info->r600_shadow_fb) { 2541 int base_align = drmmode_get_base_align(pScrn, info->pixel_bytes, 0); 2542 struct radeon_bo *front_bo = radeon_bo_open(info->bufmgr, 0, 2543 pScrn->displayWidth * 2544 info->pixel_bytes * 2545 pScrn->virtualY, 2546 base_align, 2547 RADEON_GEM_DOMAIN_VRAM, 0); 2548 2549 if (front_bo) { 2550 if (radeon_bo_map(front_bo, 1) == 0) { 2551 memset(front_bo->ptr, 0, front_bo->size); 2552 radeon_bo_unref(info->front_buffer->bo.radeon); 2553 info->front_buffer->bo.radeon = front_bo; 2554 } else { 2555 radeon_bo_unref(front_bo); 2556 front_bo = NULL; 2557 } 2558 } 2559 2560 if (!front_bo) { 2561 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 2562 "Failed to allocate new scanout BO after VT switch, " 2563 "other DRM masters may see screen contents\n"); 2564 } 2565 } 2566 2567 info->accel_state->XInited3D = FALSE; 2568 info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN; 2569 2570 pScrn->vtSema = TRUE; 2571 2572 if (!drmmode_set_desired_modes(pScrn, &info->drmmode, TRUE)) 2573 return FALSE; 2574 2575 return TRUE; 2576} 2577 2578static 2579CARD32 cleanup_black_fb(OsTimerPtr timer, CARD32 now, pointer data) 2580{ 2581 ScreenPtr screen = data; 2582 ScrnInfoPtr scrn = xf86ScreenToScrn(screen); 2583 RADEONEntPtr pRADEONEnt = RADEONEntPriv(scrn); 2584 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(scrn); 2585 int c; 2586 2587 if (xf86ScreenToScrn(radeon_master_screen(screen))->vtSema) 2588 return 0; 2589 2590 /* Unreference the all-black FB created by RADEONLeaveVT_KMS. After 2591 * this, there should be no FB left created by this driver. 2592 */ 2593 for (c = 0; c < xf86_config->num_crtc; c++) { 2594 drmmode_crtc_private_ptr drmmode_crtc = 2595 xf86_config->crtc[c]->driver_private; 2596 2597 drmmode_fb_reference(pRADEONEnt->fd, &drmmode_crtc->fb, NULL); 2598 } 2599 2600 TimerFree(timer); 2601 return 0; 2602} 2603 2604static void 2605pixmap_unref_fb(PixmapPtr pixmap) 2606{ 2607 ScrnInfoPtr scrn = xf86ScreenToScrn(pixmap->drawable.pScreen); 2608 struct drmmode_fb **fb_ptr = radeon_pixmap_get_fb_ptr(pixmap); 2609 RADEONEntPtr pRADEONEnt = RADEONEntPriv(scrn); 2610 2611 if (fb_ptr) 2612 drmmode_fb_reference(pRADEONEnt->fd, fb_ptr, NULL); 2613} 2614 2615static void 2616client_pixmap_unref_fb(void *value, XID id, void *pScreen) 2617{ 2618 PixmapPtr pixmap = value; 2619 2620 if (pixmap->drawable.pScreen == pScreen) 2621 pixmap_unref_fb(pixmap); 2622} 2623 2624void RADEONLeaveVT_KMS(ScrnInfoPtr pScrn) 2625{ 2626 RADEONInfoPtr info = RADEONPTR(pScrn); 2627 ScreenPtr pScreen = pScrn->pScreen; 2628 2629 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 2630 "RADEONLeaveVT_KMS\n"); 2631 2632 if (!info->r600_shadow_fb) { 2633 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 2634 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 2635 struct drmmode_scanout black_scanout = { .pixmap = NULL, .bo = NULL }; 2636 xf86CrtcPtr crtc; 2637 drmmode_crtc_private_ptr drmmode_crtc; 2638 unsigned w = 0, h = 0; 2639 int i; 2640 2641 /* If we're called from CloseScreen, trying to clear the black 2642 * scanout BO will likely crash and burn 2643 */ 2644 if (!pScreen->GCperDepth[0]) 2645 goto hide_cursors; 2646 2647 /* Compute maximum scanout dimensions of active CRTCs */ 2648 for (i = 0; i < xf86_config->num_crtc; i++) { 2649 crtc = xf86_config->crtc[i]; 2650 drmmode_crtc = crtc->driver_private; 2651 2652 if (!drmmode_crtc->fb) 2653 continue; 2654 2655 w = max(w, crtc->mode.HDisplay); 2656 h = max(h, crtc->mode.VDisplay); 2657 } 2658 2659 /* Make all active CRTCs scan out from an all-black framebuffer */ 2660 if (w > 0 && h > 0) { 2661 if (drmmode_crtc_scanout_create(crtc, &black_scanout, w, h)) { 2662 struct drmmode_fb *black_fb = 2663 radeon_pixmap_get_fb(black_scanout.pixmap); 2664 2665 radeon_pixmap_clear(black_scanout.pixmap); 2666 radeon_finish(pScrn, black_scanout.bo); 2667 2668 for (i = 0; i < xf86_config->num_crtc; i++) { 2669 crtc = xf86_config->crtc[i]; 2670 drmmode_crtc = crtc->driver_private; 2671 2672 if (drmmode_crtc->fb) { 2673 if (black_fb) { 2674 drmmode_set_mode(crtc, black_fb, &crtc->mode, 0, 0); 2675 } else { 2676 drmModeSetCrtc(pRADEONEnt->fd, 2677 drmmode_crtc->mode_crtc->crtc_id, 0, 2678 0, 0, NULL, 0, NULL); 2679 drmmode_fb_reference(pRADEONEnt->fd, 2680 &drmmode_crtc->fb, NULL); 2681 } 2682 2683 if (pScrn->is_gpu) { 2684 if (drmmode_crtc->scanout[0].pixmap) 2685 pixmap_unref_fb(drmmode_crtc->scanout[0].pixmap); 2686 if (drmmode_crtc->scanout[1].pixmap) 2687 pixmap_unref_fb(drmmode_crtc->scanout[1].pixmap); 2688 } else { 2689 drmmode_crtc_scanout_free(crtc); 2690 } 2691 } 2692 } 2693 } 2694 } 2695 2696 xf86RotateFreeShadow(pScrn); 2697 drmmode_crtc_scanout_destroy(&info->drmmode, &black_scanout); 2698 2699 /* Unreference FBs of all pixmaps. After this, the only FB remaining 2700 * should be the all-black one being scanned out by active CRTCs 2701 */ 2702 for (i = 0; i < currentMaxClients; i++) { 2703 if (i > 0 && 2704 (!clients[i] || clients[i]->clientState != ClientStateRunning)) 2705 continue; 2706 2707 FindClientResourcesByType(clients[i], RT_PIXMAP, 2708 client_pixmap_unref_fb, pScreen); 2709 } 2710 2711 pixmap_unref_fb(pScreen->GetScreenPixmap(pScreen)); 2712 } else { 2713 memset(info->front_buffer->bo.radeon->ptr, 0, 2714 pScrn->displayWidth * info->pixel_bytes * pScrn->virtualY); 2715 } 2716 2717 if (pScreen->GCperDepth[0]) 2718 TimerSet(NULL, 0, 1000, cleanup_black_fb, pScreen); 2719 2720 hide_cursors: 2721 xf86_hide_cursors (pScrn); 2722 2723 radeon_drop_drm_master(pScrn); 2724 2725 info->accel_state->XInited3D = FALSE; 2726 info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN; 2727 2728 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 2729 "Ok, leaving now...\n"); 2730} 2731 2732 2733Bool RADEONSwitchMode_KMS(ScrnInfoPtr pScrn, DisplayModePtr mode) 2734{ 2735 Bool ret; 2736 ret = xf86SetSingleMode (pScrn, mode, RR_Rotate_0); 2737 return ret; 2738 2739} 2740 2741void RADEONAdjustFrame_KMS(ScrnInfoPtr pScrn, int x, int y) 2742{ 2743 RADEONInfoPtr info = RADEONPTR(pScrn); 2744 drmmode_adjust_frame(pScrn, &info->drmmode, x, y); 2745 return; 2746} 2747 2748static Bool radeon_setup_kernel_mem(ScreenPtr pScreen) 2749{ 2750 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); 2751 RADEONInfoPtr info = RADEONPTR(pScrn); 2752 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 2753 int cpp = info->pixel_bytes; 2754 int pitch; 2755 uint32_t tiling_flags = 0; 2756 2757 if (info->accel_state->exa) { 2758 xf86DrvMsg(pScreen->myNum, X_ERROR, "Memory map already initialized\n"); 2759 return FALSE; 2760 } 2761 if (!info->use_glamor && info->r600_shadow_fb == FALSE) { 2762 info->accel_state->exa = exaDriverAlloc(); 2763 if (!info->accel_state->exa) { 2764 xf86DrvMsg(pScreen->myNum, X_ERROR, "exaDriverAlloc failed\n"); 2765 return FALSE; 2766 } 2767 } 2768 2769 { 2770 int cursor_size; 2771 int c, i; 2772 2773 cursor_size = info->cursor_w * info->cursor_h * 4; 2774 cursor_size = RADEON_ALIGN(cursor_size, RADEON_GPU_PAGE_SIZE); 2775 for (c = 0; c < xf86_config->num_crtc; c++) { 2776 drmmode_crtc_private_ptr drmmode_crtc = xf86_config->crtc[c]->driver_private; 2777 2778 for (i = 0; i < 2; i++) { 2779 if (!drmmode_crtc->cursor_bo[i]) { 2780 drmmode_crtc->cursor_bo[i] = 2781 radeon_bo_open(info->bufmgr, 0, cursor_size, 0, 2782 RADEON_GEM_DOMAIN_VRAM, 0); 2783 2784 if (!(drmmode_crtc->cursor_bo[i])) { 2785 ErrorF("Failed to allocate cursor buffer memory\n"); 2786 return FALSE; 2787 } 2788 2789 if (radeon_bo_map(drmmode_crtc->cursor_bo[i], 1)) 2790 ErrorF("Failed to map cursor buffer memory\n"); 2791 } 2792 } 2793 } 2794 } 2795 2796 if (!info->front_buffer) { 2797 int usage = CREATE_PIXMAP_USAGE_BACKING_PIXMAP; 2798 2799 if (info->allowColorTiling && !info->shadow_primary) { 2800 if (info->ChipFamily < CHIP_FAMILY_R600 || info->allowColorTiling2D) 2801 usage |= RADEON_CREATE_PIXMAP_TILING_MACRO; 2802 else 2803 usage |= RADEON_CREATE_PIXMAP_TILING_MICRO; 2804 } 2805 2806 info->front_buffer = radeon_alloc_pixmap_bo(pScrn, pScrn->virtualX, 2807 pScrn->virtualY, 2808 pScrn->depth, 2809 usage, 2810 pScrn->bitsPerPixel, 2811 &pitch, 2812 &info->front_surface, 2813 &tiling_flags); 2814 2815 if (info->r600_shadow_fb == TRUE) { 2816 if (radeon_bo_map(info->front_buffer->bo.radeon, 1)) { 2817 ErrorF("Failed to map cursor buffer memory\n"); 2818 } 2819 } 2820 2821 if (!info->use_glamor) { 2822#if X_BYTE_ORDER == X_BIG_ENDIAN 2823 switch (cpp) { 2824 case 4: 2825 tiling_flags |= RADEON_TILING_SWAP_32BIT; 2826 break; 2827 case 2: 2828 tiling_flags |= RADEON_TILING_SWAP_16BIT; 2829 break; 2830 } 2831 if (info->ChipFamily < CHIP_FAMILY_R600 && 2832 info->r600_shadow_fb && tiling_flags) 2833 tiling_flags |= RADEON_TILING_SURFACE; 2834#endif 2835 if (tiling_flags) 2836 radeon_bo_set_tiling(info->front_buffer->bo.radeon, tiling_flags, pitch); 2837 } 2838 2839 pScrn->displayWidth = pitch / cpp; 2840 } 2841 2842 pitch = pScrn->displayWidth * cpp; 2843 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Front buffer size: %dK\n", 2844 pitch * pScrn->virtualY / 1024); 2845 radeon_kms_update_vram_limit(pScrn, pitch * pScrn->virtualY); 2846 return TRUE; 2847} 2848 2849void radeon_kms_update_vram_limit(ScrnInfoPtr pScrn, uint32_t new_fb_size) 2850{ 2851 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 2852 RADEONInfoPtr info = RADEONPTR(pScrn); 2853 uint64_t remain_size_bytes; 2854 int c; 2855 2856 for (c = 0; c < xf86_config->num_crtc; c++) { 2857 drmmode_crtc_private_ptr drmmode_crtc = xf86_config->crtc[c]->driver_private; 2858 2859 if (drmmode_crtc->cursor_bo[0]) 2860 new_fb_size += (64 * 4 * 64); 2861 } 2862 2863 remain_size_bytes = info->vram_size - new_fb_size; 2864 remain_size_bytes = (remain_size_bytes / 10) * 9; 2865 if (remain_size_bytes > 0xffffffff) 2866 remain_size_bytes = 0xffffffff; 2867 radeon_cs_set_limit(info->cs, RADEON_GEM_DOMAIN_VRAM, 2868 (uint32_t)remain_size_bytes); 2869 2870 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "VRAM usage limit set to %uK\n", 2871 (uint32_t)remain_size_bytes / 1024); 2872} 2873 2874/* Used to disallow modes that are not supported by the hardware */ 2875ModeStatus RADEONValidMode(ScrnInfoPtr pScrn, DisplayModePtr mode, 2876 Bool verbose, int flag) 2877{ 2878 RADEONInfoPtr info = RADEONPTR(pScrn); 2879 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 2880 2881 /* 2882 * RN50 has effective maximum mode bandwidth of about 300MiB/s. 2883 * XXX should really do this for all chips by properly computing 2884 * memory bandwidth and an overhead factor. 2885 */ 2886 if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2) { 2887 if (xf86ModeBandwidth(mode, pScrn->bitsPerPixel) > 300) 2888 return MODE_BANDWIDTH; 2889 } 2890 /* There are problems with double scan mode at high clocks 2891 * They're likely related PLL and display buffer settings. 2892 * Disable these modes for now. 2893 */ 2894 if (mode->Flags & V_DBLSCAN) { 2895 if ((mode->CrtcHDisplay >= 1024) || (mode->CrtcVDisplay >= 768)) 2896 return MODE_CLOCK_RANGE; 2897 } 2898 return MODE_OK; 2899} 2900