radeon_kms.c revision 5f74fd6d
1/* 2 * Copyright © 2009 Red Hat, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Dave Airlie <airlied@redhat.com> 25 * 26 */ 27#ifdef HAVE_CONFIG_H 28#include "config.h" 29#endif 30 31#include <errno.h> 32#include <sys/ioctl.h> 33/* Driver data structures */ 34#include "radeon.h" 35#include "radeon_reg.h" 36#include "radeon_probe.h" 37#include "micmap.h" 38 39#include "radeon_version.h" 40#include "shadow.h" 41 42#include "atipciids.h" 43 44/* DPMS */ 45#ifdef HAVE_XEXTPROTO_71 46#include <X11/extensions/dpmsconst.h> 47#else 48#define DPMS_SERVER 49#include <X11/extensions/dpms.h> 50#endif 51 52#include "radeon_chipinfo_gen.h" 53 54#include "radeon_bo_gem.h" 55#include "radeon_cs_gem.h" 56#include "radeon_vbo.h" 57 58extern SymTabRec RADEONChipsets[]; 59static Bool radeon_setup_kernel_mem(ScreenPtr pScreen); 60 61const OptionInfoRec RADEONOptions_KMS[] = { 62 { OPTION_ACCEL, "Accel", OPTV_BOOLEAN, {0}, FALSE }, 63 { OPTION_SW_CURSOR, "SWcursor", OPTV_BOOLEAN, {0}, FALSE }, 64 { OPTION_PAGE_FLIP, "EnablePageFlip", OPTV_BOOLEAN, {0}, FALSE }, 65 { OPTION_COLOR_TILING, "ColorTiling", OPTV_BOOLEAN, {0}, FALSE }, 66 { OPTION_COLOR_TILING_2D,"ColorTiling2D", OPTV_BOOLEAN, {0}, FALSE }, 67 { OPTION_RENDER_ACCEL, "RenderAccel", OPTV_BOOLEAN, {0}, FALSE }, 68 { OPTION_SUBPIXEL_ORDER, "SubPixelOrder", OPTV_ANYSTR, {0}, FALSE }, 69#ifdef USE_GLAMOR 70 { OPTION_ACCELMETHOD, "AccelMethod", OPTV_STRING, {0}, FALSE }, 71#endif 72 { OPTION_EXA_VSYNC, "EXAVSync", OPTV_BOOLEAN, {0}, FALSE }, 73 { OPTION_EXA_PIXMAPS, "EXAPixmaps", OPTV_BOOLEAN, {0}, FALSE }, 74 { OPTION_ZAPHOD_HEADS, "ZaphodHeads", OPTV_STRING, {0}, FALSE }, 75 { OPTION_PAGE_FLIP, "EnablePageFlip", OPTV_BOOLEAN, {0}, FALSE }, 76 { OPTION_SWAPBUFFERS_WAIT,"SwapbuffersWait", OPTV_BOOLEAN, {0}, FALSE }, 77 { -1, NULL, OPTV_NONE, {0}, FALSE } 78}; 79 80const OptionInfoRec *RADEONOptionsWeak(void) { return RADEONOptions_KMS; } 81 82void radeon_cs_flush_indirect(ScrnInfoPtr pScrn) 83{ 84 RADEONInfoPtr info = RADEONPTR(pScrn); 85 struct radeon_accel_state *accel_state = info->accel_state; 86 int ret; 87 88 if (!info->cs->cdw) 89 return; 90 91 /* release the current VBO so we don't block on mapping it later */ 92 if (info->accel_state->vbo.vb_offset && info->accel_state->vbo.vb_bo) { 93 radeon_vbo_put(pScrn, &info->accel_state->vbo); 94 info->accel_state->vbo.vb_start_op = -1; 95 } 96 97 /* release the current VBO so we don't block on mapping it later */ 98 if (info->accel_state->cbuf.vb_bo) { 99 radeon_vbo_put(pScrn, &info->accel_state->cbuf); 100 info->accel_state->cbuf.vb_start_op = -1; 101 } 102 103 radeon_cs_emit(info->cs); 104 radeon_cs_erase(info->cs); 105 106 if (accel_state->use_vbos) 107 radeon_vbo_flush_bos(pScrn); 108 109 ret = radeon_cs_space_check_with_bo(info->cs, 110 accel_state->vbo.vb_bo, 111 RADEON_GEM_DOMAIN_GTT, 0); 112 if (ret) 113 ErrorF("space check failed in flush\n"); 114 115 if (info->reemit_current2d && info->state_2d.op) 116 info->reemit_current2d(pScrn, info->state_2d.op); 117 118 if (info->dri2.enabled) { 119 info->accel_state->XInited3D = FALSE; 120 info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN; 121 } 122 123} 124 125void radeon_ddx_cs_start(ScrnInfoPtr pScrn, 126 int n, const char *file, 127 const char *func, int line) 128{ 129 RADEONInfoPtr info = RADEONPTR(pScrn); 130 131 if (info->cs->cdw + n > info->cs->ndw) { 132 radeon_cs_flush_indirect(pScrn); 133 134 } 135 radeon_cs_begin(info->cs, n, file, func, line); 136} 137 138 139extern _X_EXPORT int gRADEONEntityIndex; 140 141static int getRADEONEntityIndex(void) 142{ 143 return gRADEONEntityIndex; 144} 145 146 147RADEONEntPtr RADEONEntPriv(ScrnInfoPtr pScrn) 148{ 149 DevUnion *pPriv; 150 RADEONInfoPtr info = RADEONPTR(pScrn); 151 pPriv = xf86GetEntityPrivate(info->pEnt->index, 152 getRADEONEntityIndex()); 153 return pPriv->ptr; 154} 155 156/* Allocate our private RADEONInfoRec */ 157static Bool RADEONGetRec(ScrnInfoPtr pScrn) 158{ 159 if (pScrn->driverPrivate) return TRUE; 160 161 pScrn->driverPrivate = xnfcalloc(sizeof(RADEONInfoRec), 1); 162 return TRUE; 163} 164 165/* Free our private RADEONInfoRec */ 166static void RADEONFreeRec(ScrnInfoPtr pScrn) 167{ 168 RADEONInfoPtr info; 169 170 if (!pScrn || !pScrn->driverPrivate) return; 171 172 info = RADEONPTR(pScrn); 173 174 if (info->dri2.drm_fd > 0) { 175 DevUnion *pPriv; 176 RADEONEntPtr pRADEONEnt; 177 pPriv = xf86GetEntityPrivate(pScrn->entityList[0], 178 getRADEONEntityIndex()); 179 180 pRADEONEnt = pPriv->ptr; 181 pRADEONEnt->fd_ref--; 182 if (!pRADEONEnt->fd_ref) { 183#ifdef XF86_PDEV_SERVER_FD 184 if (!(pRADEONEnt->platform_dev && 185 pRADEONEnt->platform_dev->flags & XF86_PDEV_SERVER_FD)) 186#endif 187 drmClose(pRADEONEnt->fd); 188 pRADEONEnt->fd = 0; 189 } 190 } 191 192 if (info->accel_state) { 193 free(info->accel_state); 194 info->accel_state = NULL; 195 } 196 197 free(pScrn->driverPrivate); 198 pScrn->driverPrivate = NULL; 199} 200 201static void * 202radeonShadowWindow(ScreenPtr screen, CARD32 row, CARD32 offset, int mode, 203 CARD32 *size, void *closure) 204{ 205 ScrnInfoPtr pScrn = xf86ScreenToScrn(screen); 206 RADEONInfoPtr info = RADEONPTR(pScrn); 207 int stride; 208 209 stride = (pScrn->displayWidth * pScrn->bitsPerPixel) / 8; 210 *size = stride; 211 212 return ((uint8_t *)info->front_bo->ptr + row * stride + offset); 213} 214 215static void 216radeonUpdatePacked(ScreenPtr pScreen, shadowBufPtr pBuf) 217{ 218 shadowUpdatePacked(pScreen, pBuf); 219} 220 221static Bool RADEONCreateScreenResources_KMS(ScreenPtr pScreen) 222{ 223 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); 224 RADEONInfoPtr info = RADEONPTR(pScrn); 225 PixmapPtr pixmap; 226 struct radeon_surface *surface; 227 228 pScreen->CreateScreenResources = info->CreateScreenResources; 229 if (!(*pScreen->CreateScreenResources)(pScreen)) 230 return FALSE; 231 pScreen->CreateScreenResources = RADEONCreateScreenResources_KMS; 232 233 if (!drmmode_set_desired_modes(pScrn, &info->drmmode)) 234 return FALSE; 235 236 drmmode_uevent_init(pScrn, &info->drmmode); 237 238 if (info->r600_shadow_fb) { 239 pixmap = pScreen->GetScreenPixmap(pScreen); 240 241 if (!shadowAdd(pScreen, pixmap, radeonUpdatePacked, 242 radeonShadowWindow, 0, NULL)) 243 return FALSE; 244 } 245 246 if (info->dri2.enabled || info->use_glamor) { 247 if (info->front_bo) { 248 PixmapPtr pPix = pScreen->GetScreenPixmap(pScreen); 249 radeon_set_pixmap_bo(pPix, info->front_bo); 250 surface = radeon_get_pixmap_surface(pPix); 251 if (surface) { 252 *surface = info->front_surface; 253 } 254 } 255 } 256 257 if (info->use_glamor) 258 radeon_glamor_create_screen_resources(pScreen); 259 260 return TRUE; 261} 262 263#ifdef RADEON_PIXMAP_SHARING 264static void 265redisplay_dirty(ScreenPtr screen, PixmapDirtyUpdatePtr dirty) 266{ 267 ScrnInfoPtr pScrn = xf86ScreenToScrn(screen); 268 RegionRec pixregion; 269 270 PixmapRegionInit(&pixregion, dirty->slave_dst); 271 DamageRegionAppend(&dirty->slave_dst->drawable, &pixregion); 272#ifdef HAS_DIRTYTRACKING_ROTATION 273 PixmapSyncDirtyHelper(dirty); 274#else 275 PixmapSyncDirtyHelper(dirty, &pixregion); 276#endif 277 278 radeon_cs_flush_indirect(pScrn); 279 DamageRegionProcessPending(&dirty->slave_dst->drawable); 280 RegionUninit(&pixregion); 281} 282 283static void 284radeon_dirty_update(ScreenPtr screen) 285{ 286 RegionPtr region; 287 PixmapDirtyUpdatePtr ent; 288 289 if (xorg_list_is_empty(&screen->pixmap_dirty_list)) 290 return; 291 292 xorg_list_for_each_entry(ent, &screen->pixmap_dirty_list, ent) { 293 region = DamageRegion(ent->damage); 294 if (RegionNotEmpty(region)) { 295 redisplay_dirty(screen, ent); 296 DamageEmpty(ent->damage); 297 } 298 } 299} 300#endif 301 302static void RADEONBlockHandler_KMS(BLOCKHANDLER_ARGS_DECL) 303{ 304 SCREEN_PTR(arg); 305 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); 306 RADEONInfoPtr info = RADEONPTR(pScrn); 307 308 pScreen->BlockHandler = info->BlockHandler; 309 (*pScreen->BlockHandler) (BLOCKHANDLER_ARGS); 310 pScreen->BlockHandler = RADEONBlockHandler_KMS; 311 312 if (info->use_glamor) 313 radeon_glamor_flush(pScrn); 314 315 radeon_cs_flush_indirect(pScrn); 316#ifdef RADEON_PIXMAP_SHARING 317 radeon_dirty_update(pScreen); 318#endif 319} 320 321static void 322radeon_flush_callback(CallbackListPtr *list, 323 pointer user_data, pointer call_data) 324{ 325 ScrnInfoPtr pScrn = user_data; 326 327 if (pScrn->vtSema) { 328 radeon_cs_flush_indirect(pScrn); 329 radeon_glamor_flush(pScrn); 330 } 331} 332 333static Bool RADEONIsFastFBWorking(ScrnInfoPtr pScrn) 334{ 335 RADEONInfoPtr info = RADEONPTR(pScrn); 336 struct drm_radeon_info ginfo; 337 int r; 338 uint32_t tmp = 0; 339 340 memset(&ginfo, 0, sizeof(ginfo)); 341 ginfo.request = RADEON_INFO_FASTFB_WORKING; 342 ginfo.value = (uintptr_t)&tmp; 343 r = drmCommandWriteRead(info->dri2.drm_fd, DRM_RADEON_INFO, &ginfo, sizeof(ginfo)); 344 if (r) { 345 return FALSE; 346 } 347 if (tmp == 1) 348 return TRUE; 349 return FALSE; 350} 351 352static Bool RADEONIsFusionGARTWorking(ScrnInfoPtr pScrn) 353{ 354 RADEONInfoPtr info = RADEONPTR(pScrn); 355 struct drm_radeon_info ginfo; 356 int r; 357 uint32_t tmp; 358 359 memset(&ginfo, 0, sizeof(ginfo)); 360 ginfo.request = RADEON_INFO_FUSION_GART_WORKING; 361 ginfo.value = (uintptr_t)&tmp; 362 r = drmCommandWriteRead(info->dri2.drm_fd, DRM_RADEON_INFO, &ginfo, sizeof(ginfo)); 363 if (r) { 364 return FALSE; 365 } 366 if (tmp == 1) 367 return TRUE; 368 return FALSE; 369} 370 371static Bool RADEONIsAccelWorking(ScrnInfoPtr pScrn) 372{ 373 RADEONInfoPtr info = RADEONPTR(pScrn); 374 struct drm_radeon_info ginfo; 375 int r; 376 uint32_t tmp; 377 378 memset(&ginfo, 0, sizeof(ginfo)); 379 if (info->dri2.pKernelDRMVersion->version_minor >= 5) 380 ginfo.request = RADEON_INFO_ACCEL_WORKING2; 381 else 382 ginfo.request = RADEON_INFO_ACCEL_WORKING; 383 ginfo.value = (uintptr_t)&tmp; 384 r = drmCommandWriteRead(info->dri2.drm_fd, DRM_RADEON_INFO, &ginfo, sizeof(ginfo)); 385 if (r) { 386 /* If kernel is too old before 2.6.32 than assume accel is working */ 387 if (r == -EINVAL) { 388 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Kernel too old missing accel " 389 "information, assuming accel is working\n"); 390 return TRUE; 391 } 392 return FALSE; 393 } 394 if (info->ChipFamily == CHIP_FAMILY_HAWAII) { 395 if (tmp == 2 || tmp == 3) 396 return TRUE; 397 } else if (tmp) { 398 return TRUE; 399 } 400 return FALSE; 401} 402 403/* This is called by RADEONPreInit to set up the default visual */ 404static Bool RADEONPreInitVisual(ScrnInfoPtr pScrn) 405{ 406 RADEONInfoPtr info = RADEONPTR(pScrn); 407 408 if (!xf86SetDepthBpp(pScrn, 0, 0, 0, Support32bppFb)) 409 return FALSE; 410 411 switch (pScrn->depth) { 412 case 8: 413 case 15: 414 case 16: 415 case 24: 416 break; 417 418 default: 419 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 420 "Given depth (%d) is not supported by %s driver\n", 421 pScrn->depth, RADEON_DRIVER_NAME); 422 return FALSE; 423 } 424 425 xf86PrintDepthBpp(pScrn); 426 427 info->pix24bpp = xf86GetBppFromDepth(pScrn, 428 pScrn->depth); 429 info->pixel_bytes = pScrn->bitsPerPixel / 8; 430 431 if (info->pix24bpp == 24) { 432 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 433 "Radeon does NOT support 24bpp\n"); 434 return FALSE; 435 } 436 437 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 438 "Pixel depth = %d bits stored in %d byte%s (%d bpp pixmaps)\n", 439 pScrn->depth, 440 info->pixel_bytes, 441 info->pixel_bytes > 1 ? "s" : "", 442 info->pix24bpp); 443 444 if (!xf86SetDefaultVisual(pScrn, -1)) return FALSE; 445 446 if (pScrn->depth > 8 && pScrn->defaultVisual != TrueColor) { 447 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 448 "Default visual (%s) is not supported at depth %d\n", 449 xf86GetVisualName(pScrn->defaultVisual), pScrn->depth); 450 return FALSE; 451 } 452 return TRUE; 453} 454 455/* This is called by RADEONPreInit to handle all color weight issues */ 456static Bool RADEONPreInitWeight(ScrnInfoPtr pScrn) 457{ 458 RADEONInfoPtr info = RADEONPTR(pScrn); 459 460 /* Save flag for 6 bit DAC to use for 461 setting CRTC registers. Otherwise use 462 an 8 bit DAC, even if xf86SetWeight sets 463 pScrn->rgbBits to some value other than 464 8. */ 465 info->dac6bits = FALSE; 466 467 if (pScrn->depth > 8) { 468 rgb defaultWeight = { 0, 0, 0 }; 469 470 if (!xf86SetWeight(pScrn, defaultWeight, defaultWeight)) return FALSE; 471 } else { 472 pScrn->rgbBits = 8; 473 } 474 475 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 476 "Using %d bits per RGB (%d bit DAC)\n", 477 pScrn->rgbBits, info->dac6bits ? 6 : 8); 478 479 return TRUE; 480} 481 482static Bool RADEONPreInitAccel_KMS(ScrnInfoPtr pScrn) 483{ 484 RADEONInfoPtr info = RADEONPTR(pScrn); 485 486 if (!(info->accel_state = calloc(1, sizeof(struct radeon_accel_state)))) { 487 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unable to allocate accel_state rec!\n"); 488 return FALSE; 489 } 490 491 /* Check whether direct mapping is used for fast fb access*/ 492 if (RADEONIsFastFBWorking(pScrn)) { 493 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct mapping of fb aperture is enabled for fast fb access.\n"); 494 info->is_fast_fb = TRUE; 495 } 496 497 if (!xf86ReturnOptValBool(info->Options, OPTION_ACCEL, TRUE) || 498 (!RADEONIsAccelWorking(pScrn))) { 499 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 500 "GPU accel disabled or not working, using shadowfb for KMS\n"); 501shadowfb: 502 info->r600_shadow_fb = TRUE; 503 if (!xf86LoadSubModule(pScrn, "shadow")) 504 info->r600_shadow_fb = FALSE; 505 return TRUE; 506 } 507 508#ifdef DRI2 509 info->dri2.available = !!xf86LoadSubModule(pScrn, "dri2"); 510#endif 511 512 if (radeon_glamor_pre_init(pScrn)) 513 return TRUE; 514 515 if (info->ChipFamily >= CHIP_FAMILY_TAHITI) { 516 goto shadowfb; 517 } else if (info->ChipFamily == CHIP_FAMILY_PALM) { 518 info->accel_state->allowHWDFS = RADEONIsFusionGARTWorking(pScrn); 519 } else 520 info->accel_state->allowHWDFS = TRUE; 521 522 if ((info->ChipFamily == CHIP_FAMILY_RS100) || 523 (info->ChipFamily == CHIP_FAMILY_RS200) || 524 (info->ChipFamily == CHIP_FAMILY_RS300) || 525 (info->ChipFamily == CHIP_FAMILY_RS400) || 526 (info->ChipFamily == CHIP_FAMILY_RS480) || 527 (info->ChipFamily == CHIP_FAMILY_RS600) || 528 (info->ChipFamily == CHIP_FAMILY_RS690) || 529 (info->ChipFamily == CHIP_FAMILY_RS740)) 530 info->accel_state->has_tcl = FALSE; 531 else { 532 info->accel_state->has_tcl = TRUE; 533 } 534 535 { 536 int errmaj = 0, errmin = 0; 537 info->exaReq.majorversion = EXA_VERSION_MAJOR; 538 info->exaReq.minorversion = EXA_VERSION_MINOR; 539 if (!LoadSubModule(pScrn->module, "exa", NULL, NULL, NULL, 540 &info->exaReq, &errmaj, &errmin)) { 541 LoaderErrorMsg(NULL, "exa", errmaj, errmin); 542 return FALSE; 543 } 544 } 545 546 return TRUE; 547} 548 549static Bool RADEONPreInitChipType_KMS(ScrnInfoPtr pScrn) 550{ 551 RADEONInfoPtr info = RADEONPTR(pScrn); 552 int i; 553 554 info->Chipset = PCI_DEV_DEVICE_ID(info->PciInfo); 555 pScrn->chipset = (char *)xf86TokenToString(RADEONChipsets, info->Chipset); 556 if (!pScrn->chipset) { 557 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 558 "ChipID 0x%04x is not recognized\n", info->Chipset); 559 return FALSE; 560 } 561 562 if (info->Chipset < 0) { 563 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 564 "Chipset \"%s\" is not recognized\n", pScrn->chipset); 565 return FALSE; 566 } 567 xf86DrvMsg(pScrn->scrnIndex, X_PROBED, 568 "Chipset: \"%s\" (ChipID = 0x%04x)\n", 569 pScrn->chipset, 570 info->Chipset); 571 572 for (i = 0; i < sizeof(RADEONCards) / sizeof(RADEONCardInfo); i++) { 573 if (info->Chipset == RADEONCards[i].pci_device_id) { 574 RADEONCardInfo *card = &RADEONCards[i]; 575 info->ChipFamily = card->chip_family; 576 break; 577 } 578 } 579 580#ifdef RENDER 581 info->RenderAccel = xf86ReturnOptValBool(info->Options, OPTION_RENDER_ACCEL, 582 info->Chipset != PCI_CHIP_RN50_515E && 583 info->Chipset != PCI_CHIP_RN50_5969); 584#endif 585 return TRUE; 586} 587 588static int radeon_get_drm_master_fd(ScrnInfoPtr pScrn) 589{ 590 RADEONInfoPtr info = RADEONPTR(pScrn); 591#ifdef XF86_PDEV_SERVER_FD 592 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 593#endif 594 struct pci_device *dev = info->PciInfo; 595 char *busid; 596 int fd; 597 598#ifdef XF86_PDEV_SERVER_FD 599 if (pRADEONEnt->platform_dev) { 600 fd = xf86_get_platform_device_int_attrib(pRADEONEnt->platform_dev, 601 ODEV_ATTRIB_FD, -1); 602 if (fd != -1) 603 return fd; 604 } 605#endif 606 607#if XORG_VERSION_CURRENT >= XORG_VERSION_NUMERIC(1,9,99,901,0) 608 XNFasprintf(&busid, "pci:%04x:%02x:%02x.%d", 609 dev->domain, dev->bus, dev->dev, dev->func); 610#else 611 busid = XNFprintf("pci:%04x:%02x:%02x.%d", 612 dev->domain, dev->bus, dev->dev, dev->func); 613#endif 614 615 fd = drmOpen(NULL, busid); 616 if (fd == -1) 617 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 618 "[drm] Failed to open DRM device for %s: %s\n", 619 busid, strerror(errno)); 620 621 free(busid); 622 return fd; 623} 624 625static Bool radeon_open_drm_master(ScrnInfoPtr pScrn) 626{ 627 RADEONInfoPtr info = RADEONPTR(pScrn); 628 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 629 drmSetVersion sv; 630 int err; 631 632 if (pRADEONEnt->fd) { 633 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 634 " reusing fd for second head\n"); 635 636 info->drmmode.fd = info->dri2.drm_fd = pRADEONEnt->fd; 637 pRADEONEnt->fd_ref++; 638 return TRUE; 639 } 640 641 info->dri2.drm_fd = radeon_get_drm_master_fd(pScrn); 642 if (info->dri2.drm_fd == -1) 643 return FALSE; 644 645 /* Check that what we opened was a master or a master-capable FD, 646 * by setting the version of the interface we'll use to talk to it. 647 * (see DRIOpenDRMMaster() in DRI1) 648 */ 649 sv.drm_di_major = 1; 650 sv.drm_di_minor = 1; 651 sv.drm_dd_major = -1; 652 sv.drm_dd_minor = -1; 653 err = drmSetInterfaceVersion(info->dri2.drm_fd, &sv); 654 if (err != 0) { 655 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 656 "[drm] failed to set drm interface version.\n"); 657 drmClose(info->dri2.drm_fd); 658 info->dri2.drm_fd = -1; 659 660 return FALSE; 661 } 662 663 pRADEONEnt->fd = info->dri2.drm_fd; 664 pRADEONEnt->fd_ref = 1; 665 info->drmmode.fd = info->dri2.drm_fd; 666 return TRUE; 667} 668 669static Bool r600_get_tile_config(ScrnInfoPtr pScrn) 670{ 671 RADEONInfoPtr info = RADEONPTR(pScrn); 672 struct drm_radeon_info ginfo; 673 int r; 674 uint32_t tmp; 675 676 if (info->ChipFamily < CHIP_FAMILY_R600) 677 return FALSE; 678 679 memset(&ginfo, 0, sizeof(ginfo)); 680 ginfo.request = RADEON_INFO_TILING_CONFIG; 681 ginfo.value = (uintptr_t)&tmp; 682 r = drmCommandWriteRead(info->dri2.drm_fd, DRM_RADEON_INFO, &ginfo, sizeof(ginfo)); 683 if (r) 684 return FALSE; 685 686 info->tile_config = tmp; 687 info->r7xx_bank_op = 0; 688 if (info->ChipFamily >= CHIP_FAMILY_CEDAR) { 689 if (info->dri2.pKernelDRMVersion->version_minor >= 7) { 690 switch (info->tile_config & 0xf) { 691 case 0: 692 info->num_channels = 1; 693 break; 694 case 1: 695 info->num_channels = 2; 696 break; 697 case 2: 698 info->num_channels = 4; 699 break; 700 case 3: 701 info->num_channels = 8; 702 break; 703 default: 704 return FALSE; 705 } 706 707 switch((info->tile_config & 0xf0) >> 4) { 708 case 0: 709 info->num_banks = 4; 710 break; 711 case 1: 712 info->num_banks = 8; 713 break; 714 case 2: 715 info->num_banks = 16; 716 break; 717 default: 718 return FALSE; 719 } 720 721 switch ((info->tile_config & 0xf00) >> 8) { 722 case 0: 723 info->group_bytes = 256; 724 break; 725 case 1: 726 info->group_bytes = 512; 727 break; 728 default: 729 return FALSE; 730 } 731 } else 732 return FALSE; 733 } else { 734 switch((info->tile_config & 0xe) >> 1) { 735 case 0: 736 info->num_channels = 1; 737 break; 738 case 1: 739 info->num_channels = 2; 740 break; 741 case 2: 742 info->num_channels = 4; 743 break; 744 case 3: 745 info->num_channels = 8; 746 break; 747 default: 748 return FALSE; 749 } 750 switch((info->tile_config & 0x30) >> 4) { 751 case 0: 752 info->num_banks = 4; 753 break; 754 case 1: 755 info->num_banks = 8; 756 break; 757 default: 758 return FALSE; 759 } 760 switch((info->tile_config & 0xc0) >> 6) { 761 case 0: 762 info->group_bytes = 256; 763 break; 764 case 1: 765 info->group_bytes = 512; 766 break; 767 default: 768 return FALSE; 769 } 770 } 771 772 info->have_tiling_info = TRUE; 773 return TRUE; 774} 775 776static void RADEONSetupCapabilities(ScrnInfoPtr pScrn) 777{ 778#ifdef RADEON_PIXMAP_SHARING 779 RADEONInfoPtr info = RADEONPTR(pScrn); 780 uint64_t value; 781 int ret; 782 783 pScrn->capabilities = 0; 784 ret = drmGetCap(info->dri2.drm_fd, DRM_CAP_PRIME, &value); 785 if (ret == 0) { 786 if (value & DRM_PRIME_CAP_EXPORT) 787 pScrn->capabilities |= RR_Capability_SourceOutput | RR_Capability_SinkOffload; 788 if (value & DRM_PRIME_CAP_IMPORT) 789 pScrn->capabilities |= RR_Capability_SourceOffload | RR_Capability_SinkOutput; 790 } 791#endif 792} 793 794Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int flags) 795{ 796 RADEONInfoPtr info; 797 RADEONEntPtr pRADEONEnt; 798 DevUnion* pPriv; 799 Gamma zeros = { 0.0, 0.0, 0.0 }; 800 uint32_t tiling = 0; 801 int cpp; 802 803 if (flags & PROBE_DETECT) 804 return TRUE; 805 806 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 807 "RADEONPreInit_KMS\n"); 808 if (pScrn->numEntities != 1) return FALSE; 809 if (!RADEONGetRec(pScrn)) return FALSE; 810 811 info = RADEONPTR(pScrn); 812 info->IsSecondary = FALSE; 813 info->IsPrimary = FALSE; 814 info->pEnt = xf86GetEntityInfo(pScrn->entityList[pScrn->numEntities - 1]); 815 if (info->pEnt->location.type != BUS_PCI 816#ifdef XSERVER_PLATFORM_BUS 817 && info->pEnt->location.type != BUS_PLATFORM 818#endif 819 ) 820 goto fail; 821 822 pPriv = xf86GetEntityPrivate(pScrn->entityList[0], 823 getRADEONEntityIndex()); 824 pRADEONEnt = pPriv->ptr; 825 826 if(xf86IsEntityShared(pScrn->entityList[0])) 827 { 828 if(xf86IsPrimInitDone(pScrn->entityList[0])) 829 { 830 info->IsSecondary = TRUE; 831 pRADEONEnt->pSecondaryScrn = pScrn; 832 } 833 else 834 { 835 info->IsPrimary = TRUE; 836 xf86SetPrimInitDone(pScrn->entityList[0]); 837 pRADEONEnt->pPrimaryScrn = pScrn; 838 pRADEONEnt->HasSecondary = FALSE; 839 } 840 } 841 842 info->PciInfo = xf86GetPciInfoForEntity(info->pEnt->index); 843 pScrn->monitor = pScrn->confScreen->monitor; 844 845 if (!RADEONPreInitVisual(pScrn)) 846 goto fail; 847 848 xf86CollectOptions(pScrn, NULL); 849 if (!(info->Options = malloc(sizeof(RADEONOptions_KMS)))) 850 goto fail; 851 852 memcpy(info->Options, RADEONOptions_KMS, sizeof(RADEONOptions_KMS)); 853 xf86ProcessOptions(pScrn->scrnIndex, pScrn->options, info->Options); 854 855 if (!RADEONPreInitWeight(pScrn)) 856 goto fail; 857 858 if (!RADEONPreInitChipType_KMS(pScrn)) 859 goto fail; 860 861 if (radeon_open_drm_master(pScrn) == FALSE) { 862 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Kernel modesetting setup failed\n"); 863 goto fail; 864 } 865 866 info->dri2.available = FALSE; 867 info->dri2.enabled = FALSE; 868 info->dri2.pKernelDRMVersion = drmGetVersion(info->dri2.drm_fd); 869 if (info->dri2.pKernelDRMVersion == NULL) { 870 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 871 "RADEONDRIGetVersion failed to get the DRM version\n"); 872 goto fail; 873 } 874 875 if (!RADEONPreInitAccel_KMS(pScrn)) goto fail; 876 877 info->allowColorTiling2D = FALSE; 878 879 RADEONSetupCapabilities(pScrn); 880 881 /* don't enable tiling if accel is not enabled */ 882 if (!info->r600_shadow_fb) { 883 Bool colorTilingDefault = 884 xorgGetVersion() >= XORG_VERSION_NUMERIC(1,9,4,901,0) && 885 info->ChipFamily >= CHIP_FAMILY_R300 && 886 /* this check could be removed sometime after a big mesa release 887 * with proper bit, in the meantime you need to set tiling option in 888 * xorg configuration files 889 */ 890 info->ChipFamily <= CHIP_FAMILY_MULLINS && 891 !info->is_fast_fb; 892 893 /* 2D color tiling */ 894 if (info->ChipFamily >= CHIP_FAMILY_R600) { 895 info->allowColorTiling2D = xf86ReturnOptValBool(info->Options, OPTION_COLOR_TILING_2D, 896 info->ChipFamily <= CHIP_FAMILY_MULLINS); 897 } 898 899 if (info->ChipFamily >= CHIP_FAMILY_R600) { 900 /* set default group bytes, overridden by kernel info below */ 901 info->group_bytes = 256; 902 info->have_tiling_info = FALSE; 903 if (info->dri2.pKernelDRMVersion->version_minor >= 6) { 904 if (r600_get_tile_config(pScrn)) { 905 info->allowColorTiling = xf86ReturnOptValBool(info->Options, 906 OPTION_COLOR_TILING, colorTilingDefault); 907 /* need working DFS for tiling */ 908 if ((info->ChipFamily == CHIP_FAMILY_PALM) && 909 (!info->accel_state->allowHWDFS)) 910 info->allowColorTiling = FALSE; 911 } else 912 info->allowColorTiling = FALSE; 913 } else 914 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 915 "R6xx+ KMS Color Tiling requires radeon drm 2.6.0 or newer\n"); 916 } else 917 info->allowColorTiling = xf86ReturnOptValBool(info->Options, 918 OPTION_COLOR_TILING, colorTilingDefault); 919 } else 920 info->allowColorTiling = FALSE; 921 922 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 923 "KMS Color Tiling: %sabled\n", info->allowColorTiling ? "en" : "dis"); 924 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 925 "KMS Color Tiling 2D: %sabled\n", info->allowColorTiling2D ? "en" : "dis"); 926 927 if (info->dri2.pKernelDRMVersion->version_minor >= 8) { 928 info->allowPageFlip = xf86ReturnOptValBool(info->Options, 929 OPTION_PAGE_FLIP, TRUE); 930 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 931 "KMS Pageflipping: %sabled\n", info->allowPageFlip ? "en" : "dis"); 932 } 933 934 info->swapBuffersWait = xf86ReturnOptValBool(info->Options, 935 OPTION_SWAPBUFFERS_WAIT, TRUE); 936 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 937 "SwapBuffers wait for vsync: %sabled\n", info->swapBuffersWait ? "en" : "dis"); 938 939 if (drmmode_pre_init(pScrn, &info->drmmode, pScrn->bitsPerPixel / 8) == FALSE) { 940 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Kernel modesetting setup failed\n"); 941 goto fail; 942 } 943 944 if (info->drmmode.mode_res->count_crtcs == 1) 945 pRADEONEnt->HasCRTC2 = FALSE; 946 else 947 pRADEONEnt->HasCRTC2 = TRUE; 948 949 950 /* fix up cloning on rn50 cards 951 * since they only have one crtc sometimes the xserver doesn't assign 952 * a crtc to one of the outputs even though both outputs have common modes 953 * which results in only one monitor being enabled. Assign a crtc here so 954 * that both outputs light up. 955 */ 956 if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2) { 957 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 958 int i; 959 960 for (i = 0; i < xf86_config->num_output; i++) { 961 xf86OutputPtr output = xf86_config->output[i]; 962 963 /* XXX: double check crtc mode */ 964 if ((output->probed_modes != NULL) && (output->crtc == NULL)) 965 output->crtc = xf86_config->crtc[0]; 966 } 967 } 968 969 /* set cursor size */ 970 if (info->ChipFamily >= CHIP_FAMILY_BONAIRE) { 971 info->cursor_w = CURSOR_WIDTH_CIK; 972 info->cursor_h = CURSOR_HEIGHT_CIK; 973 } else { 974 info->cursor_w = CURSOR_WIDTH; 975 info->cursor_h = CURSOR_HEIGHT; 976 } 977 978 { 979 struct drm_radeon_gem_info mminfo; 980 981 if (!drmCommandWriteRead(info->dri2.drm_fd, DRM_RADEON_GEM_INFO, &mminfo, sizeof(mminfo))) 982 { 983 info->vram_size = mminfo.vram_visible; 984 info->gart_size = mminfo.gart_size; 985 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 986 "mem size init: gart size :%llx vram size: s:%llx visible:%llx\n", 987 (unsigned long long)mminfo.gart_size, 988 (unsigned long long)mminfo.vram_size, 989 (unsigned long long)mminfo.vram_visible); 990 } 991 } 992 993 if (!info->use_glamor) { 994 info->exa_pixmaps = xf86ReturnOptValBool(info->Options, 995 OPTION_EXA_PIXMAPS, 996 (info->vram_size > (32 * 1024 * 1024) && 997 info->RenderAccel && 998 !info->is_fast_fb)); 999 if (info->exa_pixmaps) 1000 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1001 "EXA: Driver will allow EXA pixmaps in VRAM\n"); 1002 else 1003 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1004 "EXA: Driver will not allow EXA pixmaps in VRAM\n"); 1005 } 1006 1007 /* no tiled scanout on r6xx+ yet */ 1008 if (info->allowColorTiling) { 1009 if (info->ChipFamily >= CHIP_FAMILY_R600) 1010 tiling |= RADEON_TILING_MICRO; 1011 else 1012 tiling |= RADEON_TILING_MACRO; 1013 } 1014 cpp = pScrn->bitsPerPixel / 8; 1015 pScrn->displayWidth = 1016 RADEON_ALIGN(pScrn->virtualX, drmmode_get_pitch_align(pScrn, cpp, tiling)); 1017 1018 /* Set display resolution */ 1019 xf86SetDpi(pScrn, 0, 0); 1020 1021 /* Get ScreenInit function */ 1022 if (!xf86LoadSubModule(pScrn, "fb")) return FALSE; 1023 1024 if (!xf86SetGamma(pScrn, zeros)) return FALSE; 1025 1026 if (!xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) { 1027 if (!xf86LoadSubModule(pScrn, "ramdac")) return FALSE; 1028 } 1029 1030 if (pScrn->modes == NULL 1031#ifdef XSERVER_PLATFORM_BUS 1032 && !pScrn->is_gpu 1033#endif 1034 ) { 1035 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No modes.\n"); 1036 goto fail; 1037 } 1038 1039 return TRUE; 1040 fail: 1041 RADEONFreeRec(pScrn); 1042 return FALSE; 1043 1044} 1045 1046static Bool RADEONCursorInit_KMS(ScreenPtr pScreen) 1047{ 1048 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); 1049 RADEONInfoPtr info = RADEONPTR(pScrn); 1050 1051 return xf86_cursors_init (pScreen, info->cursor_w, info->cursor_h, 1052 (HARDWARE_CURSOR_TRUECOLOR_AT_8BPP | 1053 HARDWARE_CURSOR_AND_SOURCE_WITH_MASK | 1054 HARDWARE_CURSOR_SOURCE_MASK_INTERLEAVE_1 | 1055 HARDWARE_CURSOR_UPDATE_UNHIDDEN | 1056 HARDWARE_CURSOR_ARGB)); 1057} 1058 1059void 1060RADEONBlank(ScrnInfoPtr pScrn) 1061{ 1062 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 1063 xf86OutputPtr output; 1064 xf86CrtcPtr crtc; 1065 int o, c; 1066 1067 for (c = 0; c < xf86_config->num_crtc; c++) { 1068 crtc = xf86_config->crtc[c]; 1069 for (o = 0; o < xf86_config->num_output; o++) { 1070 output = xf86_config->output[o]; 1071 if (output->crtc != crtc) 1072 continue; 1073 1074 output->funcs->dpms(output, DPMSModeOff); 1075 } 1076 crtc->funcs->dpms(crtc, DPMSModeOff); 1077 } 1078} 1079 1080void 1081RADEONUnblank(ScrnInfoPtr pScrn) 1082{ 1083 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 1084 xf86OutputPtr output; 1085 xf86CrtcPtr crtc; 1086 int o, c; 1087 for (c = 0; c < xf86_config->num_crtc; c++) { 1088 crtc = xf86_config->crtc[c]; 1089 if(!crtc->enabled) 1090 continue; 1091 crtc->funcs->dpms(crtc, DPMSModeOn); 1092 for (o = 0; o < xf86_config->num_output; o++) { 1093 output = xf86_config->output[o]; 1094 if (output->crtc != crtc) 1095 continue; 1096 output->funcs->dpms(output, DPMSModeOn); 1097 } 1098 } 1099} 1100 1101 1102static Bool RADEONSaveScreen_KMS(ScreenPtr pScreen, int mode) 1103{ 1104 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); 1105 Bool unblank; 1106 1107 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 1108 "RADEONSaveScreen(%d)\n", mode); 1109 1110 unblank = xf86IsUnblank(mode); 1111 if (unblank) SetTimeSinceLastInputEvent(); 1112 1113 if ((pScrn != NULL) && pScrn->vtSema) { 1114 if (unblank) 1115 RADEONUnblank(pScrn); 1116 else 1117 RADEONBlank(pScrn); 1118 } 1119 return TRUE; 1120} 1121 1122static Bool radeon_set_drm_master(ScrnInfoPtr pScrn) 1123{ 1124 RADEONInfoPtr info = RADEONPTR(pScrn); 1125#ifdef XF86_PDEV_SERVER_FD 1126 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 1127#endif 1128 int err; 1129 1130#ifdef XF86_PDEV_SERVER_FD 1131 if (pRADEONEnt->platform_dev && 1132 (pRADEONEnt->platform_dev->flags & XF86_PDEV_SERVER_FD)) 1133 return TRUE; 1134#endif 1135 1136 err = drmSetMaster(info->dri2.drm_fd); 1137 if (err) 1138 ErrorF("Unable to retrieve master\n"); 1139 1140 return err == 0; 1141} 1142 1143static void radeon_drop_drm_master(ScrnInfoPtr pScrn) 1144{ 1145 RADEONInfoPtr info = RADEONPTR(pScrn); 1146#ifdef XF86_PDEV_SERVER_FD 1147 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 1148 1149 if (pRADEONEnt->platform_dev && 1150 (pRADEONEnt->platform_dev->flags & XF86_PDEV_SERVER_FD)) 1151 return; 1152#endif 1153 1154 drmDropMaster(info->dri2.drm_fd); 1155} 1156 1157/* Called at the end of each server generation. Restore the original 1158 * text mode, unmap video memory, and unwrap and call the saved 1159 * CloseScreen function. 1160 */ 1161static Bool RADEONCloseScreen_KMS(CLOSE_SCREEN_ARGS_DECL) 1162{ 1163 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); 1164 RADEONInfoPtr info = RADEONPTR(pScrn); 1165 1166 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 1167 "RADEONCloseScreen\n"); 1168 1169 drmmode_uevent_fini(pScrn, &info->drmmode); 1170 radeon_cs_flush_indirect(pScrn); 1171 1172 DeleteCallback(&FlushCallback, radeon_flush_callback, pScrn); 1173 1174 if (info->accel_state->exa) { 1175 exaDriverFini(pScreen); 1176 free(info->accel_state->exa); 1177 info->accel_state->exa = NULL; 1178 } 1179 1180 if (info->accel_state->use_vbos) 1181 radeon_vbo_free_lists(pScrn); 1182 1183 radeon_drop_drm_master(pScrn); 1184 1185 drmmode_fini(pScrn, &info->drmmode); 1186 if (info->dri2.enabled) 1187 radeon_dri2_close_screen(pScreen); 1188 1189 pScrn->vtSema = FALSE; 1190 xf86ClearPrimInitDone(info->pEnt->index); 1191 pScreen->BlockHandler = info->BlockHandler; 1192 pScreen->CloseScreen = info->CloseScreen; 1193 return (*pScreen->CloseScreen)(CLOSE_SCREEN_ARGS); 1194} 1195 1196 1197void RADEONFreeScreen_KMS(FREE_SCREEN_ARGS_DECL) 1198{ 1199 SCRN_INFO_PTR(arg); 1200 RADEONInfoPtr info = RADEONPTR(pScrn); 1201 1202 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 1203 "RADEONFreeScreen\n"); 1204 1205 /* when server quits at PreInit, we don't need do this anymore*/ 1206 if (!info) return; 1207 1208 RADEONFreeRec(pScrn); 1209} 1210 1211Bool RADEONScreenInit_KMS(SCREEN_INIT_ARGS_DECL) 1212{ 1213 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); 1214 RADEONInfoPtr info = RADEONPTR(pScrn); 1215 int subPixelOrder = SubPixelUnknown; 1216 const char *s; 1217 void *front_ptr; 1218 1219 pScrn->fbOffset = 0; 1220 1221 miClearVisualTypes(); 1222 if (!miSetVisualTypes(pScrn->depth, 1223 miGetDefaultVisualMask(pScrn->depth), 1224 pScrn->rgbBits, 1225 pScrn->defaultVisual)) return FALSE; 1226 miSetPixmapDepths (); 1227 1228 if (!radeon_set_drm_master(pScrn)) 1229 return FALSE; 1230 1231 info->directRenderingEnabled = FALSE; 1232 if (info->r600_shadow_fb == FALSE) 1233 info->directRenderingEnabled = radeon_dri2_screen_init(pScreen); 1234 1235 info->surf_man = radeon_surface_manager_new(info->dri2.drm_fd); 1236 if (!info->bufmgr) 1237 info->bufmgr = radeon_bo_manager_gem_ctor(info->dri2.drm_fd); 1238 if (!info->bufmgr) { 1239 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1240 "failed to initialise GEM buffer manager"); 1241 return FALSE; 1242 } 1243 drmmode_set_bufmgr(pScrn, &info->drmmode, info->bufmgr); 1244 1245 if (!info->csm) 1246 info->csm = radeon_cs_manager_gem_ctor(info->dri2.drm_fd); 1247 if (!info->csm) { 1248 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1249 "failed to initialise command submission manager"); 1250 return FALSE; 1251 } 1252 1253 if (!info->cs) 1254 info->cs = radeon_cs_create(info->csm, RADEON_BUFFER_SIZE/4); 1255 if (!info->cs) { 1256 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1257 "failed to initialise command submission buffer"); 1258 return FALSE; 1259 } 1260 1261 radeon_cs_set_limit(info->cs, RADEON_GEM_DOMAIN_GTT, info->gart_size); 1262 radeon_cs_space_set_flush(info->cs, (void(*)(void *))radeon_cs_flush_indirect, pScrn); 1263 1264 if (!radeon_setup_kernel_mem(pScreen)) { 1265 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "radeon_setup_kernel_mem failed\n"); 1266 return FALSE; 1267 } 1268 front_ptr = info->front_bo->ptr; 1269 1270 if (info->r600_shadow_fb) { 1271 info->fb_shadow = calloc(1, 1272 pScrn->displayWidth * pScrn->virtualY * 1273 ((pScrn->bitsPerPixel + 7) >> 3)); 1274 if (info->fb_shadow == NULL) { 1275 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1276 "Failed to allocate shadow framebuffer\n"); 1277 info->r600_shadow_fb = FALSE; 1278 } else { 1279 if (!fbScreenInit(pScreen, info->fb_shadow, 1280 pScrn->virtualX, pScrn->virtualY, 1281 pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth, 1282 pScrn->bitsPerPixel)) 1283 return FALSE; 1284 } 1285 } 1286 1287 if (info->r600_shadow_fb == FALSE) { 1288 /* Init fb layer */ 1289 if (!fbScreenInit(pScreen, front_ptr, 1290 pScrn->virtualX, pScrn->virtualY, 1291 pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth, 1292 pScrn->bitsPerPixel)) 1293 return FALSE; 1294 } 1295 1296 xf86SetBlackWhitePixels(pScreen); 1297 1298 if (pScrn->bitsPerPixel > 8) { 1299 VisualPtr visual; 1300 1301 visual = pScreen->visuals + pScreen->numVisuals; 1302 while (--visual >= pScreen->visuals) { 1303 if ((visual->class | DynamicClass) == DirectColor) { 1304 visual->offsetRed = pScrn->offset.red; 1305 visual->offsetGreen = pScrn->offset.green; 1306 visual->offsetBlue = pScrn->offset.blue; 1307 visual->redMask = pScrn->mask.red; 1308 visual->greenMask = pScrn->mask.green; 1309 visual->blueMask = pScrn->mask.blue; 1310 } 1311 } 1312 } 1313 1314 /* Must be after RGB order fixed */ 1315 fbPictureInit (pScreen, 0, 0); 1316 1317#ifdef RENDER 1318 if ((s = xf86GetOptValString(info->Options, OPTION_SUBPIXEL_ORDER))) { 1319 if (strcmp(s, "RGB") == 0) subPixelOrder = SubPixelHorizontalRGB; 1320 else if (strcmp(s, "BGR") == 0) subPixelOrder = SubPixelHorizontalBGR; 1321 else if (strcmp(s, "NONE") == 0) subPixelOrder = SubPixelNone; 1322 PictureSetSubpixelOrder (pScreen, subPixelOrder); 1323 } 1324#endif 1325 1326 pScrn->vtSema = TRUE; 1327 xf86SetBackingStore(pScreen); 1328 1329 if (info->directRenderingEnabled) { 1330 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct rendering enabled\n"); 1331 } else { 1332 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 1333 "Direct rendering disabled\n"); 1334 } 1335 1336 if (info->r600_shadow_fb) { 1337 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Acceleration disabled\n"); 1338 info->accelOn = FALSE; 1339 } else { 1340 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 1341 "Initializing Acceleration\n"); 1342 if (RADEONAccelInit(pScreen)) { 1343 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Acceleration enabled\n"); 1344 info->accelOn = TRUE; 1345 } else { 1346 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1347 "Acceleration initialization failed\n"); 1348 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Acceleration disabled\n"); 1349 info->accelOn = FALSE; 1350 } 1351 } 1352 1353 /* Init DPMS */ 1354 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 1355 "Initializing DPMS\n"); 1356 xf86DPMSInit(pScreen, xf86DPMSSet, 0); 1357 1358 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 1359 "Initializing Cursor\n"); 1360 1361 /* Set Silken Mouse */ 1362 xf86SetSilkenMouse(pScreen); 1363 1364 /* Cursor setup */ 1365 miDCInitialize(pScreen, xf86GetPointerScreenFuncs()); 1366 1367 if (!xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) { 1368 if (RADEONCursorInit_KMS(pScreen)) { 1369 } 1370 } 1371 1372 /* DGA setup */ 1373#ifdef XFreeXDGA 1374 /* DGA is dangerous on kms as the base and framebuffer location may change: 1375 * http://lists.freedesktop.org/archives/xorg-devel/2009-September/002113.html 1376 */ 1377 /* xf86DiDGAInit(pScreen, info->LinearAddr + pScrn->fbOffset); */ 1378#endif 1379 if (info->r600_shadow_fb == FALSE) { 1380 /* Init Xv */ 1381 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 1382 "Initializing Xv\n"); 1383 RADEONInitVideo(pScreen); 1384 } 1385 1386 if (info->r600_shadow_fb == TRUE) { 1387 if (!shadowSetup(pScreen)) { 1388 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1389 "Shadowfb initialization failed\n"); 1390 return FALSE; 1391 } 1392 } 1393 pScrn->pScreen = pScreen; 1394 1395 /* Provide SaveScreen & wrap BlockHandler and CloseScreen */ 1396 /* Wrap CloseScreen */ 1397 info->CloseScreen = pScreen->CloseScreen; 1398 pScreen->CloseScreen = RADEONCloseScreen_KMS; 1399 pScreen->SaveScreen = RADEONSaveScreen_KMS; 1400 info->BlockHandler = pScreen->BlockHandler; 1401 pScreen->BlockHandler = RADEONBlockHandler_KMS; 1402 1403 if (!AddCallback(&FlushCallback, radeon_flush_callback, pScrn)) 1404 return FALSE; 1405 1406 info->CreateScreenResources = pScreen->CreateScreenResources; 1407 pScreen->CreateScreenResources = RADEONCreateScreenResources_KMS; 1408 1409#ifdef RADEON_PIXMAP_SHARING 1410 pScreen->StartPixmapTracking = PixmapStartDirtyTracking; 1411 pScreen->StopPixmapTracking = PixmapStopDirtyTracking; 1412#endif 1413 1414 if (!xf86CrtcScreenInit (pScreen)) 1415 return FALSE; 1416 1417 /* Wrap pointer motion to flip touch screen around */ 1418// info->PointerMoved = pScrn->PointerMoved; 1419// pScrn->PointerMoved = RADEONPointerMoved; 1420 1421 if (!drmmode_setup_colormap(pScreen, pScrn)) 1422 return FALSE; 1423 1424 /* Note unused options */ 1425 if (serverGeneration == 1) 1426 xf86ShowUnusedOptions(pScrn->scrnIndex, pScrn->options); 1427 1428 drmmode_init(pScrn, &info->drmmode); 1429 1430 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 1431 "RADEONScreenInit finished\n"); 1432 1433 info->accel_state->XInited3D = FALSE; 1434 info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN; 1435 1436 return TRUE; 1437} 1438 1439Bool RADEONEnterVT_KMS(VT_FUNC_ARGS_DECL) 1440{ 1441 SCRN_INFO_PTR(arg); 1442 RADEONInfoPtr info = RADEONPTR(pScrn); 1443 1444 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 1445 "RADEONEnterVT_KMS\n"); 1446 1447 radeon_set_drm_master(pScrn); 1448 1449 info->accel_state->XInited3D = FALSE; 1450 info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN; 1451 1452 pScrn->vtSema = TRUE; 1453 1454 if (!drmmode_set_desired_modes(pScrn, &info->drmmode)) 1455 return FALSE; 1456 1457 return TRUE; 1458} 1459 1460 1461void RADEONLeaveVT_KMS(VT_FUNC_ARGS_DECL) 1462{ 1463 SCRN_INFO_PTR(arg); 1464 RADEONInfoPtr info = RADEONPTR(pScrn); 1465 1466 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 1467 "RADEONLeaveVT_KMS\n"); 1468 1469 radeon_drop_drm_master(pScrn); 1470 1471 xf86RotateFreeShadow(pScrn); 1472 1473 xf86_hide_cursors (pScrn); 1474 info->accel_state->XInited3D = FALSE; 1475 info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN; 1476 1477 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 1478 "Ok, leaving now...\n"); 1479} 1480 1481 1482Bool RADEONSwitchMode_KMS(SWITCH_MODE_ARGS_DECL) 1483{ 1484 SCRN_INFO_PTR(arg); 1485 Bool ret; 1486 ret = xf86SetSingleMode (pScrn, mode, RR_Rotate_0); 1487 return ret; 1488 1489} 1490 1491void RADEONAdjustFrame_KMS(ADJUST_FRAME_ARGS_DECL) 1492{ 1493 SCRN_INFO_PTR(arg); 1494 RADEONInfoPtr info = RADEONPTR(pScrn); 1495 drmmode_adjust_frame(pScrn, &info->drmmode, x, y); 1496 return; 1497} 1498 1499static Bool radeon_setup_kernel_mem(ScreenPtr pScreen) 1500{ 1501 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); 1502 RADEONInfoPtr info = RADEONPTR(pScrn); 1503 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 1504 int cpp = info->pixel_bytes; 1505 uint32_t screen_size; 1506 int pitch, base_align; 1507 uint32_t tiling_flags = 0; 1508 struct radeon_surface surface; 1509 1510 if (info->accel_state->exa != NULL) { 1511 xf86DrvMsg(pScreen->myNum, X_ERROR, "Memory map already initialized\n"); 1512 return FALSE; 1513 } 1514 if (!info->use_glamor && info->r600_shadow_fb == FALSE) { 1515 info->accel_state->exa = exaDriverAlloc(); 1516 if (info->accel_state->exa == NULL) { 1517 xf86DrvMsg(pScreen->myNum, X_ERROR, "exaDriverAlloc failed\n"); 1518 return FALSE; 1519 } 1520 } 1521 1522 if (info->allowColorTiling) { 1523 if (info->ChipFamily >= CHIP_FAMILY_R600) { 1524 if (info->allowColorTiling2D) { 1525 tiling_flags |= RADEON_TILING_MACRO; 1526 } else { 1527 tiling_flags |= RADEON_TILING_MICRO; 1528 } 1529 } else 1530 tiling_flags |= RADEON_TILING_MACRO; 1531 } 1532 pitch = RADEON_ALIGN(pScrn->virtualX, drmmode_get_pitch_align(pScrn, cpp, tiling_flags)) * cpp; 1533 screen_size = RADEON_ALIGN(pScrn->virtualY, drmmode_get_height_align(pScrn, tiling_flags)) * pitch; 1534 base_align = drmmode_get_base_align(pScrn, cpp, tiling_flags); 1535 if (info->ChipFamily >= CHIP_FAMILY_R600) { 1536 if(!info->surf_man) { 1537 xf86DrvMsg(pScreen->myNum, X_ERROR, 1538 "failed to initialise surface manager\n"); 1539 return FALSE; 1540 } 1541 memset(&surface, 0, sizeof(struct radeon_surface)); 1542 surface.npix_x = pScrn->virtualX; 1543 surface.npix_y = pScrn->virtualY; 1544 surface.npix_z = 1; 1545 surface.blk_w = 1; 1546 surface.blk_h = 1; 1547 surface.blk_d = 1; 1548 surface.array_size = 1; 1549 surface.last_level = 0; 1550 surface.bpe = cpp; 1551 surface.nsamples = 1; 1552 surface.flags = RADEON_SURF_SCANOUT; 1553 /* we are requiring a recent enough libdrm version */ 1554 surface.flags |= RADEON_SURF_HAS_TILE_MODE_INDEX; 1555 surface.flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE); 1556 surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE); 1557 if (tiling_flags & RADEON_TILING_MICRO) { 1558 surface.flags = RADEON_SURF_CLR(surface.flags, MODE); 1559 surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE); 1560 } 1561 if (tiling_flags & RADEON_TILING_MACRO) { 1562 surface.flags = RADEON_SURF_CLR(surface.flags, MODE); 1563 surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE); 1564 } 1565 if (radeon_surface_best(info->surf_man, &surface)) { 1566 xf86DrvMsg(pScreen->myNum, X_ERROR, 1567 "radeon_surface_best failed\n"); 1568 return FALSE; 1569 } 1570 if (radeon_surface_init(info->surf_man, &surface)) { 1571 xf86DrvMsg(pScreen->myNum, X_ERROR, 1572 "radeon_surface_init failed\n"); 1573 return FALSE; 1574 } 1575 pitch = surface.level[0].pitch_bytes; 1576 screen_size = surface.bo_size; 1577 base_align = surface.bo_alignment; 1578 tiling_flags = 0; 1579 switch (surface.level[0].mode) { 1580 case RADEON_SURF_MODE_2D: 1581 tiling_flags |= RADEON_TILING_MACRO; 1582 tiling_flags |= surface.bankw << RADEON_TILING_EG_BANKW_SHIFT; 1583 tiling_flags |= surface.bankh << RADEON_TILING_EG_BANKH_SHIFT; 1584 tiling_flags |= surface.mtilea << RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT; 1585 tiling_flags |= eg_tile_split(surface.tile_split) << RADEON_TILING_EG_TILE_SPLIT_SHIFT; 1586 break; 1587 case RADEON_SURF_MODE_1D: 1588 tiling_flags |= RADEON_TILING_MICRO; 1589 break; 1590 default: 1591 break; 1592 } 1593 info->front_surface = surface; 1594 } 1595 { 1596 int cursor_size; 1597 int c; 1598 1599 cursor_size = info->cursor_w * info->cursor_h * 4; 1600 cursor_size = RADEON_ALIGN(cursor_size, RADEON_GPU_PAGE_SIZE); 1601 for (c = 0; c < xf86_config->num_crtc; c++) { 1602 /* cursor objects */ 1603 if (info->cursor_bo[c] == NULL) { 1604 info->cursor_bo[c] = radeon_bo_open(info->bufmgr, 0, 1605 cursor_size, 0, 1606 RADEON_GEM_DOMAIN_VRAM, 0); 1607 if (!info->cursor_bo[c]) { 1608 ErrorF("Failed to allocate cursor buffer memory\n"); 1609 return FALSE; 1610 } 1611 1612 if (radeon_bo_map(info->cursor_bo[c], 1)) { 1613 ErrorF("Failed to map cursor buffer memory\n"); 1614 } 1615 1616 drmmode_set_cursor(pScrn, &info->drmmode, c, info->cursor_bo[c]); 1617 } 1618 } 1619 } 1620 1621 screen_size = RADEON_ALIGN(screen_size, RADEON_GPU_PAGE_SIZE); 1622 1623 if (info->front_bo == NULL) { 1624 info->front_bo = radeon_bo_open(info->bufmgr, 0, screen_size, 1625 base_align, RADEON_GEM_DOMAIN_VRAM, 0); 1626 if (info->r600_shadow_fb == TRUE) { 1627 if (radeon_bo_map(info->front_bo, 1)) { 1628 ErrorF("Failed to map cursor buffer memory\n"); 1629 } 1630 } 1631#if X_BYTE_ORDER == X_BIG_ENDIAN 1632 switch (cpp) { 1633 case 4: 1634 tiling_flags |= RADEON_TILING_SWAP_32BIT; 1635 break; 1636 case 2: 1637 tiling_flags |= RADEON_TILING_SWAP_16BIT; 1638 break; 1639 } 1640 if (info->ChipFamily < CHIP_FAMILY_R600 && 1641 info->r600_shadow_fb && tiling_flags) 1642 tiling_flags |= RADEON_TILING_SURFACE; 1643#endif 1644 if (tiling_flags) 1645 radeon_bo_set_tiling(info->front_bo, tiling_flags, pitch); 1646 } 1647 1648 pScrn->displayWidth = pitch / cpp; 1649 1650 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Front buffer size: %dK\n", info->front_bo->size/1024); 1651 radeon_kms_update_vram_limit(pScrn, screen_size); 1652 return TRUE; 1653} 1654 1655void radeon_kms_update_vram_limit(ScrnInfoPtr pScrn, uint32_t new_fb_size) 1656{ 1657 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 1658 RADEONInfoPtr info = RADEONPTR(pScrn); 1659 uint64_t remain_size_bytes; 1660 int c; 1661 1662 for (c = 0; c < xf86_config->num_crtc; c++) { 1663 if (info->cursor_bo[c] != NULL) { 1664 new_fb_size += (64 * 4 * 64); 1665 } 1666 } 1667 1668 remain_size_bytes = info->vram_size - new_fb_size; 1669 remain_size_bytes = (remain_size_bytes / 10) * 9; 1670 if (remain_size_bytes > 0xffffffff) 1671 remain_size_bytes = 0xffffffff; 1672 radeon_cs_set_limit(info->cs, RADEON_GEM_DOMAIN_VRAM, 1673 (uint32_t)remain_size_bytes); 1674 1675 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "VRAM usage limit set to %uK\n", 1676 (uint32_t)remain_size_bytes / 1024); 1677} 1678 1679/* Used to disallow modes that are not supported by the hardware */ 1680ModeStatus RADEONValidMode(SCRN_ARG_TYPE arg, DisplayModePtr mode, 1681 Bool verbose, int flag) 1682{ 1683 SCRN_INFO_PTR(arg); 1684 RADEONInfoPtr info = RADEONPTR(pScrn); 1685 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 1686 1687 /* 1688 * RN50 has effective maximum mode bandwidth of about 300MiB/s. 1689 * XXX should really do this for all chips by properly computing 1690 * memory bandwidth and an overhead factor. 1691 */ 1692 if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2) { 1693 if (xf86ModeBandwidth(mode, pScrn->bitsPerPixel) > 300) 1694 return MODE_BANDWIDTH; 1695 } 1696 /* There are problems with double scan mode at high clocks 1697 * They're likely related PLL and display buffer settings. 1698 * Disable these modes for now. 1699 */ 1700 if (mode->Flags & V_DBLSCAN) { 1701 if ((mode->CrtcHDisplay >= 1024) || (mode->CrtcVDisplay >= 768)) 1702 return MODE_CLOCK_RANGE; 1703 } 1704 return MODE_OK; 1705} 1706