radeon_kms.c revision 8a02c2b0
1/* 2 * Copyright © 2009 Red Hat, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Dave Airlie <airlied@redhat.com> 25 * 26 */ 27#ifdef HAVE_CONFIG_H 28#include "config.h" 29#endif 30 31#include <errno.h> 32#include <sys/ioctl.h> 33/* Driver data structures */ 34#include "radeon.h" 35#include "radeon_bo_helper.h" 36#include "radeon_drm_queue.h" 37#include "radeon_glamor.h" 38#include "radeon_reg.h" 39#include "radeon_probe.h" 40#include "micmap.h" 41#include "mipointrst.h" 42 43#include "radeon_version.h" 44#include "shadow.h" 45#include <xf86Priv.h> 46 47#include "atipciids.h" 48 49#if HAVE_PRESENT_H 50#include <present.h> 51#endif 52 53/* DPMS */ 54#ifdef HAVE_XEXTPROTO_71 55#include <X11/extensions/dpmsconst.h> 56#else 57#define DPMS_SERVER 58#include <X11/extensions/dpms.h> 59#endif 60 61#include <X11/extensions/damageproto.h> 62 63#include "radeon_chipinfo_gen.h" 64 65#include "radeon_bo_gem.h" 66#include "radeon_cs_gem.h" 67#include "radeon_vbo.h" 68 69static DevScreenPrivateKeyRec radeon_client_private_key; 70DevScreenPrivateKeyRec radeon_device_private_key; 71 72extern SymTabRec RADEONChipsets[]; 73static Bool radeon_setup_kernel_mem(ScreenPtr pScreen); 74 75const OptionInfoRec RADEONOptions_KMS[] = { 76 { OPTION_ACCEL, "Accel", OPTV_BOOLEAN, {0}, FALSE }, 77 { OPTION_SW_CURSOR, "SWcursor", OPTV_BOOLEAN, {0}, FALSE }, 78 { OPTION_PAGE_FLIP, "EnablePageFlip", OPTV_BOOLEAN, {0}, FALSE }, 79 { OPTION_COLOR_TILING, "ColorTiling", OPTV_BOOLEAN, {0}, FALSE }, 80 { OPTION_COLOR_TILING_2D,"ColorTiling2D", OPTV_BOOLEAN, {0}, FALSE }, 81 { OPTION_RENDER_ACCEL, "RenderAccel", OPTV_BOOLEAN, {0}, FALSE }, 82 { OPTION_SUBPIXEL_ORDER, "SubPixelOrder", OPTV_ANYSTR, {0}, FALSE }, 83#ifdef USE_GLAMOR 84 { OPTION_ACCELMETHOD, "AccelMethod", OPTV_STRING, {0}, FALSE }, 85 { OPTION_SHADOW_PRIMARY, "ShadowPrimary", OPTV_BOOLEAN, {0}, FALSE }, 86#endif 87 { OPTION_EXA_VSYNC, "EXAVSync", OPTV_BOOLEAN, {0}, FALSE }, 88 { OPTION_EXA_PIXMAPS, "EXAPixmaps", OPTV_BOOLEAN, {0}, FALSE }, 89 { OPTION_ZAPHOD_HEADS, "ZaphodHeads", OPTV_STRING, {0}, FALSE }, 90 { OPTION_SWAPBUFFERS_WAIT,"SwapbuffersWait", OPTV_BOOLEAN, {0}, FALSE }, 91 { OPTION_DELETE_DP12, "DeleteUnusedDP12Displays", OPTV_BOOLEAN, {0}, FALSE}, 92 { OPTION_DRI3, "DRI3", OPTV_BOOLEAN, {0}, FALSE }, 93 { OPTION_DRI, "DRI", OPTV_INTEGER, {0}, FALSE }, 94 { OPTION_TEAR_FREE, "TearFree", OPTV_BOOLEAN, {0}, FALSE }, 95 { -1, NULL, OPTV_NONE, {0}, FALSE } 96}; 97 98const OptionInfoRec *RADEONOptionsWeak(void) { return RADEONOptions_KMS; } 99 100void radeon_cs_flush_indirect(ScrnInfoPtr pScrn) 101{ 102 RADEONInfoPtr info = RADEONPTR(pScrn); 103 struct radeon_accel_state *accel_state; 104 int ret; 105 106 info->gpu_flushed++; 107 108#ifdef USE_GLAMOR 109 if (info->use_glamor) { 110 glamor_block_handler(pScrn->pScreen); 111 return; 112 } 113#endif 114 115 if (!info->cs->cdw) 116 return; 117 118 accel_state = info->accel_state; 119 120 /* release the current VBO so we don't block on mapping it later */ 121 if (info->accel_state->vbo.vb_offset && info->accel_state->vbo.vb_bo) { 122 radeon_vbo_put(pScrn, &info->accel_state->vbo); 123 info->accel_state->vbo.vb_start_op = -1; 124 } 125 126 /* release the current VBO so we don't block on mapping it later */ 127 if (info->accel_state->cbuf.vb_bo) { 128 radeon_vbo_put(pScrn, &info->accel_state->cbuf); 129 info->accel_state->cbuf.vb_start_op = -1; 130 } 131 132 radeon_cs_emit(info->cs); 133 radeon_cs_erase(info->cs); 134 135 if (accel_state->use_vbos) 136 radeon_vbo_flush_bos(pScrn); 137 138 ret = radeon_cs_space_check_with_bo(info->cs, 139 accel_state->vbo.vb_bo, 140 RADEON_GEM_DOMAIN_GTT, 0); 141 if (ret) 142 ErrorF("space check failed in flush\n"); 143 144 if (info->reemit_current2d && info->state_2d.op) 145 info->reemit_current2d(pScrn, info->state_2d.op); 146 147 if (info->dri2.enabled) { 148 info->accel_state->XInited3D = FALSE; 149 info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN; 150 } 151 152} 153 154void radeon_ddx_cs_start(ScrnInfoPtr pScrn, 155 int n, const char *file, 156 const char *func, int line) 157{ 158 RADEONInfoPtr info = RADEONPTR(pScrn); 159 160 if (info->cs->cdw + n > info->cs->ndw) { 161 radeon_cs_flush_indirect(pScrn); 162 163 } 164 radeon_cs_begin(info->cs, n, file, func, line); 165} 166 167 168extern _X_EXPORT int gRADEONEntityIndex; 169 170static int getRADEONEntityIndex(void) 171{ 172 return gRADEONEntityIndex; 173} 174 175 176RADEONEntPtr RADEONEntPriv(ScrnInfoPtr pScrn) 177{ 178 DevUnion *pPriv; 179 RADEONInfoPtr info = RADEONPTR(pScrn); 180 pPriv = xf86GetEntityPrivate(info->pEnt->index, 181 getRADEONEntityIndex()); 182 return pPriv->ptr; 183} 184 185/* Allocate our private RADEONInfoRec */ 186static Bool RADEONGetRec(ScrnInfoPtr pScrn) 187{ 188 if (pScrn->driverPrivate) return TRUE; 189 190 pScrn->driverPrivate = xnfcalloc(sizeof(RADEONInfoRec), 1); 191 return TRUE; 192} 193 194/* Free our private RADEONInfoRec */ 195static void RADEONFreeRec(ScrnInfoPtr pScrn) 196{ 197 DevUnion *pPriv; 198 RADEONEntPtr pRADEONEnt; 199 RADEONInfoPtr info; 200 EntityInfoPtr pEnt; 201 202 if (!pScrn) 203 return; 204 205 info = RADEONPTR(pScrn); 206 if (info) { 207 if (info->fbcon_pixmap) 208 pScrn->pScreen->DestroyPixmap(info->fbcon_pixmap); 209 210 if (info->accel_state) { 211 free(info->accel_state); 212 info->accel_state = NULL; 213 } 214 215 pEnt = info->pEnt; 216 free(pScrn->driverPrivate); 217 pScrn->driverPrivate = NULL; 218 } else { 219 pEnt = xf86GetEntityInfo(pScrn->entityList[pScrn->numEntities - 1]); 220 } 221 222 pPriv = xf86GetEntityPrivate(pEnt->index, gRADEONEntityIndex); 223 pRADEONEnt = pPriv->ptr; 224 if (pRADEONEnt->fd > 0) { 225 DevUnion *pPriv; 226 RADEONEntPtr pRADEONEnt; 227 pPriv = xf86GetEntityPrivate(pScrn->entityList[0], 228 getRADEONEntityIndex()); 229 230 pRADEONEnt = pPriv->ptr; 231 pRADEONEnt->fd_ref--; 232 if (!pRADEONEnt->fd_ref) { 233#ifdef XF86_PDEV_SERVER_FD 234 if (!(pRADEONEnt->platform_dev && 235 pRADEONEnt->platform_dev->flags & XF86_PDEV_SERVER_FD)) 236#endif 237 drmClose(pRADEONEnt->fd); 238 free(pPriv->ptr); 239 pPriv->ptr = NULL; 240 } 241 } 242 243 free(pEnt); 244} 245 246static void * 247radeonShadowWindow(ScreenPtr screen, CARD32 row, CARD32 offset, int mode, 248 CARD32 *size, void *closure) 249{ 250 ScrnInfoPtr pScrn = xf86ScreenToScrn(screen); 251 RADEONInfoPtr info = RADEONPTR(pScrn); 252 int stride; 253 254 stride = (pScrn->displayWidth * pScrn->bitsPerPixel) / 8; 255 *size = stride; 256 257 return ((uint8_t *)info->front_bo->ptr + row * stride + offset); 258} 259 260static void 261radeonUpdatePacked(ScreenPtr pScreen, shadowBufPtr pBuf) 262{ 263 shadowUpdatePacked(pScreen, pBuf); 264} 265 266static Bool 267callback_needs_flush(RADEONInfoPtr info, struct radeon_client_priv *client_priv) 268{ 269 return (int)(client_priv->needs_flush - info->gpu_flushed) > 0; 270} 271 272static void 273radeon_event_callback(CallbackListPtr *list, 274 pointer user_data, pointer call_data) 275{ 276 EventInfoRec *eventinfo = call_data; 277 ScrnInfoPtr pScrn = user_data; 278 ScreenPtr pScreen = pScrn->pScreen; 279 struct radeon_client_priv *client_priv = 280 dixLookupScreenPrivate(&eventinfo->client->devPrivates, 281 &radeon_client_private_key, pScreen); 282 struct radeon_client_priv *server_priv = 283 dixLookupScreenPrivate(&serverClient->devPrivates, 284 &radeon_client_private_key, pScreen); 285 RADEONInfoPtr info = RADEONPTR(pScrn); 286 int i; 287 288 if (callback_needs_flush(info, client_priv) || 289 callback_needs_flush(info, server_priv)) 290 return; 291 292 /* Don't let gpu_flushed get too far ahead of needs_flush, in order 293 * to prevent false positives in callback_needs_flush() 294 */ 295 client_priv->needs_flush = info->gpu_flushed; 296 server_priv->needs_flush = info->gpu_flushed; 297 298 for (i = 0; i < eventinfo->count; i++) { 299 if (eventinfo->events[i].u.u.type == info->callback_event_type) { 300 client_priv->needs_flush++; 301 server_priv->needs_flush++; 302 return; 303 } 304 } 305} 306 307static void 308radeon_flush_callback(CallbackListPtr *list, 309 pointer user_data, pointer call_data) 310{ 311 ScrnInfoPtr pScrn = user_data; 312 ScreenPtr pScreen = pScrn->pScreen; 313 ClientPtr client = call_data ? call_data : serverClient; 314 struct radeon_client_priv *client_priv = 315 dixLookupScreenPrivate(&client->devPrivates, 316 &radeon_client_private_key, pScreen); 317 RADEONInfoPtr info = RADEONPTR(pScrn); 318 319 if (pScrn->vtSema && callback_needs_flush(info, client_priv)) 320 radeon_cs_flush_indirect(pScrn); 321} 322 323static Bool RADEONCreateScreenResources_KMS(ScreenPtr pScreen) 324{ 325 ExtensionEntry *damage_ext; 326 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); 327 RADEONInfoPtr info = RADEONPTR(pScrn); 328 PixmapPtr pixmap; 329 struct radeon_surface *surface; 330 331 pScreen->CreateScreenResources = info->CreateScreenResources; 332 if (!(*pScreen->CreateScreenResources)(pScreen)) 333 return FALSE; 334 pScreen->CreateScreenResources = RADEONCreateScreenResources_KMS; 335 336 /* Set the RandR primary output if Xorg hasn't */ 337 if (dixPrivateKeyRegistered(rrPrivKey)) { 338 rrScrPrivPtr rrScrPriv = rrGetScrPriv(pScreen); 339 340 if (!pScreen->isGPU && !rrScrPriv->primaryOutput) { 341 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 342 343 rrScrPriv->primaryOutput = xf86_config->output[0]->randr_output; 344 RROutputChanged(rrScrPriv->primaryOutput, FALSE); 345 rrScrPriv->layoutChanged = TRUE; 346 } 347 } 348 349 if (!drmmode_set_desired_modes(pScrn, &info->drmmode, pScreen->isGPU)) 350 return FALSE; 351 352 drmmode_uevent_init(pScrn, &info->drmmode); 353 354 if (info->r600_shadow_fb) { 355 pixmap = pScreen->GetScreenPixmap(pScreen); 356 357 if (!shadowAdd(pScreen, pixmap, radeonUpdatePacked, 358 radeonShadowWindow, 0, NULL)) 359 return FALSE; 360 } 361 362 if (info->dri2.enabled || info->use_glamor) { 363 if (info->front_bo) { 364 PixmapPtr pPix = pScreen->GetScreenPixmap(pScreen); 365 if (!radeon_set_pixmap_bo(pPix, info->front_bo)) 366 return FALSE; 367 surface = radeon_get_pixmap_surface(pPix); 368 if (surface) { 369 *surface = info->front_surface; 370 } 371 } 372 } 373 374 if (info->use_glamor) 375 radeon_glamor_create_screen_resources(pScreen); 376 377 info->callback_event_type = -1; 378 if (!pScreen->isGPU && (damage_ext = CheckExtension("DAMAGE"))) { 379 info->callback_event_type = damage_ext->eventBase + XDamageNotify; 380 381 if (!AddCallback(&FlushCallback, radeon_flush_callback, pScrn)) 382 return FALSE; 383 384 if (!AddCallback(&EventCallback, radeon_event_callback, pScrn)) { 385 DeleteCallback(&FlushCallback, radeon_flush_callback, pScrn); 386 return FALSE; 387 } 388 389 if (!dixRegisterScreenPrivateKey(&radeon_client_private_key, pScreen, 390 PRIVATE_CLIENT, sizeof(struct radeon_client_priv))) { 391 DeleteCallback(&FlushCallback, radeon_flush_callback, pScrn); 392 DeleteCallback(&EventCallback, radeon_event_callback, pScrn); 393 return FALSE; 394 } 395 } 396 397 return TRUE; 398} 399 400static Bool 401radeon_scanout_extents_intersect(xf86CrtcPtr xf86_crtc, BoxPtr extents) 402{ 403 if (xf86_crtc->scrn->is_gpu) { 404 extents->x1 -= xf86_crtc->x; 405 extents->y1 -= xf86_crtc->y; 406 extents->x2 -= xf86_crtc->x; 407 extents->y2 -= xf86_crtc->y; 408 } else { 409 extents->x1 -= xf86_crtc->filter_width >> 1; 410 extents->x2 += xf86_crtc->filter_width >> 1; 411 extents->y1 -= xf86_crtc->filter_height >> 1; 412 extents->y2 += xf86_crtc->filter_height >> 1; 413 pixman_f_transform_bounds(&xf86_crtc->f_framebuffer_to_crtc, extents); 414 } 415 416 extents->x1 = max(extents->x1, 0); 417 extents->y1 = max(extents->y1, 0); 418 extents->x2 = min(extents->x2, xf86_crtc->mode.HDisplay); 419 extents->y2 = min(extents->y2, xf86_crtc->mode.VDisplay); 420 421 return (extents->x1 < extents->x2 && extents->y1 < extents->y2); 422} 423 424static RegionPtr 425transform_region(RegionPtr region, struct pict_f_transform *transform, 426 int w, int h) 427{ 428 BoxPtr boxes = RegionRects(region); 429 int nboxes = RegionNumRects(region); 430 xRectanglePtr rects = malloc(nboxes * sizeof(*rects)); 431 RegionPtr transformed; 432 int nrects = 0; 433 BoxRec box; 434 int i; 435 436 for (i = 0; i < nboxes; i++) { 437 box.x1 = boxes[i].x1; 438 box.x2 = boxes[i].x2; 439 box.y1 = boxes[i].y1; 440 box.y2 = boxes[i].y2; 441 pixman_f_transform_bounds(transform, &box); 442 443 box.x1 = max(box.x1, 0); 444 box.y1 = max(box.y1, 0); 445 box.x2 = min(box.x2, w); 446 box.y2 = min(box.y2, h); 447 if (box.x1 >= box.x2 || box.y1 >= box.y2) 448 continue; 449 450 rects[nrects].x = box.x1; 451 rects[nrects].y = box.y1; 452 rects[nrects].width = box.x2 - box.x1; 453 rects[nrects].height = box.y2 - box.y1; 454 nrects++; 455 } 456 457 transformed = RegionFromRects(nrects, rects, CT_UNSORTED); 458 free(rects); 459 return transformed; 460} 461 462static void 463radeon_sync_scanout_pixmaps(xf86CrtcPtr xf86_crtc, RegionPtr new_region, 464 int scanout_id) 465{ 466 drmmode_crtc_private_ptr drmmode_crtc = xf86_crtc->driver_private; 467 DrawablePtr dst = &drmmode_crtc->scanout[scanout_id].pixmap->drawable; 468 DrawablePtr src = &drmmode_crtc->scanout[scanout_id ^ 1].pixmap->drawable; 469 RegionPtr last_region = &drmmode_crtc->scanout_last_region; 470 ScrnInfoPtr scrn = xf86_crtc->scrn; 471 ScreenPtr pScreen = scrn->pScreen; 472 RADEONInfoPtr info = RADEONPTR(scrn); 473 RegionRec remaining; 474 RegionPtr sync_region = NULL; 475 BoxRec extents; 476 Bool force; 477 GCPtr gc; 478 479 if (RegionNil(last_region)) 480 return; 481 482 RegionNull(&remaining); 483 RegionSubtract(&remaining, last_region, new_region); 484 if (RegionNil(&remaining)) 485 goto uninit; 486 487 extents = *RegionExtents(&remaining); 488 if (!radeon_scanout_extents_intersect(xf86_crtc, &extents)) 489 goto uninit; 490 491 if (xf86_crtc->driverIsPerformingTransform) { 492 sync_region = transform_region(&remaining, 493 &xf86_crtc->f_framebuffer_to_crtc, 494 dst->width, dst->height); 495 } else { 496 sync_region = RegionDuplicate(&remaining); 497 RegionTranslate(sync_region, -xf86_crtc->x, -xf86_crtc->y); 498 } 499 500 force = info->accel_state->force; 501 info->accel_state->force = TRUE; 502 503 gc = GetScratchGC(dst->depth, pScreen); 504 if (gc) { 505 gc->funcs->ChangeClip(gc, CT_REGION, sync_region, 0); 506 ValidateGC(dst, gc); 507 sync_region = NULL; 508 gc->ops->CopyArea(src, dst, gc, 0, 0, dst->width, dst->height, 0, 0); 509 FreeScratchGC(gc); 510 } 511 512 info->accel_state->force = force; 513 514 uninit: 515 if (sync_region) 516 RegionDestroy(sync_region); 517 RegionUninit(&remaining); 518} 519 520static void 521radeon_scanout_flip_abort(xf86CrtcPtr crtc, void *event_data) 522{ 523 RADEONEntPtr pRADEONEnt = RADEONEntPriv(crtc->scrn); 524 drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; 525 526 drmmode_crtc->scanout_update_pending = FALSE; 527 drmmode_fb_reference(pRADEONEnt->fd, &drmmode_crtc->flip_pending, 528 NULL); 529} 530 531static void 532radeon_scanout_flip_handler(xf86CrtcPtr crtc, uint32_t msc, uint64_t usec, 533 void *event_data) 534{ 535 RADEONEntPtr pRADEONEnt = RADEONEntPriv(crtc->scrn); 536 drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; 537 538 drmmode_fb_reference(pRADEONEnt->fd, &drmmode_crtc->fb, 539 drmmode_crtc->flip_pending); 540 radeon_scanout_flip_abort(crtc, event_data); 541 542#ifdef HAVE_PRESENT_H 543 if (drmmode_crtc->present_vblank_event_id) { 544 present_event_notify(drmmode_crtc->present_vblank_event_id, 545 drmmode_crtc->present_vblank_usec, 546 drmmode_crtc->present_vblank_msc); 547 drmmode_crtc->present_vblank_event_id = 0; 548 } 549#endif 550} 551 552 553static RegionPtr 554dirty_region(PixmapDirtyUpdatePtr dirty) 555{ 556 RegionPtr damageregion = DamageRegion(dirty->damage); 557 RegionPtr dstregion; 558 559#ifdef HAS_DIRTYTRACKING_ROTATION 560 if (dirty->rotation != RR_Rotate_0) { 561 dstregion = transform_region(damageregion, 562 &dirty->f_inverse, 563 dirty->slave_dst->drawable.width, 564 dirty->slave_dst->drawable.height); 565 } else 566#endif 567 { 568 RegionRec pixregion; 569 570 dstregion = RegionDuplicate(damageregion); 571 RegionTranslate(dstregion, -dirty->x, -dirty->y); 572 PixmapRegionInit(&pixregion, dirty->slave_dst); 573 RegionIntersect(dstregion, dstregion, &pixregion); 574 RegionUninit(&pixregion); 575 } 576 577 return dstregion; 578} 579 580static void 581redisplay_dirty(PixmapDirtyUpdatePtr dirty, RegionPtr region) 582{ 583 ScrnInfoPtr src_scrn = 584 xf86ScreenToScrn(radeon_dirty_src_drawable(dirty)->pScreen); 585 586 if (RegionNil(region)) 587 goto out; 588 589 if (dirty->slave_dst->master_pixmap) 590 DamageRegionAppend(&dirty->slave_dst->drawable, region); 591 592#ifdef HAS_DIRTYTRACKING_ROTATION 593 PixmapSyncDirtyHelper(dirty); 594#else 595 PixmapSyncDirtyHelper(dirty, region); 596#endif 597 598 radeon_cs_flush_indirect(src_scrn); 599 if (dirty->slave_dst->master_pixmap) 600 DamageRegionProcessPending(&dirty->slave_dst->drawable); 601 602out: 603 DamageEmpty(dirty->damage); 604} 605 606static void 607radeon_prime_scanout_update_abort(xf86CrtcPtr crtc, void *event_data) 608{ 609 drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; 610 611 drmmode_crtc->scanout_update_pending = FALSE; 612} 613 614void 615radeon_sync_shared_pixmap(PixmapDirtyUpdatePtr dirty) 616{ 617 ScreenPtr master_screen = radeon_dirty_master(dirty); 618 PixmapDirtyUpdatePtr ent; 619 RegionPtr region; 620 621 xorg_list_for_each_entry(ent, &master_screen->pixmap_dirty_list, ent) { 622 if (!radeon_dirty_src_equals(dirty, ent->slave_dst)) 623 continue; 624 625 region = dirty_region(ent); 626 redisplay_dirty(ent, region); 627 RegionDestroy(region); 628 } 629} 630 631 632#if HAS_SYNC_SHARED_PIXMAP 633 634static Bool 635master_has_sync_shared_pixmap(ScrnInfoPtr scrn, PixmapDirtyUpdatePtr dirty) 636{ 637 ScreenPtr master_screen = radeon_dirty_master(dirty); 638 639 return master_screen->SyncSharedPixmap != NULL; 640} 641 642static Bool 643slave_has_sync_shared_pixmap(ScrnInfoPtr scrn, PixmapDirtyUpdatePtr dirty) 644{ 645 ScreenPtr slave_screen = dirty->slave_dst->drawable.pScreen; 646 647 return slave_screen->SyncSharedPixmap != NULL; 648} 649 650static void 651call_sync_shared_pixmap(PixmapDirtyUpdatePtr dirty) 652{ 653 ScreenPtr master_screen = radeon_dirty_master(dirty); 654 655 master_screen->SyncSharedPixmap(dirty); 656} 657 658#else /* !HAS_SYNC_SHARED_PIXMAP */ 659 660static Bool 661master_has_sync_shared_pixmap(ScrnInfoPtr scrn, PixmapDirtyUpdatePtr dirty) 662{ 663 ScrnInfoPtr master_scrn = xf86ScreenToScrn(radeon_dirty_master(dirty)); 664 665 return master_scrn->driverName == scrn->driverName; 666} 667 668static Bool 669slave_has_sync_shared_pixmap(ScrnInfoPtr scrn, PixmapDirtyUpdatePtr dirty) 670{ 671 ScrnInfoPtr slave_scrn = xf86ScreenToScrn(dirty->slave_dst->drawable.pScreen); 672 673 return slave_scrn->driverName == scrn->driverName; 674} 675 676static void 677call_sync_shared_pixmap(PixmapDirtyUpdatePtr dirty) 678{ 679 radeon_sync_shared_pixmap(dirty); 680} 681 682#endif /* HAS_SYNC_SHARED_PIXMAPS */ 683 684 685static xf86CrtcPtr 686radeon_prime_dirty_to_crtc(PixmapDirtyUpdatePtr dirty) 687{ 688 ScreenPtr screen = dirty->slave_dst->drawable.pScreen; 689 ScrnInfoPtr scrn = xf86ScreenToScrn(screen); 690 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(scrn); 691 int c; 692 693 /* Find the CRTC which is scanning out from this slave pixmap */ 694 for (c = 0; c < xf86_config->num_crtc; c++) { 695 xf86CrtcPtr xf86_crtc = xf86_config->crtc[c]; 696 drmmode_crtc_private_ptr drmmode_crtc = xf86_crtc->driver_private; 697 698 if (radeon_dirty_src_equals(dirty, drmmode_crtc->prime_scanout_pixmap)) 699 return xf86_crtc; 700 } 701 702 return NULL; 703} 704 705static Bool 706radeon_prime_scanout_do_update(xf86CrtcPtr crtc, unsigned scanout_id) 707{ 708 ScrnInfoPtr scrn = crtc->scrn; 709 ScreenPtr screen = scrn->pScreen; 710 drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; 711 PixmapDirtyUpdatePtr dirty; 712 Bool ret = FALSE; 713 714 xorg_list_for_each_entry(dirty, &screen->pixmap_dirty_list, ent) { 715 if (radeon_dirty_src_equals(dirty, drmmode_crtc->prime_scanout_pixmap)) { 716 RegionPtr region; 717 718 if (master_has_sync_shared_pixmap(scrn, dirty)) 719 call_sync_shared_pixmap(dirty); 720 721 region = dirty_region(dirty); 722 if (RegionNil(region)) 723 goto destroy; 724 725 if (drmmode_crtc->tear_free) { 726 RegionTranslate(region, crtc->x, crtc->y); 727 radeon_sync_scanout_pixmaps(crtc, region, scanout_id); 728 radeon_cs_flush_indirect(scrn); 729 RegionCopy(&drmmode_crtc->scanout_last_region, region); 730 RegionTranslate(region, -crtc->x, -crtc->y); 731 dirty->slave_dst = drmmode_crtc->scanout[scanout_id].pixmap; 732 } 733 734 redisplay_dirty(dirty, region); 735 ret = TRUE; 736 destroy: 737 RegionDestroy(region); 738 break; 739 } 740 } 741 742 return ret; 743} 744 745static void 746radeon_prime_scanout_update_handler(xf86CrtcPtr crtc, uint32_t frame, uint64_t usec, 747 void *event_data) 748{ 749 drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; 750 751 radeon_prime_scanout_do_update(crtc, 0); 752 drmmode_crtc->scanout_update_pending = FALSE; 753} 754 755static void 756radeon_prime_scanout_update(PixmapDirtyUpdatePtr dirty) 757{ 758 ScreenPtr screen = dirty->slave_dst->drawable.pScreen; 759 ScrnInfoPtr scrn = xf86ScreenToScrn(screen); 760 xf86CrtcPtr xf86_crtc = radeon_prime_dirty_to_crtc(dirty); 761 drmmode_crtc_private_ptr drmmode_crtc; 762 uintptr_t drm_queue_seq; 763 764 if (!xf86_crtc || !xf86_crtc->enabled) 765 return; 766 767 drmmode_crtc = xf86_crtc->driver_private; 768 if (drmmode_crtc->scanout_update_pending || 769 !drmmode_crtc->scanout[drmmode_crtc->scanout_id].pixmap || 770 drmmode_crtc->dpms_mode != DPMSModeOn) 771 return; 772 773 drm_queue_seq = radeon_drm_queue_alloc(xf86_crtc, 774 RADEON_DRM_QUEUE_CLIENT_DEFAULT, 775 RADEON_DRM_QUEUE_ID_DEFAULT, NULL, 776 radeon_prime_scanout_update_handler, 777 radeon_prime_scanout_update_abort); 778 if (drm_queue_seq == RADEON_DRM_QUEUE_ERROR) { 779 xf86DrvMsg(scrn->scrnIndex, X_WARNING, 780 "radeon_drm_queue_alloc failed for PRIME update\n"); 781 return; 782 } 783 784 if (!drmmode_wait_vblank(xf86_crtc, DRM_VBLANK_RELATIVE | DRM_VBLANK_EVENT, 785 1, drm_queue_seq, NULL, NULL)) { 786 xf86DrvMsg(scrn->scrnIndex, X_WARNING, 787 "drmmode_wait_vblank failed for PRIME update: %s\n", 788 strerror(errno)); 789 radeon_drm_abort_entry(drm_queue_seq); 790 return; 791 } 792 793 drmmode_crtc->scanout_update_pending = TRUE; 794} 795 796static void 797radeon_prime_scanout_flip(PixmapDirtyUpdatePtr ent) 798{ 799 ScreenPtr screen = ent->slave_dst->drawable.pScreen; 800 ScrnInfoPtr scrn = xf86ScreenToScrn(screen); 801 RADEONEntPtr pRADEONEnt = RADEONEntPriv(scrn); 802 xf86CrtcPtr crtc = radeon_prime_dirty_to_crtc(ent); 803 drmmode_crtc_private_ptr drmmode_crtc; 804 uintptr_t drm_queue_seq; 805 unsigned scanout_id; 806 807 if (!crtc || !crtc->enabled) 808 return; 809 810 drmmode_crtc = crtc->driver_private; 811 if (drmmode_crtc->scanout_update_pending || 812 !drmmode_crtc->scanout[drmmode_crtc->scanout_id].pixmap || 813 drmmode_crtc->dpms_mode != DPMSModeOn) 814 return; 815 816 scanout_id = drmmode_crtc->scanout_id ^ 1; 817 if (!radeon_prime_scanout_do_update(crtc, scanout_id)) 818 return; 819 820 drm_queue_seq = radeon_drm_queue_alloc(crtc, 821 RADEON_DRM_QUEUE_CLIENT_DEFAULT, 822 RADEON_DRM_QUEUE_ID_DEFAULT, 823 NULL, 824 radeon_scanout_flip_handler, 825 radeon_scanout_flip_abort); 826 if (drm_queue_seq == RADEON_DRM_QUEUE_ERROR) { 827 xf86DrvMsg(scrn->scrnIndex, X_WARNING, 828 "Allocating DRM event queue entry failed for PRIME flip.\n"); 829 return; 830 } 831 832 drmmode_fb_reference(pRADEONEnt->fd, &drmmode_crtc->flip_pending, 833 radeon_pixmap_get_fb(drmmode_crtc->scanout[scanout_id].pixmap)); 834 if (!drmmode_crtc->flip_pending) { 835 xf86DrvMsg(scrn->scrnIndex, X_WARNING, 836 "Failed to get FB for PRIME flip.\n"); 837 radeon_drm_abort_entry(drm_queue_seq); 838 return; 839 } 840 841 if (drmmode_page_flip_target_relative(pRADEONEnt, drmmode_crtc, 842 drmmode_crtc->flip_pending->handle, 843 0, drm_queue_seq, 0) != 0) { 844 xf86DrvMsg(scrn->scrnIndex, X_WARNING, "flip queue failed in %s: %s\n", 845 __func__, strerror(errno)); 846 radeon_drm_abort_entry(drm_queue_seq); 847 return; 848 } 849 850 drmmode_crtc->scanout_id = scanout_id; 851 drmmode_crtc->scanout_update_pending = TRUE; 852} 853 854static void 855radeon_dirty_update(ScrnInfoPtr scrn) 856{ 857 ScreenPtr screen = scrn->pScreen; 858 PixmapDirtyUpdatePtr ent; 859 RegionPtr region; 860 861 xorg_list_for_each_entry(ent, &screen->pixmap_dirty_list, ent) { 862 if (screen->isGPU) { 863 PixmapDirtyUpdatePtr region_ent = ent; 864 865 if (master_has_sync_shared_pixmap(scrn, ent)) { 866 ScreenPtr master_screen = radeon_dirty_master(ent); 867 868 xorg_list_for_each_entry(region_ent, &master_screen->pixmap_dirty_list, ent) { 869 if (radeon_dirty_src_equals(ent, region_ent->slave_dst)) 870 break; 871 } 872 } 873 874 region = dirty_region(region_ent); 875 876 if (RegionNotEmpty(region)) { 877 xf86CrtcPtr crtc = radeon_prime_dirty_to_crtc(ent); 878 drmmode_crtc_private_ptr drmmode_crtc = NULL; 879 880 if (crtc) 881 drmmode_crtc = crtc->driver_private; 882 883 if (drmmode_crtc && drmmode_crtc->tear_free) 884 radeon_prime_scanout_flip(ent); 885 else 886 radeon_prime_scanout_update(ent); 887 } else { 888 DamageEmpty(region_ent->damage); 889 } 890 891 RegionDestroy(region); 892 } else { 893 if (slave_has_sync_shared_pixmap(scrn, ent)) 894 continue; 895 896 region = dirty_region(ent); 897 redisplay_dirty(ent, region); 898 RegionDestroy(region); 899 } 900 } 901} 902 903 904Bool 905radeon_scanout_do_update(xf86CrtcPtr xf86_crtc, int scanout_id, 906 PixmapPtr src_pix, BoxPtr extents) 907{ 908 drmmode_crtc_private_ptr drmmode_crtc = xf86_crtc->driver_private; 909 RegionRec region = { .extents = *extents, .data = NULL }; 910 ScrnInfoPtr scrn = xf86_crtc->scrn; 911 ScreenPtr pScreen = scrn->pScreen; 912 RADEONInfoPtr info = RADEONPTR(scrn); 913 DrawablePtr pDraw; 914 Bool force; 915 916 if (!xf86_crtc->enabled || 917 !drmmode_crtc->scanout[scanout_id].pixmap || 918 extents->x1 >= extents->x2 || extents->y1 >= extents->y2) 919 return FALSE; 920 921 pDraw = &drmmode_crtc->scanout[scanout_id].pixmap->drawable; 922 if (!radeon_scanout_extents_intersect(xf86_crtc, extents)) 923 return FALSE; 924 925 if (drmmode_crtc->tear_free) { 926 radeon_sync_scanout_pixmaps(xf86_crtc, ®ion, scanout_id); 927 RegionCopy(&drmmode_crtc->scanout_last_region, ®ion); 928 } 929 930 force = info->accel_state->force; 931 info->accel_state->force = TRUE; 932 933 if (xf86_crtc->driverIsPerformingTransform) { 934 SourceValidateProcPtr SourceValidate = pScreen->SourceValidate; 935 PictFormatPtr format = PictureWindowFormat(pScreen->root); 936 int error; 937 PicturePtr src, dst; 938 939 src = CreatePicture(None, &src_pix->drawable, format, 0L, NULL, 940 serverClient, &error); 941 if (!src) { 942 ErrorF("Failed to create source picture for transformed scanout " 943 "update\n"); 944 goto out; 945 } 946 947 dst = CreatePicture(None, pDraw, format, 0L, NULL, serverClient, &error); 948 if (!dst) { 949 ErrorF("Failed to create destination picture for transformed scanout " 950 "update\n"); 951 goto free_src; 952 } 953 954 error = SetPictureTransform(src, &xf86_crtc->crtc_to_framebuffer); 955 if (error) { 956 ErrorF("SetPictureTransform failed for transformed scanout " 957 "update\n"); 958 goto free_dst; 959 } 960 961 if (xf86_crtc->filter) 962 SetPicturePictFilter(src, xf86_crtc->filter, xf86_crtc->params, 963 xf86_crtc->nparams); 964 965 pScreen->SourceValidate = NULL; 966 CompositePicture(PictOpSrc, 967 src, NULL, dst, 968 extents->x1, extents->y1, 0, 0, extents->x1, 969 extents->y1, extents->x2 - extents->x1, 970 extents->y2 - extents->y1); 971 pScreen->SourceValidate = SourceValidate; 972 973 free_dst: 974 FreePicture(dst, None); 975 free_src: 976 FreePicture(src, None); 977 } else 978 out: 979 { 980 GCPtr gc = GetScratchGC(pDraw->depth, pScreen); 981 982 ValidateGC(pDraw, gc); 983 (*gc->ops->CopyArea)(&src_pix->drawable, pDraw, gc, 984 xf86_crtc->x + extents->x1, xf86_crtc->y + extents->y1, 985 extents->x2 - extents->x1, extents->y2 - extents->y1, 986 extents->x1, extents->y1); 987 FreeScratchGC(gc); 988 } 989 990 radeon_cs_flush_indirect(scrn); 991 992 info->accel_state->force = force; 993 994 return TRUE; 995} 996 997static void 998radeon_scanout_update_abort(xf86CrtcPtr crtc, void *event_data) 999{ 1000 drmmode_crtc_private_ptr drmmode_crtc = event_data; 1001 1002 drmmode_crtc->scanout_update_pending = FALSE; 1003} 1004 1005static void 1006radeon_scanout_update_handler(xf86CrtcPtr crtc, uint32_t frame, uint64_t usec, 1007 void *event_data) 1008{ 1009 drmmode_crtc_private_ptr drmmode_crtc = event_data; 1010 ScreenPtr screen = crtc->scrn->pScreen; 1011 RegionPtr region = DamageRegion(drmmode_crtc->scanout_damage); 1012 1013 if (crtc->enabled && 1014 !drmmode_crtc->flip_pending && 1015 drmmode_crtc->dpms_mode == DPMSModeOn) { 1016 if (radeon_scanout_do_update(crtc, drmmode_crtc->scanout_id, 1017 screen->GetWindowPixmap(screen->root), 1018 ®ion->extents)) 1019 RegionEmpty(region); 1020 } 1021 1022 radeon_scanout_update_abort(crtc, event_data); 1023} 1024 1025static void 1026radeon_scanout_update(xf86CrtcPtr xf86_crtc) 1027{ 1028 drmmode_crtc_private_ptr drmmode_crtc = xf86_crtc->driver_private; 1029 uintptr_t drm_queue_seq; 1030 ScrnInfoPtr scrn; 1031 DamagePtr pDamage; 1032 RegionPtr pRegion; 1033 BoxRec extents; 1034 1035 if (!xf86_crtc->enabled || 1036 drmmode_crtc->scanout_update_pending || 1037 drmmode_crtc->flip_pending || 1038 drmmode_crtc->dpms_mode != DPMSModeOn) 1039 return; 1040 1041 pDamage = drmmode_crtc->scanout_damage; 1042 if (!pDamage) 1043 return; 1044 1045 pRegion = DamageRegion(pDamage); 1046 if (!RegionNotEmpty(pRegion)) 1047 return; 1048 1049 extents = *RegionExtents(pRegion); 1050 if (!radeon_scanout_extents_intersect(xf86_crtc, &extents)) { 1051 RegionEmpty(pRegion); 1052 return; 1053 } 1054 1055 scrn = xf86_crtc->scrn; 1056 drm_queue_seq = radeon_drm_queue_alloc(xf86_crtc, 1057 RADEON_DRM_QUEUE_CLIENT_DEFAULT, 1058 RADEON_DRM_QUEUE_ID_DEFAULT, 1059 drmmode_crtc, 1060 radeon_scanout_update_handler, 1061 radeon_scanout_update_abort); 1062 if (drm_queue_seq == RADEON_DRM_QUEUE_ERROR) { 1063 xf86DrvMsg(scrn->scrnIndex, X_WARNING, 1064 "radeon_drm_queue_alloc failed for scanout update\n"); 1065 return; 1066 } 1067 1068 if (!drmmode_wait_vblank(xf86_crtc, DRM_VBLANK_RELATIVE | DRM_VBLANK_EVENT, 1069 1, drm_queue_seq, NULL, NULL)) { 1070 xf86DrvMsg(scrn->scrnIndex, X_WARNING, 1071 "drmmode_wait_vblank failed for scanout update: %s\n", 1072 strerror(errno)); 1073 radeon_drm_abort_entry(drm_queue_seq); 1074 return; 1075 } 1076 1077 drmmode_crtc->scanout_update_pending = TRUE; 1078} 1079 1080static void 1081radeon_scanout_flip(ScreenPtr pScreen, RADEONInfoPtr info, 1082 xf86CrtcPtr xf86_crtc) 1083{ 1084 drmmode_crtc_private_ptr drmmode_crtc = xf86_crtc->driver_private; 1085 RegionPtr region = DamageRegion(drmmode_crtc->scanout_damage); 1086 ScrnInfoPtr scrn = xf86_crtc->scrn; 1087 RADEONEntPtr pRADEONEnt = RADEONEntPriv(scrn); 1088 uintptr_t drm_queue_seq; 1089 unsigned scanout_id; 1090 1091 if (drmmode_crtc->scanout_update_pending || 1092 drmmode_crtc->flip_pending || 1093 drmmode_crtc->dpms_mode != DPMSModeOn) 1094 return; 1095 1096 scanout_id = drmmode_crtc->scanout_id ^ 1; 1097 if (!radeon_scanout_do_update(xf86_crtc, scanout_id, 1098 pScreen->GetWindowPixmap(pScreen->root), 1099 ®ion->extents)) 1100 return; 1101 RegionEmpty(region); 1102 1103 drm_queue_seq = radeon_drm_queue_alloc(xf86_crtc, 1104 RADEON_DRM_QUEUE_CLIENT_DEFAULT, 1105 RADEON_DRM_QUEUE_ID_DEFAULT, 1106 NULL, 1107 radeon_scanout_flip_handler, 1108 radeon_scanout_flip_abort); 1109 if (drm_queue_seq == RADEON_DRM_QUEUE_ERROR) { 1110 xf86DrvMsg(scrn->scrnIndex, X_WARNING, 1111 "Allocating DRM event queue entry failed.\n"); 1112 return; 1113 } 1114 1115 drmmode_fb_reference(pRADEONEnt->fd, &drmmode_crtc->flip_pending, 1116 radeon_pixmap_get_fb(drmmode_crtc->scanout[scanout_id].pixmap)); 1117 if (!drmmode_crtc->flip_pending) { 1118 xf86DrvMsg(scrn->scrnIndex, X_WARNING, 1119 "Failed to get FB for scanout flip.\n"); 1120 radeon_drm_abort_entry(drm_queue_seq); 1121 return; 1122 } 1123 1124 if (drmmode_page_flip_target_relative(pRADEONEnt, drmmode_crtc, 1125 drmmode_crtc->flip_pending->handle, 1126 0, drm_queue_seq, 0) != 0) { 1127 xf86DrvMsg(scrn->scrnIndex, X_WARNING, "flip queue failed in %s: %s, " 1128 "TearFree inactive until next modeset\n", 1129 __func__, strerror(errno)); 1130 radeon_drm_abort_entry(drm_queue_seq); 1131 RegionCopy(DamageRegion(drmmode_crtc->scanout_damage), 1132 &drmmode_crtc->scanout_last_region); 1133 RegionEmpty(&drmmode_crtc->scanout_last_region); 1134 radeon_scanout_update(xf86_crtc); 1135 drmmode_crtc_scanout_destroy(drmmode_crtc->drmmode, 1136 &drmmode_crtc->scanout[scanout_id]); 1137 drmmode_crtc->tear_free = FALSE; 1138 return; 1139 } 1140 1141 drmmode_crtc->scanout_id = scanout_id; 1142 drmmode_crtc->scanout_update_pending = TRUE; 1143} 1144 1145static void RADEONBlockHandler_KMS(BLOCKHANDLER_ARGS_DECL) 1146{ 1147 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); 1148 RADEONInfoPtr info = RADEONPTR(pScrn); 1149 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 1150 int c; 1151 1152 pScreen->BlockHandler = info->BlockHandler; 1153 (*pScreen->BlockHandler) (BLOCKHANDLER_ARGS); 1154 pScreen->BlockHandler = RADEONBlockHandler_KMS; 1155 1156 if (!xf86ScreenToScrn(radeon_master_screen(pScreen))->vtSema) 1157 return; 1158 1159 if (!pScreen->isGPU) 1160 { 1161 for (c = 0; c < xf86_config->num_crtc; c++) { 1162 xf86CrtcPtr crtc = xf86_config->crtc[c]; 1163 drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; 1164 1165 if (drmmode_crtc->tear_free) 1166 radeon_scanout_flip(pScreen, info, crtc); 1167 else if (drmmode_crtc->scanout[drmmode_crtc->scanout_id].pixmap) 1168 radeon_scanout_update(crtc); 1169 } 1170 } 1171 1172 radeon_cs_flush_indirect(pScrn); 1173 1174 radeon_dirty_update(pScrn); 1175} 1176 1177static Bool RADEONIsFastFBWorking(ScrnInfoPtr pScrn) 1178{ 1179 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 1180 struct drm_radeon_info ginfo; 1181 int r; 1182 uint32_t tmp = 0; 1183 1184 memset(&ginfo, 0, sizeof(ginfo)); 1185 ginfo.request = RADEON_INFO_FASTFB_WORKING; 1186 ginfo.value = (uintptr_t)&tmp; 1187 r = drmCommandWriteRead(pRADEONEnt->fd, DRM_RADEON_INFO, &ginfo, sizeof(ginfo)); 1188 if (r) { 1189 return FALSE; 1190 } 1191 if (tmp == 1) 1192 return TRUE; 1193 return FALSE; 1194} 1195 1196static Bool RADEONIsFusionGARTWorking(ScrnInfoPtr pScrn) 1197{ 1198 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 1199 struct drm_radeon_info ginfo; 1200 int r; 1201 uint32_t tmp; 1202 1203 memset(&ginfo, 0, sizeof(ginfo)); 1204 ginfo.request = RADEON_INFO_FUSION_GART_WORKING; 1205 ginfo.value = (uintptr_t)&tmp; 1206 r = drmCommandWriteRead(pRADEONEnt->fd, DRM_RADEON_INFO, &ginfo, sizeof(ginfo)); 1207 if (r) { 1208 return FALSE; 1209 } 1210 if (tmp == 1) 1211 return TRUE; 1212 return FALSE; 1213} 1214 1215static Bool RADEONIsAccelWorking(ScrnInfoPtr pScrn) 1216{ 1217 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 1218 RADEONInfoPtr info = RADEONPTR(pScrn); 1219 struct drm_radeon_info ginfo; 1220 int r; 1221 uint32_t tmp; 1222 1223 memset(&ginfo, 0, sizeof(ginfo)); 1224 if (info->dri2.pKernelDRMVersion->version_minor >= 5) 1225 ginfo.request = RADEON_INFO_ACCEL_WORKING2; 1226 else 1227 ginfo.request = RADEON_INFO_ACCEL_WORKING; 1228 ginfo.value = (uintptr_t)&tmp; 1229 r = drmCommandWriteRead(pRADEONEnt->fd, DRM_RADEON_INFO, &ginfo, sizeof(ginfo)); 1230 if (r) { 1231 /* If kernel is too old before 2.6.32 than assume accel is working */ 1232 if (r == -EINVAL) { 1233 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Kernel too old missing accel " 1234 "information, assuming accel is working\n"); 1235 return TRUE; 1236 } 1237 return FALSE; 1238 } 1239 if (info->ChipFamily == CHIP_FAMILY_HAWAII) { 1240 if (tmp == 2 || tmp == 3) 1241 return TRUE; 1242 } else if (tmp) { 1243 return TRUE; 1244 } 1245 return FALSE; 1246} 1247 1248/* This is called by RADEONPreInit to set up the default visual */ 1249static Bool RADEONPreInitVisual(ScrnInfoPtr pScrn) 1250{ 1251 RADEONInfoPtr info = RADEONPTR(pScrn); 1252 1253 if (!xf86SetDepthBpp(pScrn, 0, 0, 0, Support32bppFb)) 1254 return FALSE; 1255 1256 switch (pScrn->depth) { 1257 case 8: 1258 case 15: 1259 case 16: 1260 case 24: 1261 case 30: 1262 break; 1263 1264 default: 1265 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1266 "Given depth (%d) is not supported by %s driver\n", 1267 pScrn->depth, RADEON_DRIVER_NAME); 1268 return FALSE; 1269 } 1270 1271 xf86PrintDepthBpp(pScrn); 1272 1273 info->pix24bpp = xf86GetBppFromDepth(pScrn, 1274 pScrn->depth); 1275 info->pixel_bytes = pScrn->bitsPerPixel / 8; 1276 1277 if (info->pix24bpp == 24) { 1278 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1279 "Radeon does NOT support 24bpp\n"); 1280 return FALSE; 1281 } 1282 1283 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1284 "Pixel depth = %d bits stored in %d byte%s (%d bpp pixmaps)\n", 1285 pScrn->depth, 1286 info->pixel_bytes, 1287 info->pixel_bytes > 1 ? "s" : "", 1288 info->pix24bpp); 1289 1290 if (!xf86SetDefaultVisual(pScrn, -1)) return FALSE; 1291 1292 if (pScrn->depth > 8 && pScrn->defaultVisual != TrueColor) { 1293 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1294 "Default visual (%s) is not supported at depth %d\n", 1295 xf86GetVisualName(pScrn->defaultVisual), pScrn->depth); 1296 return FALSE; 1297 } 1298 return TRUE; 1299} 1300 1301/* This is called by RADEONPreInit to handle all color weight issues */ 1302static Bool RADEONPreInitWeight(ScrnInfoPtr pScrn) 1303{ 1304 RADEONInfoPtr info = RADEONPTR(pScrn); 1305 1306 /* Save flag for 6 bit DAC to use for 1307 setting CRTC registers. Otherwise use 1308 an 8 bit DAC, even if xf86SetWeight sets 1309 pScrn->rgbBits to some value other than 1310 8. */ 1311 info->dac6bits = FALSE; 1312 1313 if (pScrn->depth > 8) { 1314 rgb defaultWeight = { 0, 0, 0 }; 1315 1316 if (!xf86SetWeight(pScrn, defaultWeight, defaultWeight)) return FALSE; 1317 } else { 1318 pScrn->rgbBits = 8; 1319 } 1320 1321 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1322 "Using %d bits per RGB (%d bit DAC)\n", 1323 pScrn->rgbBits, info->dac6bits ? 6 : 8); 1324 1325 return TRUE; 1326} 1327 1328static Bool RADEONPreInitAccel_KMS(ScrnInfoPtr pScrn) 1329{ 1330 RADEONInfoPtr info = RADEONPTR(pScrn); 1331 1332 if (!(info->accel_state = calloc(1, sizeof(struct radeon_accel_state)))) { 1333 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unable to allocate accel_state rec!\n"); 1334 return FALSE; 1335 } 1336 1337 /* Check whether direct mapping is used for fast fb access*/ 1338 if (RADEONIsFastFBWorking(pScrn)) { 1339 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct mapping of fb aperture is enabled for fast fb access.\n"); 1340 info->is_fast_fb = TRUE; 1341 } 1342 1343 if (!xf86ReturnOptValBool(info->Options, OPTION_ACCEL, TRUE) || 1344 (!RADEONIsAccelWorking(pScrn))) { 1345 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1346 "GPU accel disabled or not working, using shadowfb for KMS\n"); 1347shadowfb: 1348 if (!xf86LoadSubModule(pScrn, "shadow")) 1349 return FALSE; 1350 1351 info->r600_shadow_fb = TRUE; 1352 return TRUE; 1353 } 1354 1355#ifdef DRI2 1356 info->dri2.available = !!xf86LoadSubModule(pScrn, "dri2"); 1357#endif 1358 1359 if (radeon_glamor_pre_init(pScrn)) 1360 return TRUE; 1361 1362 if (info->ChipFamily >= CHIP_FAMILY_TAHITI) { 1363 goto shadowfb; 1364 } else if (info->ChipFamily == CHIP_FAMILY_PALM) { 1365 info->accel_state->allowHWDFS = RADEONIsFusionGARTWorking(pScrn); 1366 } else 1367 info->accel_state->allowHWDFS = TRUE; 1368 1369 if ((info->ChipFamily == CHIP_FAMILY_RS100) || 1370 (info->ChipFamily == CHIP_FAMILY_RS200) || 1371 (info->ChipFamily == CHIP_FAMILY_RS300) || 1372 (info->ChipFamily == CHIP_FAMILY_RS400) || 1373 (info->ChipFamily == CHIP_FAMILY_RS480) || 1374 (info->ChipFamily == CHIP_FAMILY_RS600) || 1375 (info->ChipFamily == CHIP_FAMILY_RS690) || 1376 (info->ChipFamily == CHIP_FAMILY_RS740)) 1377 info->accel_state->has_tcl = FALSE; 1378 else { 1379 info->accel_state->has_tcl = TRUE; 1380 } 1381 1382 { 1383 int errmaj = 0, errmin = 0; 1384 info->exaReq.majorversion = EXA_VERSION_MAJOR; 1385 info->exaReq.minorversion = EXA_VERSION_MINOR; 1386 if (!LoadSubModule(pScrn->module, "exa", NULL, NULL, NULL, 1387 &info->exaReq, &errmaj, &errmin)) { 1388 LoaderErrorMsg(NULL, "exa", errmaj, errmin); 1389 return FALSE; 1390 } 1391 } 1392 1393 return TRUE; 1394} 1395 1396static Bool RADEONPreInitChipType_KMS(ScrnInfoPtr pScrn) 1397{ 1398 RADEONInfoPtr info = RADEONPTR(pScrn); 1399 int i; 1400 1401 info->Chipset = PCI_DEV_DEVICE_ID(info->PciInfo); 1402 pScrn->chipset = (char *)xf86TokenToString(RADEONChipsets, info->Chipset); 1403 if (!pScrn->chipset) { 1404 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1405 "ChipID 0x%04x is not recognized\n", info->Chipset); 1406 return FALSE; 1407 } 1408 1409 if (info->Chipset < 0) { 1410 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1411 "Chipset \"%s\" is not recognized\n", pScrn->chipset); 1412 return FALSE; 1413 } 1414 xf86DrvMsg(pScrn->scrnIndex, X_PROBED, 1415 "Chipset: \"%s\" (ChipID = 0x%04x)\n", 1416 pScrn->chipset, 1417 info->Chipset); 1418 1419 for (i = 0; i < sizeof(RADEONCards) / sizeof(RADEONCardInfo); i++) { 1420 if (info->Chipset == RADEONCards[i].pci_device_id) { 1421 RADEONCardInfo *card = &RADEONCards[i]; 1422 info->ChipFamily = card->chip_family; 1423 break; 1424 } 1425 } 1426 1427#ifdef RENDER 1428 info->RenderAccel = xf86ReturnOptValBool(info->Options, OPTION_RENDER_ACCEL, 1429 info->Chipset != PCI_CHIP_RN50_515E && 1430 info->Chipset != PCI_CHIP_RN50_5969); 1431#endif 1432 return TRUE; 1433} 1434 1435static int radeon_get_drm_master_fd(ScrnInfoPtr pScrn) 1436{ 1437 RADEONInfoPtr info = RADEONPTR(pScrn); 1438#ifdef XF86_PDEV_SERVER_FD 1439 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 1440#endif 1441 struct pci_device *dev = info->PciInfo; 1442 char *busid; 1443 int fd; 1444 1445#ifdef XF86_PDEV_SERVER_FD 1446 if (pRADEONEnt->platform_dev) { 1447 fd = xf86_get_platform_device_int_attrib(pRADEONEnt->platform_dev, 1448 ODEV_ATTRIB_FD, -1); 1449 if (fd != -1) 1450 return fd; 1451 } 1452#endif 1453 1454 XNFasprintf(&busid, "pci:%04x:%02x:%02x.%d", 1455 dev->domain, dev->bus, dev->dev, dev->func); 1456 1457 fd = drmOpen(NULL, busid); 1458 if (fd == -1) 1459 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1460 "[drm] Failed to open DRM device for %s: %s\n", 1461 busid, strerror(errno)); 1462 1463 free(busid); 1464 return fd; 1465} 1466 1467static Bool radeon_open_drm_master(ScrnInfoPtr pScrn) 1468{ 1469 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 1470 drmSetVersion sv; 1471 int err; 1472 1473 if (pRADEONEnt->fd) { 1474 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1475 " reusing fd for second head\n"); 1476 pRADEONEnt->fd_ref++; 1477 return TRUE; 1478 } 1479 1480 pRADEONEnt->fd = radeon_get_drm_master_fd(pScrn); 1481 if (pRADEONEnt->fd == -1) 1482 return FALSE; 1483 1484 /* Check that what we opened was a master or a master-capable FD, 1485 * by setting the version of the interface we'll use to talk to it. 1486 * (see DRIOpenDRMMaster() in DRI1) 1487 */ 1488 sv.drm_di_major = 1; 1489 sv.drm_di_minor = 1; 1490 sv.drm_dd_major = -1; 1491 sv.drm_dd_minor = -1; 1492 err = drmSetInterfaceVersion(pRADEONEnt->fd, &sv); 1493 if (err != 0) { 1494 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1495 "[drm] failed to set drm interface version.\n"); 1496 drmClose(pRADEONEnt->fd); 1497 pRADEONEnt->fd = -1; 1498 1499 return FALSE; 1500 } 1501 1502 pRADEONEnt->fd_ref = 1; 1503 return TRUE; 1504} 1505 1506static Bool r600_get_tile_config(ScrnInfoPtr pScrn) 1507{ 1508 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 1509 RADEONInfoPtr info = RADEONPTR(pScrn); 1510 struct drm_radeon_info ginfo; 1511 int r; 1512 uint32_t tmp; 1513 1514 if (info->ChipFamily < CHIP_FAMILY_R600) 1515 return FALSE; 1516 1517 memset(&ginfo, 0, sizeof(ginfo)); 1518 ginfo.request = RADEON_INFO_TILING_CONFIG; 1519 ginfo.value = (uintptr_t)&tmp; 1520 r = drmCommandWriteRead(pRADEONEnt->fd, DRM_RADEON_INFO, &ginfo, sizeof(ginfo)); 1521 if (r) 1522 return FALSE; 1523 1524 info->tile_config = tmp; 1525 info->r7xx_bank_op = 0; 1526 if (info->ChipFamily >= CHIP_FAMILY_CEDAR) { 1527 if (info->dri2.pKernelDRMVersion->version_minor >= 7) { 1528 switch (info->tile_config & 0xf) { 1529 case 0: 1530 info->num_channels = 1; 1531 break; 1532 case 1: 1533 info->num_channels = 2; 1534 break; 1535 case 2: 1536 info->num_channels = 4; 1537 break; 1538 case 3: 1539 info->num_channels = 8; 1540 break; 1541 default: 1542 return FALSE; 1543 } 1544 1545 switch((info->tile_config & 0xf0) >> 4) { 1546 case 0: 1547 info->num_banks = 4; 1548 break; 1549 case 1: 1550 info->num_banks = 8; 1551 break; 1552 case 2: 1553 info->num_banks = 16; 1554 break; 1555 default: 1556 return FALSE; 1557 } 1558 1559 switch ((info->tile_config & 0xf00) >> 8) { 1560 case 0: 1561 info->group_bytes = 256; 1562 break; 1563 case 1: 1564 info->group_bytes = 512; 1565 break; 1566 default: 1567 return FALSE; 1568 } 1569 } else 1570 return FALSE; 1571 } else { 1572 switch((info->tile_config & 0xe) >> 1) { 1573 case 0: 1574 info->num_channels = 1; 1575 break; 1576 case 1: 1577 info->num_channels = 2; 1578 break; 1579 case 2: 1580 info->num_channels = 4; 1581 break; 1582 case 3: 1583 info->num_channels = 8; 1584 break; 1585 default: 1586 return FALSE; 1587 } 1588 switch((info->tile_config & 0x30) >> 4) { 1589 case 0: 1590 info->num_banks = 4; 1591 break; 1592 case 1: 1593 info->num_banks = 8; 1594 break; 1595 default: 1596 return FALSE; 1597 } 1598 switch((info->tile_config & 0xc0) >> 6) { 1599 case 0: 1600 info->group_bytes = 256; 1601 break; 1602 case 1: 1603 info->group_bytes = 512; 1604 break; 1605 default: 1606 return FALSE; 1607 } 1608 } 1609 1610 info->have_tiling_info = TRUE; 1611 return TRUE; 1612} 1613 1614static void RADEONSetupCapabilities(ScrnInfoPtr pScrn) 1615{ 1616 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 1617 RADEONInfoPtr info = RADEONPTR(pScrn); 1618 uint64_t value; 1619 int ret; 1620 1621 pScrn->capabilities = 0; 1622 1623 /* PRIME offloading requires acceleration */ 1624 if (info->r600_shadow_fb) 1625 return; 1626 1627 ret = drmGetCap(pRADEONEnt->fd, DRM_CAP_PRIME, &value); 1628 if (ret == 0) { 1629 if (value & DRM_PRIME_CAP_EXPORT) 1630 pScrn->capabilities |= RR_Capability_SourceOutput | RR_Capability_SourceOffload; 1631 if (value & DRM_PRIME_CAP_IMPORT) { 1632 pScrn->capabilities |= RR_Capability_SinkOffload; 1633 if (info->drmmode.count_crtcs) 1634 pScrn->capabilities |= RR_Capability_SinkOutput; 1635 } 1636 } 1637} 1638 1639/* When the root window is created, initialize the screen contents from 1640 * console if -background none was specified on the command line 1641 */ 1642static Bool RADEONCreateWindow_oneshot(WindowPtr pWin) 1643{ 1644 ScreenPtr pScreen = pWin->drawable.pScreen; 1645 ScrnInfoPtr pScrn; 1646 RADEONInfoPtr info; 1647 Bool ret; 1648 1649 if (pWin != pScreen->root) 1650 ErrorF("%s called for non-root window %p\n", __func__, pWin); 1651 1652 pScrn = xf86ScreenToScrn(pScreen); 1653 info = RADEONPTR(pScrn); 1654 pScreen->CreateWindow = info->CreateWindow; 1655 ret = pScreen->CreateWindow(pWin); 1656 1657 if (ret) 1658 drmmode_copy_fb(pScrn, &info->drmmode); 1659 1660 return ret; 1661} 1662 1663/* When the root window is mapped, set the initial modes */ 1664void RADEONWindowExposures_oneshot(WindowPtr pWin, RegionPtr pRegion 1665#if XORG_VERSION_CURRENT < XORG_VERSION_NUMERIC(1,16,99,901,0) 1666 , RegionPtr pBSRegion 1667#endif 1668 ) 1669{ 1670 ScreenPtr pScreen = pWin->drawable.pScreen; 1671 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); 1672 RADEONInfoPtr info = RADEONPTR(pScrn); 1673 1674 if (pWin != pScreen->root) 1675 ErrorF("%s called for non-root window %p\n", __func__, pWin); 1676 1677 pScreen->WindowExposures = info->WindowExposures; 1678#if XORG_VERSION_CURRENT < XORG_VERSION_NUMERIC(1,16,99,901,0) 1679 pScreen->WindowExposures(pWin, pRegion, pBSRegion); 1680#else 1681 pScreen->WindowExposures(pWin, pRegion); 1682#endif 1683 1684 radeon_cs_flush_indirect(pScrn); 1685 radeon_bo_wait(info->front_bo); 1686 drmmode_set_desired_modes(pScrn, &info->drmmode, TRUE); 1687} 1688 1689Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int flags) 1690{ 1691 RADEONInfoPtr info; 1692 RADEONEntPtr pRADEONEnt; 1693 MessageType from; 1694 DevUnion* pPriv; 1695 Gamma zeros = { 0.0, 0.0, 0.0 }; 1696 uint32_t tiling = 0; 1697 int cpp; 1698 1699 if (flags & PROBE_DETECT) 1700 return TRUE; 1701 1702 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 1703 "RADEONPreInit_KMS\n"); 1704 if (pScrn->numEntities != 1) return FALSE; 1705 if (!RADEONGetRec(pScrn)) return FALSE; 1706 1707 info = RADEONPTR(pScrn); 1708 info->IsSecondary = FALSE; 1709 info->pEnt = xf86GetEntityInfo(pScrn->entityList[pScrn->numEntities - 1]); 1710 if (info->pEnt->location.type != BUS_PCI 1711#ifdef XSERVER_PLATFORM_BUS 1712 && info->pEnt->location.type != BUS_PLATFORM 1713#endif 1714 ) 1715 return FALSE; 1716 1717 pPriv = xf86GetEntityPrivate(pScrn->entityList[0], 1718 getRADEONEntityIndex()); 1719 pRADEONEnt = pPriv->ptr; 1720 1721 if(xf86IsEntityShared(pScrn->entityList[0])) 1722 { 1723 if(xf86IsPrimInitDone(pScrn->entityList[0])) 1724 { 1725 info->IsSecondary = TRUE; 1726 } 1727 else 1728 { 1729 xf86SetPrimInitDone(pScrn->entityList[0]); 1730 } 1731 } 1732 1733 if (info->IsSecondary) 1734 pRADEONEnt->secondary_scrn = pScrn; 1735 else 1736 pRADEONEnt->primary_scrn = pScrn; 1737 1738 info->PciInfo = xf86GetPciInfoForEntity(info->pEnt->index); 1739 pScrn->monitor = pScrn->confScreen->monitor; 1740 1741 if (!RADEONPreInitVisual(pScrn)) 1742 return FALSE; 1743 1744 xf86CollectOptions(pScrn, NULL); 1745 if (!(info->Options = malloc(sizeof(RADEONOptions_KMS)))) 1746 return FALSE; 1747 1748 memcpy(info->Options, RADEONOptions_KMS, sizeof(RADEONOptions_KMS)); 1749 xf86ProcessOptions(pScrn->scrnIndex, pScrn->options, info->Options); 1750 1751 if (!RADEONPreInitWeight(pScrn)) 1752 return FALSE; 1753 1754 if (!RADEONPreInitChipType_KMS(pScrn)) 1755 return FALSE; 1756 1757 if (radeon_open_drm_master(pScrn) == FALSE) { 1758 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Kernel modesetting setup failed\n"); 1759 return FALSE; 1760 } 1761 1762 info->dri2.available = FALSE; 1763 info->dri2.enabled = FALSE; 1764 info->dri2.pKernelDRMVersion = drmGetVersion(pRADEONEnt->fd); 1765 if (info->dri2.pKernelDRMVersion == NULL) { 1766 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1767 "RADEONDRIGetVersion failed to get the DRM version\n"); 1768 return FALSE; 1769 } 1770 1771 /* Get ScreenInit function */ 1772 if (!xf86LoadSubModule(pScrn, "fb")) 1773 return FALSE; 1774 1775 if (!RADEONPreInitAccel_KMS(pScrn)) 1776 return FALSE; 1777 1778 /* Depth 30 only supported since Linux 3.16 / kms driver minor version 39 */ 1779 if (pScrn->depth == 30 && info->dri2.pKernelDRMVersion->version_minor < 39) { 1780 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1781 "Depth 30 is not supported. Kernel too old. Needs Linux 3.16+\n"); 1782 return FALSE; 1783 } 1784 1785 radeon_drm_queue_init(); 1786 1787 info->allowColorTiling2D = FALSE; 1788 1789 /* don't enable tiling if accel is not enabled */ 1790 if (!info->r600_shadow_fb) { 1791 Bool colorTilingDefault = 1792 info->ChipFamily >= CHIP_FAMILY_R300 && 1793 /* this check could be removed sometime after a big mesa release 1794 * with proper bit, in the meantime you need to set tiling option in 1795 * xorg configuration files 1796 */ 1797 info->ChipFamily <= CHIP_FAMILY_MULLINS && 1798 !info->is_fast_fb; 1799 1800 /* 2D color tiling */ 1801 if (info->ChipFamily >= CHIP_FAMILY_R600) { 1802 info->allowColorTiling2D = xf86ReturnOptValBool(info->Options, OPTION_COLOR_TILING_2D, 1803 info->ChipFamily <= CHIP_FAMILY_MULLINS); 1804 } 1805 1806 if (info->ChipFamily >= CHIP_FAMILY_R600) { 1807 /* set default group bytes, overridden by kernel info below */ 1808 info->group_bytes = 256; 1809 info->have_tiling_info = FALSE; 1810 if (info->dri2.pKernelDRMVersion->version_minor >= 6) { 1811 if (r600_get_tile_config(pScrn)) { 1812 info->allowColorTiling = xf86ReturnOptValBool(info->Options, 1813 OPTION_COLOR_TILING, colorTilingDefault); 1814 if (!info->use_glamor) { 1815 /* need working DFS for tiling */ 1816 if (info->ChipFamily == CHIP_FAMILY_PALM && 1817 !info->accel_state->allowHWDFS) 1818 info->allowColorTiling = FALSE; 1819 } 1820 } else 1821 info->allowColorTiling = FALSE; 1822 } else 1823 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1824 "R6xx+ KMS Color Tiling requires radeon drm 2.6.0 or newer\n"); 1825 } else 1826 info->allowColorTiling = xf86ReturnOptValBool(info->Options, 1827 OPTION_COLOR_TILING, colorTilingDefault); 1828 } else 1829 info->allowColorTiling = FALSE; 1830 1831 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1832 "KMS Color Tiling: %sabled\n", info->allowColorTiling ? "en" : "dis"); 1833 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1834 "KMS Color Tiling 2D: %sabled\n", info->allowColorTiling2D ? "en" : "dis"); 1835 1836#if USE_GLAMOR 1837 if (info->use_glamor) { 1838 info->shadow_primary = xf86ReturnOptValBool(info->Options, 1839 OPTION_SHADOW_PRIMARY, FALSE); 1840 1841 if (info->shadow_primary) 1842 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "ShadowPrimary enabled\n"); 1843 } 1844#endif 1845 1846 if (!info->r600_shadow_fb) { 1847 from = X_DEFAULT; 1848 1849 info->tear_free = 2; 1850 if (xf86GetOptValBool(info->Options, OPTION_TEAR_FREE, 1851 &info->tear_free)) 1852 from = X_CONFIG; 1853 xf86DrvMsg(pScrn->scrnIndex, from, "TearFree property default: %s\n", 1854 info->tear_free == 2 ? "auto" : (info->tear_free ? "on" : "off")); 1855 } 1856 1857 if (!pScrn->is_gpu) { 1858 if (info->dri2.pKernelDRMVersion->version_minor >= 8) { 1859 Bool sw_cursor = xf86ReturnOptValBool(info->Options, 1860 OPTION_SW_CURSOR, FALSE); 1861 1862 info->allowPageFlip = xf86ReturnOptValBool(info->Options, 1863 OPTION_PAGE_FLIP, TRUE); 1864 1865 if (sw_cursor || info->shadow_primary) { 1866 xf86DrvMsg(pScrn->scrnIndex, 1867 info->allowPageFlip ? X_WARNING : X_DEFAULT, 1868 "KMS Pageflipping: disabled%s\n", 1869 info->allowPageFlip ? 1870 (sw_cursor ? " because of SWcursor" : 1871 " because of ShadowPrimary") : ""); 1872 info->allowPageFlip = FALSE; 1873 } else { 1874 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1875 "KMS Pageflipping: %sabled\n", 1876 info->allowPageFlip ? "en" : "dis"); 1877 } 1878 } 1879 1880 if (!info->use_glamor) { 1881 info->swapBuffersWait = 1882 xf86ReturnOptValBool(info->Options, OPTION_SWAPBUFFERS_WAIT, TRUE); 1883 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1884 "SwapBuffers wait for vsync: %sabled\n", 1885 info->swapBuffersWait ? "en" : "dis"); 1886 } 1887 } 1888 1889 if (xf86ReturnOptValBool(info->Options, OPTION_DELETE_DP12, FALSE)) { 1890 info->drmmode.delete_dp_12_displays = TRUE; 1891 } 1892 1893 if (drmmode_pre_init(pScrn, &info->drmmode, pScrn->bitsPerPixel / 8) == FALSE) { 1894 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Kernel modesetting setup failed\n"); 1895 return FALSE; 1896 } 1897 1898 RADEONSetupCapabilities(pScrn); 1899 1900 if (info->drmmode.count_crtcs == 1) 1901 pRADEONEnt->HasCRTC2 = FALSE; 1902 else 1903 pRADEONEnt->HasCRTC2 = TRUE; 1904 1905 1906 /* fix up cloning on rn50 cards 1907 * since they only have one crtc sometimes the xserver doesn't assign 1908 * a crtc to one of the outputs even though both outputs have common modes 1909 * which results in only one monitor being enabled. Assign a crtc here so 1910 * that both outputs light up. 1911 */ 1912 if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2) { 1913 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 1914 int i; 1915 1916 for (i = 0; i < xf86_config->num_output; i++) { 1917 xf86OutputPtr output = xf86_config->output[i]; 1918 1919 /* XXX: double check crtc mode */ 1920 if ((output->probed_modes != NULL) && (output->crtc == NULL)) 1921 output->crtc = xf86_config->crtc[0]; 1922 } 1923 } 1924 1925 /* set cursor size */ 1926 if (info->ChipFamily >= CHIP_FAMILY_BONAIRE) { 1927 info->cursor_w = CURSOR_WIDTH_CIK; 1928 info->cursor_h = CURSOR_HEIGHT_CIK; 1929 } else { 1930 info->cursor_w = CURSOR_WIDTH; 1931 info->cursor_h = CURSOR_HEIGHT; 1932 } 1933 1934 { 1935 struct drm_radeon_gem_info mminfo; 1936 1937 if (!drmCommandWriteRead(pRADEONEnt->fd, DRM_RADEON_GEM_INFO, &mminfo, sizeof(mminfo))) 1938 { 1939 info->vram_size = mminfo.vram_visible; 1940 info->gart_size = mminfo.gart_size; 1941 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1942 "mem size init: gart size :%llx vram size: s:%llx visible:%llx\n", 1943 (unsigned long long)mminfo.gart_size, 1944 (unsigned long long)mminfo.vram_size, 1945 (unsigned long long)mminfo.vram_visible); 1946 } 1947 } 1948 1949 if (!info->use_glamor) { 1950 info->exa_pixmaps = xf86ReturnOptValBool(info->Options, 1951 OPTION_EXA_PIXMAPS, 1952 (info->vram_size > (32 * 1024 * 1024) && 1953 info->RenderAccel && 1954 !info->is_fast_fb)); 1955 if (info->exa_pixmaps) 1956 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1957 "EXA: Driver will allow EXA pixmaps in VRAM\n"); 1958 else 1959 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1960 "EXA: Driver will not allow EXA pixmaps in VRAM\n"); 1961 } 1962 1963 /* no tiled scanout on r6xx+ yet */ 1964 if (info->allowColorTiling) { 1965 if (info->ChipFamily >= CHIP_FAMILY_R600) 1966 tiling |= RADEON_TILING_MICRO; 1967 else 1968 tiling |= RADEON_TILING_MACRO; 1969 } 1970 cpp = pScrn->bitsPerPixel / 8; 1971 pScrn->displayWidth = 1972 RADEON_ALIGN(pScrn->virtualX, drmmode_get_pitch_align(pScrn, cpp, tiling)); 1973 1974 /* Set display resolution */ 1975 xf86SetDpi(pScrn, 0, 0); 1976 1977 if (!xf86SetGamma(pScrn, zeros)) return FALSE; 1978 1979 if (!xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) { 1980 if (!xf86LoadSubModule(pScrn, "ramdac")) return FALSE; 1981 } 1982 1983 if (pScrn->modes == NULL 1984#ifdef XSERVER_PLATFORM_BUS 1985 && !pScrn->is_gpu 1986#endif 1987 ) { 1988 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No modes.\n"); 1989 return FALSE; 1990 } 1991 1992 return TRUE; 1993} 1994 1995static Bool RADEONCursorInit_KMS(ScreenPtr pScreen) 1996{ 1997 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); 1998 RADEONInfoPtr info = RADEONPTR(pScrn); 1999 2000 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 2001 "Initializing Cursor\n"); 2002 2003 /* Set Silken Mouse */ 2004 xf86SetSilkenMouse(pScreen); 2005 2006 /* Cursor setup */ 2007 miDCInitialize(pScreen, xf86GetPointerScreenFuncs()); 2008 2009 if (info->allowPageFlip) { 2010 miPointerScreenPtr PointPriv = 2011 dixLookupPrivate(&pScreen->devPrivates, miPointerScreenKey); 2012 2013 if (!dixRegisterScreenPrivateKey(&radeon_device_private_key, pScreen, 2014 PRIVATE_DEVICE, 2015 sizeof(struct radeon_device_priv))) { 2016 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "dixRegisterScreenPrivateKey failed\n"); 2017 return FALSE; 2018 } 2019 2020 if (PointPriv->spriteFuncs->SetCursor != drmmode_sprite_set_cursor) { 2021 info->SetCursor = PointPriv->spriteFuncs->SetCursor; 2022 info->MoveCursor = PointPriv->spriteFuncs->MoveCursor; 2023 PointPriv->spriteFuncs->SetCursor = drmmode_sprite_set_cursor; 2024 PointPriv->spriteFuncs->MoveCursor = drmmode_sprite_move_cursor; 2025 } 2026 } 2027 2028 if (xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) 2029 return TRUE; 2030 2031 if (!xf86_cursors_init(pScreen, info->cursor_w, info->cursor_h, 2032 HARDWARE_CURSOR_TRUECOLOR_AT_8BPP | 2033 HARDWARE_CURSOR_AND_SOURCE_WITH_MASK | 2034 HARDWARE_CURSOR_SOURCE_MASK_INTERLEAVE_1 | 2035 HARDWARE_CURSOR_UPDATE_UNHIDDEN | 2036 HARDWARE_CURSOR_ARGB)) { 2037 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "xf86_cursors_init failed\n"); 2038 return FALSE; 2039 } 2040 2041 return TRUE; 2042} 2043 2044void 2045RADEONBlank(ScrnInfoPtr pScrn) 2046{ 2047 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 2048 xf86OutputPtr output; 2049 xf86CrtcPtr crtc; 2050 int o, c; 2051 2052 for (c = 0; c < xf86_config->num_crtc; c++) { 2053 crtc = xf86_config->crtc[c]; 2054 for (o = 0; o < xf86_config->num_output; o++) { 2055 output = xf86_config->output[o]; 2056 if (output->crtc != crtc) 2057 continue; 2058 2059 output->funcs->dpms(output, DPMSModeOff); 2060 } 2061 crtc->funcs->dpms(crtc, DPMSModeOff); 2062 } 2063} 2064 2065void 2066RADEONUnblank(ScrnInfoPtr pScrn) 2067{ 2068 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 2069 xf86OutputPtr output; 2070 xf86CrtcPtr crtc; 2071 int o, c; 2072 for (c = 0; c < xf86_config->num_crtc; c++) { 2073 crtc = xf86_config->crtc[c]; 2074 if(!crtc->enabled) 2075 continue; 2076 crtc->funcs->dpms(crtc, DPMSModeOn); 2077 for (o = 0; o < xf86_config->num_output; o++) { 2078 output = xf86_config->output[o]; 2079 if (output->crtc != crtc) 2080 continue; 2081 output->funcs->dpms(output, DPMSModeOn); 2082 } 2083 } 2084} 2085 2086 2087static Bool RADEONSaveScreen_KMS(ScreenPtr pScreen, int mode) 2088{ 2089 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); 2090 Bool unblank; 2091 2092 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 2093 "RADEONSaveScreen(%d)\n", mode); 2094 2095 unblank = xf86IsUnblank(mode); 2096 if (unblank) SetTimeSinceLastInputEvent(); 2097 2098 if ((pScrn != NULL) && pScrn->vtSema) { 2099 if (unblank) 2100 RADEONUnblank(pScrn); 2101 else 2102 RADEONBlank(pScrn); 2103 } 2104 return TRUE; 2105} 2106 2107static Bool radeon_set_drm_master(ScrnInfoPtr pScrn) 2108{ 2109 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 2110 int err; 2111 2112#ifdef XF86_PDEV_SERVER_FD 2113 if (pRADEONEnt->platform_dev && 2114 (pRADEONEnt->platform_dev->flags & XF86_PDEV_SERVER_FD)) 2115 return TRUE; 2116#endif 2117 2118 err = drmSetMaster(pRADEONEnt->fd); 2119 if (err) 2120 ErrorF("Unable to retrieve master\n"); 2121 2122 return err == 0; 2123} 2124 2125static void radeon_drop_drm_master(ScrnInfoPtr pScrn) 2126{ 2127 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 2128 2129#ifdef XF86_PDEV_SERVER_FD 2130 if (pRADEONEnt->platform_dev && 2131 (pRADEONEnt->platform_dev->flags & XF86_PDEV_SERVER_FD)) 2132 return; 2133#endif 2134 2135 drmDropMaster(pRADEONEnt->fd); 2136} 2137 2138/* Called at the end of each server generation. Restore the original 2139 * text mode, unmap video memory, and unwrap and call the saved 2140 * CloseScreen function. 2141 */ 2142static Bool RADEONCloseScreen_KMS(ScreenPtr pScreen) 2143{ 2144 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); 2145 RADEONInfoPtr info = RADEONPTR(pScrn); 2146 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 2147 2148 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 2149 "RADEONCloseScreen\n"); 2150 2151 /* Clear mask of assigned crtc's in this generation */ 2152 pRADEONEnt->assigned_crtcs = 0; 2153 2154 drmmode_uevent_fini(pScrn, &info->drmmode); 2155 radeon_drm_queue_close(pScrn); 2156 radeon_cs_flush_indirect(pScrn); 2157 2158 if (info->callback_event_type != -1) { 2159 DeleteCallback(&EventCallback, radeon_event_callback, pScrn); 2160 DeleteCallback(&FlushCallback, radeon_flush_callback, pScrn); 2161 } 2162 2163 if (info->accel_state->exa) { 2164 exaDriverFini(pScreen); 2165 free(info->accel_state->exa); 2166 info->accel_state->exa = NULL; 2167 } 2168 2169 radeon_sync_close(pScreen); 2170 2171 if (info->accel_state->use_vbos) 2172 radeon_vbo_free_lists(pScrn); 2173 2174 radeon_drop_drm_master(pScrn); 2175 2176 drmmode_fini(pScrn, &info->drmmode); 2177 if (info->dri2.enabled) 2178 radeon_dri2_close_screen(pScreen); 2179 2180 radeon_glamor_fini(pScreen); 2181 2182 pScrn->vtSema = FALSE; 2183 xf86ClearPrimInitDone(info->pEnt->index); 2184 2185 if (info->allowPageFlip) { 2186 miPointerScreenPtr PointPriv = 2187 dixLookupPrivate(&pScreen->devPrivates, miPointerScreenKey); 2188 2189 if (PointPriv->spriteFuncs->SetCursor == drmmode_sprite_set_cursor) { 2190 PointPriv->spriteFuncs->SetCursor = info->SetCursor; 2191 PointPriv->spriteFuncs->MoveCursor = info->MoveCursor; 2192 } 2193 } 2194 2195 pScreen->BlockHandler = info->BlockHandler; 2196 pScreen->CloseScreen = info->CloseScreen; 2197 return pScreen->CloseScreen(pScreen); 2198} 2199 2200 2201void RADEONFreeScreen_KMS(ScrnInfoPtr pScrn) 2202{ 2203 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 2204 "RADEONFreeScreen\n"); 2205 2206 RADEONFreeRec(pScrn); 2207} 2208 2209Bool RADEONScreenInit_KMS(ScreenPtr pScreen, int argc, char **argv) 2210{ 2211 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); 2212 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 2213 RADEONInfoPtr info = RADEONPTR(pScrn); 2214 int subPixelOrder = SubPixelUnknown; 2215 MessageType from; 2216 Bool value; 2217 int driLevel; 2218 const char *s; 2219 void *front_ptr; 2220 2221 pScrn->fbOffset = 0; 2222 2223 miClearVisualTypes(); 2224 if (!miSetVisualTypes(pScrn->depth, 2225 miGetDefaultVisualMask(pScrn->depth), 2226 pScrn->rgbBits, 2227 pScrn->defaultVisual)) return FALSE; 2228 miSetPixmapDepths (); 2229 2230 if (!radeon_set_drm_master(pScrn)) 2231 return FALSE; 2232 2233 info->directRenderingEnabled = FALSE; 2234 if (info->r600_shadow_fb == FALSE) 2235 info->directRenderingEnabled = radeon_dri2_screen_init(pScreen); 2236 2237 info->surf_man = radeon_surface_manager_new(pRADEONEnt->fd); 2238 if (!info->bufmgr) 2239 info->bufmgr = radeon_bo_manager_gem_ctor(pRADEONEnt->fd); 2240 if (!info->bufmgr) { 2241 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2242 "failed to initialise GEM buffer manager"); 2243 return FALSE; 2244 } 2245 drmmode_set_bufmgr(pScrn, &info->drmmode, info->bufmgr); 2246 2247 if (!info->csm) 2248 info->csm = radeon_cs_manager_gem_ctor(pRADEONEnt->fd); 2249 if (!info->csm) { 2250 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2251 "failed to initialise command submission manager"); 2252 return FALSE; 2253 } 2254 2255 if (!info->cs) 2256 info->cs = radeon_cs_create(info->csm, RADEON_BUFFER_SIZE/4); 2257 if (!info->cs) { 2258 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2259 "failed to initialise command submission buffer"); 2260 return FALSE; 2261 } 2262 2263 radeon_cs_set_limit(info->cs, RADEON_GEM_DOMAIN_GTT, info->gart_size); 2264 radeon_cs_space_set_flush(info->cs, (void(*)(void *))radeon_cs_flush_indirect, pScrn); 2265 2266 if (!radeon_setup_kernel_mem(pScreen)) { 2267 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "radeon_setup_kernel_mem failed\n"); 2268 return FALSE; 2269 } 2270 front_ptr = info->front_bo->ptr; 2271 2272 if (info->r600_shadow_fb) { 2273 info->fb_shadow = calloc(1, 2274 pScrn->displayWidth * pScrn->virtualY * 2275 ((pScrn->bitsPerPixel + 7) >> 3)); 2276 if (info->fb_shadow == NULL) { 2277 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2278 "Failed to allocate shadow framebuffer\n"); 2279 return FALSE; 2280 } else { 2281 if (!fbScreenInit(pScreen, info->fb_shadow, 2282 pScrn->virtualX, pScrn->virtualY, 2283 pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth, 2284 pScrn->bitsPerPixel)) 2285 return FALSE; 2286 } 2287 } 2288 2289 if (info->r600_shadow_fb == FALSE) { 2290 /* Init fb layer */ 2291 if (!fbScreenInit(pScreen, front_ptr, 2292 pScrn->virtualX, pScrn->virtualY, 2293 pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth, 2294 pScrn->bitsPerPixel)) 2295 return FALSE; 2296 } 2297 2298 xf86SetBlackWhitePixels(pScreen); 2299 2300 if (pScrn->bitsPerPixel > 8) { 2301 VisualPtr visual; 2302 2303 visual = pScreen->visuals + pScreen->numVisuals; 2304 while (--visual >= pScreen->visuals) { 2305 if ((visual->class | DynamicClass) == DirectColor) { 2306 visual->offsetRed = pScrn->offset.red; 2307 visual->offsetGreen = pScrn->offset.green; 2308 visual->offsetBlue = pScrn->offset.blue; 2309 visual->redMask = pScrn->mask.red; 2310 visual->greenMask = pScrn->mask.green; 2311 visual->blueMask = pScrn->mask.blue; 2312 } 2313 } 2314 } 2315 2316 /* Must be after RGB order fixed */ 2317 fbPictureInit (pScreen, 0, 0); 2318 2319#ifdef RENDER 2320 if ((s = xf86GetOptValString(info->Options, OPTION_SUBPIXEL_ORDER))) { 2321 if (strcmp(s, "RGB") == 0) subPixelOrder = SubPixelHorizontalRGB; 2322 else if (strcmp(s, "BGR") == 0) subPixelOrder = SubPixelHorizontalBGR; 2323 else if (strcmp(s, "NONE") == 0) subPixelOrder = SubPixelNone; 2324 PictureSetSubpixelOrder (pScreen, subPixelOrder); 2325 } 2326#endif 2327 2328 if (!pScreen->isGPU) { 2329 if (xorgGetVersion() >= XORG_VERSION_NUMERIC(1,18,3,0,0)) 2330 value = info->use_glamor; 2331 else 2332 value = FALSE; 2333 from = X_DEFAULT; 2334 2335 if (!info->r600_shadow_fb) { 2336 if (xf86GetOptValBool(info->Options, OPTION_DRI3, &value)) 2337 from = X_CONFIG; 2338 2339 if (xf86GetOptValInteger(info->Options, OPTION_DRI, &driLevel) && 2340 (driLevel == 2 || driLevel == 3)) { 2341 from = X_CONFIG; 2342 value = driLevel == 3; 2343 } 2344 } 2345 2346 if (value) { 2347 value = radeon_sync_init(pScreen) && 2348 radeon_present_screen_init(pScreen) && 2349 radeon_dri3_screen_init(pScreen); 2350 2351 if (!value) 2352 from = X_WARNING; 2353 } 2354 2355 xf86DrvMsg(pScrn->scrnIndex, from, "DRI3 %sabled\n", value ? "en" : "dis"); 2356 } 2357 2358 pScrn->vtSema = TRUE; 2359 xf86SetBackingStore(pScreen); 2360 2361 if (info->directRenderingEnabled) { 2362 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct rendering enabled\n"); 2363 } else { 2364 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 2365 "Direct rendering disabled\n"); 2366 } 2367 2368 if (info->r600_shadow_fb) { 2369 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Acceleration disabled\n"); 2370 info->accelOn = FALSE; 2371 } else { 2372 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 2373 "Initializing Acceleration\n"); 2374 if (RADEONAccelInit(pScreen)) { 2375 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Acceleration enabled\n"); 2376 info->accelOn = TRUE; 2377 } else { 2378 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2379 "Acceleration initialization failed\n"); 2380 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Acceleration disabled\n"); 2381 info->accelOn = FALSE; 2382 } 2383 } 2384 2385 /* Init DPMS */ 2386 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 2387 "Initializing DPMS\n"); 2388 xf86DPMSInit(pScreen, xf86DPMSSet, 0); 2389 2390 if (!RADEONCursorInit_KMS(pScreen)) 2391 return FALSE; 2392 2393 /* DGA setup */ 2394#ifdef XFreeXDGA 2395 /* DGA is dangerous on kms as the base and framebuffer location may change: 2396 * http://lists.freedesktop.org/archives/xorg-devel/2009-September/002113.html 2397 */ 2398 /* xf86DiDGAInit(pScreen, info->LinearAddr + pScrn->fbOffset); */ 2399#endif 2400 if (info->r600_shadow_fb == FALSE && !pScreen->isGPU) { 2401 /* Init Xv */ 2402 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 2403 "Initializing Xv\n"); 2404 RADEONInitVideo(pScreen); 2405 } 2406 2407 if (info->r600_shadow_fb == TRUE) { 2408 if (!shadowSetup(pScreen)) { 2409 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2410 "Shadowfb initialization failed\n"); 2411 return FALSE; 2412 } 2413 } 2414 pScrn->pScreen = pScreen; 2415 2416 if (!pScreen->isGPU) { 2417 if (serverGeneration == 1 && bgNoneRoot && info->accelOn) { 2418 info->CreateWindow = pScreen->CreateWindow; 2419 pScreen->CreateWindow = RADEONCreateWindow_oneshot; 2420 } 2421 info->WindowExposures = pScreen->WindowExposures; 2422 pScreen->WindowExposures = RADEONWindowExposures_oneshot; 2423 } 2424 2425 /* Provide SaveScreen & wrap BlockHandler and CloseScreen */ 2426 /* Wrap CloseScreen */ 2427 info->CloseScreen = pScreen->CloseScreen; 2428 pScreen->CloseScreen = RADEONCloseScreen_KMS; 2429 pScreen->SaveScreen = RADEONSaveScreen_KMS; 2430 info->BlockHandler = pScreen->BlockHandler; 2431 pScreen->BlockHandler = RADEONBlockHandler_KMS; 2432 2433 info->CreateScreenResources = pScreen->CreateScreenResources; 2434 pScreen->CreateScreenResources = RADEONCreateScreenResources_KMS; 2435 2436 pScreen->StartPixmapTracking = PixmapStartDirtyTracking; 2437 pScreen->StopPixmapTracking = PixmapStopDirtyTracking; 2438#if HAS_SYNC_SHARED_PIXMAP 2439 pScreen->SyncSharedPixmap = radeon_sync_shared_pixmap; 2440#endif 2441 2442 if (!xf86CrtcScreenInit (pScreen)) 2443 return FALSE; 2444 2445 /* Wrap pointer motion to flip touch screen around */ 2446// info->PointerMoved = pScrn->PointerMoved; 2447// pScrn->PointerMoved = RADEONPointerMoved; 2448 2449 if (!drmmode_setup_colormap(pScreen, pScrn)) 2450 return FALSE; 2451 2452 /* Note unused options */ 2453 if (serverGeneration == 1) 2454 xf86ShowUnusedOptions(pScrn->scrnIndex, pScrn->options); 2455 2456 drmmode_init(pScrn, &info->drmmode); 2457 2458 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 2459 "RADEONScreenInit finished\n"); 2460 2461 info->accel_state->XInited3D = FALSE; 2462 info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN; 2463 2464 return TRUE; 2465} 2466 2467Bool RADEONEnterVT_KMS(ScrnInfoPtr pScrn) 2468{ 2469 RADEONInfoPtr info = RADEONPTR(pScrn); 2470 2471 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 2472 "RADEONEnterVT_KMS\n"); 2473 2474 radeon_set_drm_master(pScrn); 2475 2476 if (info->r600_shadow_fb) { 2477 int base_align = drmmode_get_base_align(pScrn, info->pixel_bytes, 0); 2478 struct radeon_bo *front_bo = radeon_bo_open(info->bufmgr, 0, 2479 info->front_bo->size, 2480 base_align, 2481 RADEON_GEM_DOMAIN_VRAM, 0); 2482 2483 if (front_bo) { 2484 if (radeon_bo_map(front_bo, 1) == 0) { 2485 memset(front_bo->ptr, 0, front_bo->size); 2486 radeon_bo_unref(info->front_bo); 2487 info->front_bo = front_bo; 2488 } else { 2489 radeon_bo_unref(front_bo); 2490 front_bo = NULL; 2491 } 2492 } 2493 2494 if (!front_bo) { 2495 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 2496 "Failed to allocate new scanout BO after VT switch, " 2497 "other DRM masters may see screen contents\n"); 2498 } 2499 } 2500 2501 info->accel_state->XInited3D = FALSE; 2502 info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN; 2503 2504 pScrn->vtSema = TRUE; 2505 2506 if (!drmmode_set_desired_modes(pScrn, &info->drmmode, TRUE)) 2507 return FALSE; 2508 2509 return TRUE; 2510} 2511 2512static 2513CARD32 cleanup_black_fb(OsTimerPtr timer, CARD32 now, pointer data) 2514{ 2515 ScreenPtr screen = data; 2516 ScrnInfoPtr scrn = xf86ScreenToScrn(screen); 2517 RADEONEntPtr pRADEONEnt = RADEONEntPriv(scrn); 2518 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(scrn); 2519 int c; 2520 2521 if (xf86ScreenToScrn(radeon_master_screen(screen))->vtSema) 2522 return 0; 2523 2524 /* Unreference the all-black FB created by RADEONLeaveVT_KMS. After 2525 * this, there should be no FB left created by this driver. 2526 */ 2527 for (c = 0; c < xf86_config->num_crtc; c++) { 2528 drmmode_crtc_private_ptr drmmode_crtc = 2529 xf86_config->crtc[c]->driver_private; 2530 2531 drmmode_fb_reference(pRADEONEnt->fd, &drmmode_crtc->fb, NULL); 2532 } 2533 2534 TimerFree(timer); 2535 return 0; 2536} 2537 2538static void 2539pixmap_unref_fb(void *value, XID id, void *cdata) 2540{ 2541 PixmapPtr pixmap = value; 2542 RADEONEntPtr pRADEONEnt = cdata; 2543 struct drmmode_fb **fb_ptr = radeon_pixmap_get_fb_ptr(pixmap); 2544 2545 if (fb_ptr) 2546 drmmode_fb_reference(pRADEONEnt->fd, fb_ptr, NULL); 2547} 2548 2549void RADEONLeaveVT_KMS(ScrnInfoPtr pScrn) 2550{ 2551 RADEONInfoPtr info = RADEONPTR(pScrn); 2552 ScreenPtr pScreen = pScrn->pScreen; 2553 2554 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 2555 "RADEONLeaveVT_KMS\n"); 2556 2557 if (!info->r600_shadow_fb) { 2558 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 2559 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 2560 struct drmmode_scanout black_scanout = { .pixmap = NULL, .bo = NULL }; 2561 xf86CrtcPtr crtc; 2562 drmmode_crtc_private_ptr drmmode_crtc; 2563 unsigned w = 0, h = 0; 2564 int i; 2565 2566 /* Compute maximum scanout dimensions of active CRTCs */ 2567 for (i = 0; i < xf86_config->num_crtc; i++) { 2568 crtc = xf86_config->crtc[i]; 2569 drmmode_crtc = crtc->driver_private; 2570 2571 if (!drmmode_crtc->fb) 2572 continue; 2573 2574 w = max(w, crtc->mode.HDisplay); 2575 h = max(h, crtc->mode.VDisplay); 2576 } 2577 2578 /* Make all active CRTCs scan out from an all-black framebuffer */ 2579 if (w > 0 && h > 0) { 2580 if (drmmode_crtc_scanout_create(crtc, &black_scanout, w, h)) { 2581 struct drmmode_fb *black_fb = 2582 radeon_pixmap_get_fb(black_scanout.pixmap); 2583 2584 radeon_pixmap_clear(black_scanout.pixmap); 2585 radeon_cs_flush_indirect(pScrn); 2586 radeon_bo_wait(black_scanout.bo); 2587 2588 for (i = 0; i < xf86_config->num_crtc; i++) { 2589 crtc = xf86_config->crtc[i]; 2590 drmmode_crtc = crtc->driver_private; 2591 2592 if (drmmode_crtc->fb) { 2593 if (black_fb) { 2594 drmmode_set_mode(crtc, black_fb, &crtc->mode, 0, 0); 2595 } else { 2596 drmModeSetCrtc(pRADEONEnt->fd, 2597 drmmode_crtc->mode_crtc->crtc_id, 0, 2598 0, 0, NULL, 0, NULL); 2599 drmmode_fb_reference(pRADEONEnt->fd, 2600 &drmmode_crtc->fb, NULL); 2601 } 2602 2603 if (pScrn->is_gpu) { 2604 if (drmmode_crtc->scanout[0].pixmap) 2605 pixmap_unref_fb(drmmode_crtc->scanout[0].pixmap, 2606 None, pRADEONEnt); 2607 if (drmmode_crtc->scanout[1].pixmap) 2608 pixmap_unref_fb(drmmode_crtc->scanout[1].pixmap, 2609 None, pRADEONEnt); 2610 } else { 2611 drmmode_crtc_scanout_free(drmmode_crtc); 2612 } 2613 } 2614 } 2615 } 2616 } 2617 2618 xf86RotateFreeShadow(pScrn); 2619 drmmode_crtc_scanout_destroy(&info->drmmode, &black_scanout); 2620 2621 /* Unreference FBs of all pixmaps. After this, the only FB remaining 2622 * should be the all-black one being scanned out by active CRTCs 2623 */ 2624 for (i = 0; i < currentMaxClients; i++) { 2625 if (i > 0 && 2626 (!clients[i] || clients[i]->clientState != ClientStateRunning)) 2627 continue; 2628 2629 FindClientResourcesByType(clients[i], RT_PIXMAP, pixmap_unref_fb, 2630 pRADEONEnt); 2631 } 2632 2633 pixmap_unref_fb(pScreen->GetScreenPixmap(pScreen), None, pRADEONEnt); 2634 } else { 2635 memset(info->front_bo->ptr, 0, info->front_bo->size); 2636 } 2637 2638 TimerSet(NULL, 0, 1000, cleanup_black_fb, pScreen); 2639 2640 xf86_hide_cursors (pScrn); 2641 2642 radeon_drop_drm_master(pScrn); 2643 2644 info->accel_state->XInited3D = FALSE; 2645 info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN; 2646 2647 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 2648 "Ok, leaving now...\n"); 2649} 2650 2651 2652Bool RADEONSwitchMode_KMS(ScrnInfoPtr pScrn, DisplayModePtr mode) 2653{ 2654 Bool ret; 2655 ret = xf86SetSingleMode (pScrn, mode, RR_Rotate_0); 2656 return ret; 2657 2658} 2659 2660void RADEONAdjustFrame_KMS(ScrnInfoPtr pScrn, int x, int y) 2661{ 2662 RADEONInfoPtr info = RADEONPTR(pScrn); 2663 drmmode_adjust_frame(pScrn, &info->drmmode, x, y); 2664 return; 2665} 2666 2667static Bool radeon_setup_kernel_mem(ScreenPtr pScreen) 2668{ 2669 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); 2670 RADEONInfoPtr info = RADEONPTR(pScrn); 2671 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 2672 int cpp = info->pixel_bytes; 2673 uint32_t screen_size; 2674 int pitch, base_align; 2675 uint32_t tiling_flags = 0; 2676 struct radeon_surface surface; 2677 2678 if (info->accel_state->exa != NULL) { 2679 xf86DrvMsg(pScreen->myNum, X_ERROR, "Memory map already initialized\n"); 2680 return FALSE; 2681 } 2682 if (!info->use_glamor && info->r600_shadow_fb == FALSE) { 2683 info->accel_state->exa = exaDriverAlloc(); 2684 if (info->accel_state->exa == NULL) { 2685 xf86DrvMsg(pScreen->myNum, X_ERROR, "exaDriverAlloc failed\n"); 2686 return FALSE; 2687 } 2688 } 2689 2690 if (info->allowColorTiling && !info->shadow_primary) { 2691 if (info->ChipFamily >= CHIP_FAMILY_R600) { 2692 if (info->allowColorTiling2D) { 2693 tiling_flags |= RADEON_TILING_MACRO; 2694 } else { 2695 tiling_flags |= RADEON_TILING_MICRO; 2696 } 2697 } else 2698 tiling_flags |= RADEON_TILING_MACRO; 2699 } 2700 pitch = RADEON_ALIGN(pScrn->virtualX, drmmode_get_pitch_align(pScrn, cpp, tiling_flags)) * cpp; 2701 screen_size = RADEON_ALIGN(pScrn->virtualY, drmmode_get_height_align(pScrn, tiling_flags)) * pitch; 2702 base_align = drmmode_get_base_align(pScrn, cpp, tiling_flags); 2703 if (info->ChipFamily >= CHIP_FAMILY_R600) { 2704 if(!info->surf_man) { 2705 xf86DrvMsg(pScreen->myNum, X_ERROR, 2706 "failed to initialise surface manager\n"); 2707 return FALSE; 2708 } 2709 memset(&surface, 0, sizeof(struct radeon_surface)); 2710 surface.npix_x = pScrn->virtualX; 2711 surface.npix_y = pScrn->virtualY; 2712 surface.npix_z = 1; 2713 surface.blk_w = 1; 2714 surface.blk_h = 1; 2715 surface.blk_d = 1; 2716 surface.array_size = 1; 2717 surface.last_level = 0; 2718 surface.bpe = cpp; 2719 surface.nsamples = 1; 2720 surface.flags = RADEON_SURF_SCANOUT; 2721 /* we are requiring a recent enough libdrm version */ 2722 surface.flags |= RADEON_SURF_HAS_TILE_MODE_INDEX; 2723 surface.flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE); 2724 surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE); 2725 if (tiling_flags & RADEON_TILING_MICRO) { 2726 surface.flags = RADEON_SURF_CLR(surface.flags, MODE); 2727 surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE); 2728 } 2729 if (tiling_flags & RADEON_TILING_MACRO) { 2730 surface.flags = RADEON_SURF_CLR(surface.flags, MODE); 2731 surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE); 2732 } 2733 if (radeon_surface_best(info->surf_man, &surface)) { 2734 xf86DrvMsg(pScreen->myNum, X_ERROR, 2735 "radeon_surface_best failed\n"); 2736 return FALSE; 2737 } 2738 if (radeon_surface_init(info->surf_man, &surface)) { 2739 xf86DrvMsg(pScreen->myNum, X_ERROR, 2740 "radeon_surface_init failed\n"); 2741 return FALSE; 2742 } 2743 pitch = surface.level[0].pitch_bytes; 2744 screen_size = surface.bo_size; 2745 base_align = surface.bo_alignment; 2746 tiling_flags = 0; 2747 switch (surface.level[0].mode) { 2748 case RADEON_SURF_MODE_2D: 2749 tiling_flags |= RADEON_TILING_MACRO; 2750 tiling_flags |= surface.bankw << RADEON_TILING_EG_BANKW_SHIFT; 2751 tiling_flags |= surface.bankh << RADEON_TILING_EG_BANKH_SHIFT; 2752 tiling_flags |= surface.mtilea << RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT; 2753 if (surface.tile_split) 2754 tiling_flags |= eg_tile_split(surface.tile_split) 2755 << RADEON_TILING_EG_TILE_SPLIT_SHIFT; 2756 break; 2757 case RADEON_SURF_MODE_1D: 2758 tiling_flags |= RADEON_TILING_MICRO; 2759 break; 2760 default: 2761 break; 2762 } 2763 info->front_surface = surface; 2764 } 2765 { 2766 int cursor_size; 2767 int c; 2768 2769 cursor_size = info->cursor_w * info->cursor_h * 4; 2770 cursor_size = RADEON_ALIGN(cursor_size, RADEON_GPU_PAGE_SIZE); 2771 for (c = 0; c < xf86_config->num_crtc; c++) { 2772 /* cursor objects */ 2773 if (info->cursor_bo[c] == NULL) { 2774 info->cursor_bo[c] = radeon_bo_open(info->bufmgr, 0, 2775 cursor_size, 0, 2776 RADEON_GEM_DOMAIN_VRAM, 0); 2777 if (!info->cursor_bo[c]) { 2778 ErrorF("Failed to allocate cursor buffer memory\n"); 2779 return FALSE; 2780 } 2781 2782 if (radeon_bo_map(info->cursor_bo[c], 1)) { 2783 ErrorF("Failed to map cursor buffer memory\n"); 2784 } 2785 2786 drmmode_set_cursor(pScrn, &info->drmmode, c, info->cursor_bo[c]); 2787 } 2788 } 2789 } 2790 2791 screen_size = RADEON_ALIGN(screen_size, RADEON_GPU_PAGE_SIZE); 2792 2793 if (info->front_bo == NULL) { 2794 info->front_bo = radeon_bo_open(info->bufmgr, 0, screen_size, 2795 base_align, 2796 info->shadow_primary ? 2797 RADEON_GEM_DOMAIN_GTT : 2798 RADEON_GEM_DOMAIN_VRAM, 2799 tiling_flags ? RADEON_GEM_NO_CPU_ACCESS : 0); 2800 if (info->r600_shadow_fb == TRUE) { 2801 if (radeon_bo_map(info->front_bo, 1)) { 2802 ErrorF("Failed to map cursor buffer memory\n"); 2803 } 2804 } 2805#if X_BYTE_ORDER == X_BIG_ENDIAN 2806 switch (cpp) { 2807 case 4: 2808 tiling_flags |= RADEON_TILING_SWAP_32BIT; 2809 break; 2810 case 2: 2811 tiling_flags |= RADEON_TILING_SWAP_16BIT; 2812 break; 2813 } 2814 if (info->ChipFamily < CHIP_FAMILY_R600 && 2815 info->r600_shadow_fb && tiling_flags) 2816 tiling_flags |= RADEON_TILING_SURFACE; 2817#endif 2818 if (tiling_flags) 2819 radeon_bo_set_tiling(info->front_bo, tiling_flags, pitch); 2820 } 2821 2822 pScrn->displayWidth = pitch / cpp; 2823 2824 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Front buffer size: %dK\n", info->front_bo->size/1024); 2825 radeon_kms_update_vram_limit(pScrn, screen_size); 2826 return TRUE; 2827} 2828 2829void radeon_kms_update_vram_limit(ScrnInfoPtr pScrn, uint32_t new_fb_size) 2830{ 2831 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 2832 RADEONInfoPtr info = RADEONPTR(pScrn); 2833 uint64_t remain_size_bytes; 2834 int c; 2835 2836 for (c = 0; c < xf86_config->num_crtc; c++) { 2837 if (info->cursor_bo[c] != NULL) { 2838 new_fb_size += (64 * 4 * 64); 2839 } 2840 } 2841 2842 remain_size_bytes = info->vram_size - new_fb_size; 2843 remain_size_bytes = (remain_size_bytes / 10) * 9; 2844 if (remain_size_bytes > 0xffffffff) 2845 remain_size_bytes = 0xffffffff; 2846 radeon_cs_set_limit(info->cs, RADEON_GEM_DOMAIN_VRAM, 2847 (uint32_t)remain_size_bytes); 2848 2849 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "VRAM usage limit set to %uK\n", 2850 (uint32_t)remain_size_bytes / 1024); 2851} 2852 2853/* Used to disallow modes that are not supported by the hardware */ 2854ModeStatus RADEONValidMode(ScrnInfoPtr pScrn, DisplayModePtr mode, 2855 Bool verbose, int flag) 2856{ 2857 RADEONInfoPtr info = RADEONPTR(pScrn); 2858 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 2859 2860 /* 2861 * RN50 has effective maximum mode bandwidth of about 300MiB/s. 2862 * XXX should really do this for all chips by properly computing 2863 * memory bandwidth and an overhead factor. 2864 */ 2865 if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2) { 2866 if (xf86ModeBandwidth(mode, pScrn->bitsPerPixel) > 300) 2867 return MODE_BANDWIDTH; 2868 } 2869 /* There are problems with double scan mode at high clocks 2870 * They're likely related PLL and display buffer settings. 2871 * Disable these modes for now. 2872 */ 2873 if (mode->Flags & V_DBLSCAN) { 2874 if ((mode->CrtcHDisplay >= 1024) || (mode->CrtcVDisplay >= 768)) 2875 return MODE_CLOCK_RANGE; 2876 } 2877 return MODE_OK; 2878} 2879