radeon_kms.c revision 935f1ae0 
1/*
2 * Copyright © 2009 Red Hat, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 *    Dave Airlie <airlied@redhat.com>
25 *
26 */
27#ifdef HAVE_CONFIG_H
28#include "config.h"
29#endif
30
31#include <errno.h>
32#include <sys/ioctl.h>
33/* Driver data structures */
34#include "radeon.h"
35#include "radeon_drm_queue.h"
36#include "radeon_glamor.h"
37#include "radeon_reg.h"
38#include "radeon_probe.h"
39#include "micmap.h"
40
41#include "radeon_version.h"
42#include "shadow.h"
43
44#include "atipciids.h"
45
46/* DPMS */
47#ifdef HAVE_XEXTPROTO_71
48#include <X11/extensions/dpmsconst.h>
49#else
50#define DPMS_SERVER
51#include <X11/extensions/dpms.h>
52#endif
53
54#include "radeon_chipinfo_gen.h"
55
56#include "radeon_bo_gem.h"
57#include "radeon_cs_gem.h"
58#include "radeon_vbo.h"
59
60extern SymTabRec RADEONChipsets[];
61static Bool radeon_setup_kernel_mem(ScreenPtr pScreen);
62
63const OptionInfoRec RADEONOptions_KMS[] = {
64    { OPTION_ACCEL,          "Accel",            OPTV_BOOLEAN, {0}, FALSE },
65    { OPTION_SW_CURSOR,      "SWcursor",         OPTV_BOOLEAN, {0}, FALSE },
66    { OPTION_PAGE_FLIP,      "EnablePageFlip",   OPTV_BOOLEAN, {0}, FALSE },
67    { OPTION_COLOR_TILING,   "ColorTiling",      OPTV_BOOLEAN, {0}, FALSE },
68    { OPTION_COLOR_TILING_2D,"ColorTiling2D",    OPTV_BOOLEAN, {0}, FALSE },
69    { OPTION_RENDER_ACCEL,   "RenderAccel",      OPTV_BOOLEAN, {0}, FALSE },
70    { OPTION_SUBPIXEL_ORDER, "SubPixelOrder",    OPTV_ANYSTR,  {0}, FALSE },
71#ifdef USE_GLAMOR
72    { OPTION_ACCELMETHOD,    "AccelMethod",      OPTV_STRING,  {0}, FALSE },
73    { OPTION_SHADOW_PRIMARY, "ShadowPrimary",    OPTV_BOOLEAN, {0}, FALSE },
74#endif
75    { OPTION_EXA_VSYNC,      "EXAVSync",         OPTV_BOOLEAN, {0}, FALSE },
76    { OPTION_EXA_PIXMAPS,    "EXAPixmaps",	 OPTV_BOOLEAN,   {0}, FALSE },
77    { OPTION_ZAPHOD_HEADS,   "ZaphodHeads",      OPTV_STRING,  {0}, FALSE },
78    { OPTION_SWAPBUFFERS_WAIT,"SwapbuffersWait", OPTV_BOOLEAN, {0}, FALSE },
79    { OPTION_DELETE_DP12,    "DeleteUnusedDP12Displays", OPTV_BOOLEAN, {0}, FALSE},
80    { OPTION_DRI3,           "DRI3",             OPTV_BOOLEAN, {0}, FALSE },
81    { OPTION_DRI,            "DRI",              OPTV_INTEGER, {0}, FALSE },
82    { OPTION_TEAR_FREE,      "TearFree",         OPTV_BOOLEAN, {0}, FALSE },
83    { -1,                    NULL,               OPTV_NONE,    {0}, FALSE }
84};
85
86const OptionInfoRec *RADEONOptionsWeak(void) { return RADEONOptions_KMS; }
87
88void radeon_cs_flush_indirect(ScrnInfoPtr pScrn)
89{
90    RADEONInfoPtr  info = RADEONPTR(pScrn);
91    struct radeon_accel_state *accel_state;
92    int ret;
93
94#ifdef USE_GLAMOR
95    if (info->use_glamor) {
96	glamor_block_handler(pScrn->pScreen);
97	info->gpu_flushed++;
98	return;
99    }
100#endif
101
102    if (!info->cs->cdw)
103	return;
104
105    accel_state = info->accel_state;
106
107    /* release the current VBO so we don't block on mapping it later */
108    if (info->accel_state->vbo.vb_offset && info->accel_state->vbo.vb_bo) {
109        radeon_vbo_put(pScrn, &info->accel_state->vbo);
110        info->accel_state->vbo.vb_start_op = -1;
111    }
112
113    /* release the current VBO so we don't block on mapping it later */
114    if (info->accel_state->cbuf.vb_bo) {
115        radeon_vbo_put(pScrn, &info->accel_state->cbuf);
116        info->accel_state->cbuf.vb_start_op = -1;
117    }
118
119    radeon_cs_emit(info->cs);
120    radeon_cs_erase(info->cs);
121
122    if (accel_state->use_vbos)
123        radeon_vbo_flush_bos(pScrn);
124
125    ret = radeon_cs_space_check_with_bo(info->cs,
126					accel_state->vbo.vb_bo,
127					RADEON_GEM_DOMAIN_GTT, 0);
128    if (ret)
129      ErrorF("space check failed in flush\n");
130
131    if (info->reemit_current2d && info->state_2d.op)
132        info->reemit_current2d(pScrn, info->state_2d.op);
133
134    if (info->dri2.enabled) {
135        info->accel_state->XInited3D = FALSE;
136        info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN;
137    }
138
139}
140
141void radeon_ddx_cs_start(ScrnInfoPtr pScrn,
142			 int n, const char *file,
143			 const char *func, int line)
144{
145    RADEONInfoPtr  info = RADEONPTR(pScrn);
146
147    if (info->cs->cdw + n > info->cs->ndw) {
148	radeon_cs_flush_indirect(pScrn);
149
150    }
151    radeon_cs_begin(info->cs, n, file, func, line);
152}
153
154
155extern _X_EXPORT int gRADEONEntityIndex;
156
157static int getRADEONEntityIndex(void)
158{
159    return gRADEONEntityIndex;
160}
161
162
163RADEONEntPtr RADEONEntPriv(ScrnInfoPtr pScrn)
164{
165    DevUnion     *pPriv;
166    RADEONInfoPtr  info   = RADEONPTR(pScrn);
167    pPriv = xf86GetEntityPrivate(info->pEnt->index,
168                                 getRADEONEntityIndex());
169    return pPriv->ptr;
170}
171
172/* Allocate our private RADEONInfoRec */
173static Bool RADEONGetRec(ScrnInfoPtr pScrn)
174{
175    if (pScrn->driverPrivate) return TRUE;
176
177    pScrn->driverPrivate = xnfcalloc(sizeof(RADEONInfoRec), 1);
178    return TRUE;
179}
180
181/* Free our private RADEONInfoRec */
182static void RADEONFreeRec(ScrnInfoPtr pScrn)
183{
184    RADEONInfoPtr  info;
185
186    if (!pScrn || !pScrn->driverPrivate) return;
187
188    info = RADEONPTR(pScrn);
189
190    if (info->fbcon_pixmap)
191	pScrn->pScreen->DestroyPixmap(info->fbcon_pixmap);
192
193    if (info->dri2.drm_fd > 0) {
194        DevUnion *pPriv;
195        RADEONEntPtr pRADEONEnt;
196        pPriv = xf86GetEntityPrivate(pScrn->entityList[0],
197				     getRADEONEntityIndex());
198
199        pRADEONEnt = pPriv->ptr;
200        pRADEONEnt->fd_ref--;
201        if (!pRADEONEnt->fd_ref) {
202#ifdef XF86_PDEV_SERVER_FD
203            if (!(pRADEONEnt->platform_dev &&
204                    pRADEONEnt->platform_dev->flags & XF86_PDEV_SERVER_FD))
205#endif
206                drmClose(pRADEONEnt->fd);
207            pRADEONEnt->fd = 0;
208        }
209    }
210
211    if (info->accel_state) {
212	free(info->accel_state);
213	info->accel_state = NULL;
214    }
215
216    free(pScrn->driverPrivate);
217    pScrn->driverPrivate = NULL;
218}
219
220static void *
221radeonShadowWindow(ScreenPtr screen, CARD32 row, CARD32 offset, int mode,
222		   CARD32 *size, void *closure)
223{
224    ScrnInfoPtr pScrn = xf86ScreenToScrn(screen);
225    RADEONInfoPtr  info   = RADEONPTR(pScrn);
226    int stride;
227
228    stride = (pScrn->displayWidth * pScrn->bitsPerPixel) / 8;
229    *size = stride;
230
231    return ((uint8_t *)info->front_bo->ptr + row * stride + offset);
232}
233
234static void
235radeonUpdatePacked(ScreenPtr pScreen, shadowBufPtr pBuf)
236{
237    shadowUpdatePacked(pScreen, pBuf);
238}
239
240static Bool RADEONCreateScreenResources_KMS(ScreenPtr pScreen)
241{
242    ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen);
243    RADEONInfoPtr  info   = RADEONPTR(pScrn);
244    rrScrPrivPtr rrScrPriv = rrGetScrPriv(pScreen);
245    PixmapPtr pixmap;
246    struct radeon_surface *surface;
247
248    pScreen->CreateScreenResources = info->CreateScreenResources;
249    if (!(*pScreen->CreateScreenResources)(pScreen))
250	return FALSE;
251    pScreen->CreateScreenResources = RADEONCreateScreenResources_KMS;
252
253    /* Set the RandR primary output if Xorg hasn't */
254    if (
255#ifdef RADEON_PIXMAP_SHARING
256	!pScreen->isGPU &&
257#endif
258	!rrScrPriv->primaryOutput)
259    {
260	xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
261
262	rrScrPriv->primaryOutput = xf86_config->output[0]->randr_output;
263	RROutputChanged(rrScrPriv->primaryOutput, FALSE);
264	rrScrPriv->layoutChanged = TRUE;
265    }
266
267    if (!drmmode_set_desired_modes(pScrn, &info->drmmode, FALSE))
268	return FALSE;
269
270    drmmode_uevent_init(pScrn, &info->drmmode);
271
272    if (info->r600_shadow_fb) {
273	pixmap = pScreen->GetScreenPixmap(pScreen);
274
275	if (!shadowAdd(pScreen, pixmap, radeonUpdatePacked,
276		       radeonShadowWindow, 0, NULL))
277	    return FALSE;
278    }
279
280    if (info->dri2.enabled || info->use_glamor) {
281	if (info->front_bo) {
282	    PixmapPtr pPix = pScreen->GetScreenPixmap(pScreen);
283	    radeon_set_pixmap_bo(pPix, info->front_bo);
284	    surface = radeon_get_pixmap_surface(pPix);
285	    if (surface) {
286		*surface = info->front_surface;
287	    }
288	}
289    }
290
291    if (info->use_glamor)
292	radeon_glamor_create_screen_resources(pScreen);
293
294    return TRUE;
295}
296
297#ifdef RADEON_PIXMAP_SHARING
298static void
299redisplay_dirty(ScreenPtr screen, PixmapDirtyUpdatePtr dirty)
300{
301	ScrnInfoPtr pScrn = xf86ScreenToScrn(screen);
302	RegionRec pixregion;
303
304	PixmapRegionInit(&pixregion, dirty->slave_dst);
305	DamageRegionAppend(&dirty->slave_dst->drawable, &pixregion);
306#ifdef HAS_DIRTYTRACKING_ROTATION
307	PixmapSyncDirtyHelper(dirty);
308#else
309	PixmapSyncDirtyHelper(dirty, &pixregion);
310#endif
311
312	radeon_cs_flush_indirect(pScrn);
313	DamageRegionProcessPending(&dirty->slave_dst->drawable);
314	RegionUninit(&pixregion);
315}
316
317static void
318radeon_dirty_update(ScreenPtr screen)
319{
320	RegionPtr region;
321	PixmapDirtyUpdatePtr ent;
322
323	if (xorg_list_is_empty(&screen->pixmap_dirty_list))
324		return;
325
326	xorg_list_for_each_entry(ent, &screen->pixmap_dirty_list, ent) {
327		region = DamageRegion(ent->damage);
328		if (RegionNotEmpty(region)) {
329			redisplay_dirty(screen, ent);
330			DamageEmpty(ent->damage);
331		}
332	}
333}
334#endif
335
336static Bool
337radeon_scanout_extents_intersect(xf86CrtcPtr xf86_crtc, BoxPtr extents, int w,
338				 int h)
339{
340    extents->x1 = max(extents->x1 - xf86_crtc->x, 0);
341    extents->y1 = max(extents->y1 - xf86_crtc->y, 0);
342
343    switch (xf86_crtc->rotation & 0xf) {
344    case RR_Rotate_90:
345    case RR_Rotate_270:
346	extents->x2 = min(extents->x2 - xf86_crtc->x, h);
347	extents->y2 = min(extents->y2 - xf86_crtc->y, w);
348	break;
349    default:
350	extents->x2 = min(extents->x2 - xf86_crtc->x, w);
351	extents->y2 = min(extents->y2 - xf86_crtc->y, h);
352    }
353
354    return (extents->x1 < extents->x2 && extents->y1 < extents->y2);
355}
356
357static Bool
358radeon_scanout_do_update(xf86CrtcPtr xf86_crtc, int scanout_id)
359{
360    drmmode_crtc_private_ptr drmmode_crtc = xf86_crtc->driver_private;
361    ScrnInfoPtr scrn;
362    DamagePtr pDamage;
363    RegionPtr pRegion;
364    DrawablePtr pDraw;
365    ScreenPtr pScreen;
366    BoxRec extents;
367    RADEONInfoPtr info;
368    Bool force;
369
370    if (!xf86_crtc->enabled ||
371	drmmode_crtc->dpms_mode != DPMSModeOn ||
372	!drmmode_crtc->scanout[scanout_id].pixmap)
373	return FALSE;
374
375    pDamage = drmmode_crtc->scanout[scanout_id].damage;
376    if (!pDamage)
377	return FALSE;
378
379    pRegion = DamageRegion(pDamage);
380    if (!RegionNotEmpty(pRegion))
381	return FALSE;
382
383    pDraw = &drmmode_crtc->scanout[scanout_id].pixmap->drawable;
384    pScreen = pDraw->pScreen;
385    extents = *RegionExtents(pRegion);
386    RegionEmpty(pRegion);
387    if (!radeon_scanout_extents_intersect(xf86_crtc, &extents, pDraw->width,
388					  pDraw->height))
389	return FALSE;
390
391    scrn = xf86_crtc->scrn;
392    info = RADEONPTR(scrn);
393    force = info->accel_state->force;
394    info->accel_state->force = TRUE;
395
396#if XF86_CRTC_VERSION >= 4
397    if (xf86_crtc->driverIsPerformingTransform) {
398	SourceValidateProcPtr SourceValidate = pScreen->SourceValidate;
399	PictFormatPtr format = PictureWindowFormat(pScreen->root);
400	int error;
401	PicturePtr src, dst;
402	XID include_inferiors = IncludeInferiors;
403
404	src = CreatePicture(None,
405			    &pScreen->root->drawable,
406			    format,
407			    CPSubwindowMode,
408			    &include_inferiors, serverClient, &error);
409	if (!src) {
410	    ErrorF("Failed to create source picture for transformed scanout "
411		   "update\n");
412	    goto out;
413	}
414
415	dst = CreatePicture(None, pDraw, format, 0L, NULL, serverClient, &error);
416	if (!dst) {
417	    ErrorF("Failed to create destination picture for transformed scanout "
418		   "update\n");
419	    goto free_src;
420	}
421
422	error = SetPictureTransform(src, &xf86_crtc->crtc_to_framebuffer);
423	if (error) {
424	    ErrorF("SetPictureTransform failed for transformed scanout "
425		   "update\n");
426	    goto free_dst;
427	}
428
429	if (xf86_crtc->filter)
430	    SetPicturePictFilter(src, xf86_crtc->filter, xf86_crtc->params,
431				 xf86_crtc->nparams);
432
433	extents.x1 += xf86_crtc->x - (xf86_crtc->filter_width >> 1);
434	extents.x2 += xf86_crtc->x + (xf86_crtc->filter_width >> 1);
435	extents.y1 += xf86_crtc->y - (xf86_crtc->filter_height >> 1);
436	extents.y2 += xf86_crtc->y + (xf86_crtc->filter_height >> 1);
437	pixman_f_transform_bounds(&xf86_crtc->f_framebuffer_to_crtc, &extents);
438
439	pScreen->SourceValidate = NULL;
440	CompositePicture(PictOpSrc,
441			 src, NULL, dst,
442			 extents.x1, extents.y1, 0, 0, extents.x1,
443			 extents.y1, extents.x2 - extents.x1,
444			 extents.y2 - extents.y1);
445	pScreen->SourceValidate = SourceValidate;
446
447 free_dst:
448	FreePicture(dst, None);
449 free_src:
450	FreePicture(src, None);
451    } else
452 out:
453#endif /* XF86_CRTC_VERSION >= 4 */
454    {
455	GCPtr gc = GetScratchGC(pDraw->depth, pScreen);
456
457	ValidateGC(pDraw, gc);
458	(*gc->ops->CopyArea)(&pScreen->GetScreenPixmap(pScreen)->drawable,
459			     pDraw, gc,
460			     xf86_crtc->x + extents.x1, xf86_crtc->y + extents.y1,
461			     extents.x2 - extents.x1, extents.y2 - extents.y1,
462			     extents.x1, extents.y1);
463	FreeScratchGC(gc);
464    }
465
466    radeon_cs_flush_indirect(scrn);
467
468    info->accel_state->force = force;
469
470    return TRUE;
471}
472
473static void
474radeon_scanout_update_abort(xf86CrtcPtr crtc, void *event_data)
475{
476    drmmode_crtc_private_ptr drmmode_crtc = event_data;
477
478    drmmode_crtc->scanout_update_pending = FALSE;
479}
480
481void
482radeon_scanout_update_handler(xf86CrtcPtr crtc, uint32_t frame, uint64_t usec,
483			      void *event_data)
484{
485    radeon_scanout_do_update(crtc, 0);
486
487    radeon_scanout_update_abort(crtc, event_data);
488}
489
490static void
491radeon_scanout_update(xf86CrtcPtr xf86_crtc)
492{
493    drmmode_crtc_private_ptr drmmode_crtc = xf86_crtc->driver_private;
494    uintptr_t drm_queue_seq;
495    ScrnInfoPtr scrn;
496    drmVBlank vbl;
497    DamagePtr pDamage;
498    RegionPtr pRegion;
499    DrawablePtr pDraw;
500    BoxRec extents;
501
502    if (!xf86_crtc->enabled ||
503	drmmode_crtc->scanout_update_pending ||
504	!drmmode_crtc->scanout[0].pixmap ||
505	drmmode_crtc->dpms_mode != DPMSModeOn)
506	return;
507
508    pDamage = drmmode_crtc->scanout[0].damage;
509    if (!pDamage)
510	return;
511
512    pRegion = DamageRegion(pDamage);
513    if (!RegionNotEmpty(pRegion))
514	return;
515
516    pDraw = &drmmode_crtc->scanout[0].pixmap->drawable;
517    extents = *RegionExtents(pRegion);
518    if (!radeon_scanout_extents_intersect(xf86_crtc, &extents, pDraw->width,
519					  pDraw->height))
520	return;
521
522    scrn = xf86_crtc->scrn;
523    drm_queue_seq = radeon_drm_queue_alloc(xf86_crtc,
524					   RADEON_DRM_QUEUE_CLIENT_DEFAULT,
525					   RADEON_DRM_QUEUE_ID_DEFAULT,
526					   drmmode_crtc,
527					   radeon_scanout_update_handler,
528					   radeon_scanout_update_abort);
529    if (!drm_queue_seq) {
530	xf86DrvMsg(scrn->scrnIndex, X_WARNING,
531		   "radeon_drm_queue_alloc failed for scanout update\n");
532	return;
533    }
534
535    vbl.request.type = DRM_VBLANK_RELATIVE | DRM_VBLANK_EVENT;
536    vbl.request.type |= radeon_populate_vbl_request_type(xf86_crtc);
537    vbl.request.sequence = 1;
538    vbl.request.signal = drm_queue_seq;
539    if (drmWaitVBlank(RADEONPTR(scrn)->dri2.drm_fd, &vbl)) {
540	xf86DrvMsg(scrn->scrnIndex, X_WARNING,
541		   "drmWaitVBlank failed for scanout update: %s\n",
542		   strerror(errno));
543	radeon_drm_abort_entry(drm_queue_seq);
544	return;
545    }
546
547    drmmode_crtc->scanout_update_pending = TRUE;
548}
549
550static void
551radeon_scanout_flip_abort(xf86CrtcPtr crtc, void *event_data)
552{
553    drmmode_crtc_private_ptr drmmode_crtc = event_data;
554
555    drmmode_crtc->scanout_update_pending = FALSE;
556    drmmode_crtc->flip_pending = FALSE;
557}
558
559static void
560radeon_scanout_flip(ScreenPtr pScreen, RADEONInfoPtr info,
561		    xf86CrtcPtr xf86_crtc)
562{
563    drmmode_crtc_private_ptr drmmode_crtc = xf86_crtc->driver_private;
564    ScrnInfoPtr scrn;
565    uintptr_t drm_queue_seq;
566    unsigned scanout_id;
567
568    if (drmmode_crtc->scanout_update_pending)
569	return;
570
571    scanout_id = drmmode_crtc->scanout_id ^ 1;
572    if (!radeon_scanout_do_update(xf86_crtc, scanout_id))
573	return;
574
575    scrn = xf86_crtc->scrn;
576    drm_queue_seq = radeon_drm_queue_alloc(xf86_crtc,
577					   RADEON_DRM_QUEUE_CLIENT_DEFAULT,
578					   RADEON_DRM_QUEUE_ID_DEFAULT,
579					   drmmode_crtc, NULL,
580					   radeon_scanout_flip_abort);
581    if (!drm_queue_seq) {
582	xf86DrvMsg(scrn->scrnIndex, X_WARNING,
583		   "Allocating DRM event queue entry failed.\n");
584	return;
585    }
586
587    if (drmModePageFlip(drmmode_crtc->drmmode->fd, drmmode_crtc->mode_crtc->crtc_id,
588			drmmode_crtc->scanout[scanout_id].fb_id,
589			DRM_MODE_PAGE_FLIP_EVENT, (void*)drm_queue_seq)) {
590	xf86DrvMsg(scrn->scrnIndex, X_WARNING, "flip queue failed in %s: %s\n",
591		   __func__, strerror(errno));
592	return;
593    }
594
595    drmmode_crtc->scanout_id = scanout_id;
596    drmmode_crtc->scanout_update_pending = TRUE;
597    drmmode_crtc->flip_pending = TRUE;
598}
599
600static void RADEONBlockHandler_KMS(BLOCKHANDLER_ARGS_DECL)
601{
602    SCREEN_PTR(arg);
603    ScrnInfoPtr    pScrn   = xf86ScreenToScrn(pScreen);
604    RADEONInfoPtr  info    = RADEONPTR(pScrn);
605    xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
606    int c;
607
608    pScreen->BlockHandler = info->BlockHandler;
609    (*pScreen->BlockHandler) (BLOCKHANDLER_ARGS);
610    pScreen->BlockHandler = RADEONBlockHandler_KMS;
611
612    for (c = 0; c < xf86_config->num_crtc; c++) {
613	if (info->tear_free)
614	    radeon_scanout_flip(pScreen, info, xf86_config->crtc[c]);
615	else if (info->shadow_primary
616#if XF86_CRTC_VERSION >= 4
617		 || xf86_config->crtc[c]->driverIsPerformingTransform
618#endif
619	    )
620	    radeon_scanout_update(xf86_config->crtc[c]);
621    }
622
623    radeon_cs_flush_indirect(pScrn);
624
625#ifdef RADEON_PIXMAP_SHARING
626    radeon_dirty_update(pScreen);
627#endif
628}
629
630static void RADEONBlockHandler_oneshot(BLOCKHANDLER_ARGS_DECL)
631{
632    SCREEN_PTR(arg);
633    ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen);
634    RADEONInfoPtr info = RADEONPTR(pScrn);
635
636    RADEONBlockHandler_KMS(BLOCKHANDLER_ARGS);
637
638    drmmode_set_desired_modes(pScrn, &info->drmmode, TRUE);
639}
640
641static void
642radeon_flush_callback(CallbackListPtr *list,
643		      pointer user_data, pointer call_data)
644{
645    ScrnInfoPtr pScrn = user_data;
646
647    if (pScrn->vtSema)
648        radeon_cs_flush_indirect(pScrn);
649}
650
651static Bool RADEONIsFastFBWorking(ScrnInfoPtr pScrn)
652{
653    RADEONInfoPtr info = RADEONPTR(pScrn);
654    struct drm_radeon_info ginfo;
655    int r;
656    uint32_t tmp = 0;
657
658    memset(&ginfo, 0, sizeof(ginfo));
659    ginfo.request = RADEON_INFO_FASTFB_WORKING;
660    ginfo.value = (uintptr_t)&tmp;
661    r = drmCommandWriteRead(info->dri2.drm_fd, DRM_RADEON_INFO, &ginfo, sizeof(ginfo));
662    if (r) {
663	return FALSE;
664    }
665    if (tmp == 1)
666	return TRUE;
667    return FALSE;
668}
669
670static Bool RADEONIsFusionGARTWorking(ScrnInfoPtr pScrn)
671{
672    RADEONInfoPtr info = RADEONPTR(pScrn);
673    struct drm_radeon_info ginfo;
674    int r;
675    uint32_t tmp;
676
677    memset(&ginfo, 0, sizeof(ginfo));
678    ginfo.request = RADEON_INFO_FUSION_GART_WORKING;
679    ginfo.value = (uintptr_t)&tmp;
680    r = drmCommandWriteRead(info->dri2.drm_fd, DRM_RADEON_INFO, &ginfo, sizeof(ginfo));
681    if (r) {
682	return FALSE;
683    }
684    if (tmp == 1)
685	return TRUE;
686    return FALSE;
687}
688
689static Bool RADEONIsAccelWorking(ScrnInfoPtr pScrn)
690{
691    RADEONInfoPtr info = RADEONPTR(pScrn);
692    struct drm_radeon_info ginfo;
693    int r;
694    uint32_t tmp;
695
696    memset(&ginfo, 0, sizeof(ginfo));
697    if (info->dri2.pKernelDRMVersion->version_minor >= 5)
698	ginfo.request = RADEON_INFO_ACCEL_WORKING2;
699    else
700	ginfo.request = RADEON_INFO_ACCEL_WORKING;
701    ginfo.value = (uintptr_t)&tmp;
702    r = drmCommandWriteRead(info->dri2.drm_fd, DRM_RADEON_INFO, &ginfo, sizeof(ginfo));
703    if (r) {
704        /* If kernel is too old before 2.6.32 than assume accel is working */
705        if (r == -EINVAL) {
706            xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Kernel too old missing accel "
707                       "information, assuming accel is working\n");
708            return TRUE;
709        }
710        return FALSE;
711    }
712    if (info->ChipFamily == CHIP_FAMILY_HAWAII) {
713        if (tmp == 2 || tmp == 3)
714            return TRUE;
715    } else if (tmp) {
716        return TRUE;
717    }
718    return FALSE;
719}
720
721/* This is called by RADEONPreInit to set up the default visual */
722static Bool RADEONPreInitVisual(ScrnInfoPtr pScrn)
723{
724    RADEONInfoPtr  info = RADEONPTR(pScrn);
725
726    if (!xf86SetDepthBpp(pScrn, 0, 0, 0, Support32bppFb))
727	return FALSE;
728
729    switch (pScrn->depth) {
730    case 8:
731    case 15:
732    case 16:
733    case 24:
734	break;
735
736    default:
737	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
738		   "Given depth (%d) is not supported by %s driver\n",
739		   pScrn->depth, RADEON_DRIVER_NAME);
740	return FALSE;
741    }
742
743    xf86PrintDepthBpp(pScrn);
744
745    info->pix24bpp                   = xf86GetBppFromDepth(pScrn,
746							   pScrn->depth);
747    info->pixel_bytes  = pScrn->bitsPerPixel / 8;
748
749    if (info->pix24bpp == 24) {
750	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
751		   "Radeon does NOT support 24bpp\n");
752	return FALSE;
753    }
754
755    xf86DrvMsg(pScrn->scrnIndex, X_INFO,
756	       "Pixel depth = %d bits stored in %d byte%s (%d bpp pixmaps)\n",
757	       pScrn->depth,
758	       info->pixel_bytes,
759	       info->pixel_bytes > 1 ? "s" : "",
760	       info->pix24bpp);
761
762    if (!xf86SetDefaultVisual(pScrn, -1)) return FALSE;
763
764    if (pScrn->depth > 8 && pScrn->defaultVisual != TrueColor) {
765	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
766		   "Default visual (%s) is not supported at depth %d\n",
767		   xf86GetVisualName(pScrn->defaultVisual), pScrn->depth);
768	return FALSE;
769    }
770    return TRUE;
771}
772
773/* This is called by RADEONPreInit to handle all color weight issues */
774static Bool RADEONPreInitWeight(ScrnInfoPtr pScrn)
775{
776    RADEONInfoPtr  info = RADEONPTR(pScrn);
777
778				/* Save flag for 6 bit DAC to use for
779				   setting CRTC registers.  Otherwise use
780				   an 8 bit DAC, even if xf86SetWeight sets
781				   pScrn->rgbBits to some value other than
782				   8. */
783    info->dac6bits = FALSE;
784
785    if (pScrn->depth > 8) {
786	rgb  defaultWeight = { 0, 0, 0 };
787
788	if (!xf86SetWeight(pScrn, defaultWeight, defaultWeight)) return FALSE;
789    } else {
790	pScrn->rgbBits = 8;
791    }
792
793    xf86DrvMsg(pScrn->scrnIndex, X_INFO,
794	       "Using %d bits per RGB (%d bit DAC)\n",
795	       pScrn->rgbBits, info->dac6bits ? 6 : 8);
796
797    return TRUE;
798}
799
800static Bool RADEONPreInitAccel_KMS(ScrnInfoPtr pScrn)
801{
802    RADEONInfoPtr  info = RADEONPTR(pScrn);
803
804    if (!(info->accel_state = calloc(1, sizeof(struct radeon_accel_state)))) {
805	xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unable to allocate accel_state rec!\n");
806	return FALSE;
807    }
808
809    /* Check whether direct mapping is used for fast fb access*/
810    if (RADEONIsFastFBWorking(pScrn)) {
811	xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct mapping of fb aperture is enabled for fast fb access.\n");
812	info->is_fast_fb = TRUE;
813    }
814
815    if (!xf86ReturnOptValBool(info->Options, OPTION_ACCEL, TRUE) ||
816	(!RADEONIsAccelWorking(pScrn))) {
817	xf86DrvMsg(pScrn->scrnIndex, X_INFO,
818		   "GPU accel disabled or not working, using shadowfb for KMS\n");
819shadowfb:
820	info->r600_shadow_fb = TRUE;
821	if (!xf86LoadSubModule(pScrn, "shadow"))
822	    info->r600_shadow_fb = FALSE;
823	return TRUE;
824    }
825
826#ifdef DRI2
827    info->dri2.available = !!xf86LoadSubModule(pScrn, "dri2");
828#endif
829
830    if (radeon_glamor_pre_init(pScrn))
831	return TRUE;
832
833    if (info->ChipFamily >= CHIP_FAMILY_TAHITI) {
834	goto shadowfb;
835    } else if (info->ChipFamily == CHIP_FAMILY_PALM) {
836	info->accel_state->allowHWDFS = RADEONIsFusionGARTWorking(pScrn);
837    } else
838	info->accel_state->allowHWDFS = TRUE;
839
840    if ((info->ChipFamily == CHIP_FAMILY_RS100) ||
841	(info->ChipFamily == CHIP_FAMILY_RS200) ||
842	(info->ChipFamily == CHIP_FAMILY_RS300) ||
843	(info->ChipFamily == CHIP_FAMILY_RS400) ||
844	(info->ChipFamily == CHIP_FAMILY_RS480) ||
845	(info->ChipFamily == CHIP_FAMILY_RS600) ||
846	(info->ChipFamily == CHIP_FAMILY_RS690) ||
847	(info->ChipFamily == CHIP_FAMILY_RS740))
848	info->accel_state->has_tcl = FALSE;
849    else {
850	info->accel_state->has_tcl = TRUE;
851    }
852
853    {
854	int errmaj = 0, errmin = 0;
855	info->exaReq.majorversion = EXA_VERSION_MAJOR;
856	info->exaReq.minorversion = EXA_VERSION_MINOR;
857	if (!LoadSubModule(pScrn->module, "exa", NULL, NULL, NULL,
858			   &info->exaReq, &errmaj, &errmin)) {
859	    LoaderErrorMsg(NULL, "exa", errmaj, errmin);
860	    return FALSE;
861	}
862    }
863
864    return TRUE;
865}
866
867static Bool RADEONPreInitChipType_KMS(ScrnInfoPtr pScrn)
868{
869    RADEONInfoPtr  info   = RADEONPTR(pScrn);
870    int i;
871
872    info->Chipset = PCI_DEV_DEVICE_ID(info->PciInfo);
873    pScrn->chipset = (char *)xf86TokenToString(RADEONChipsets, info->Chipset);
874    if (!pScrn->chipset) {
875	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
876		   "ChipID 0x%04x is not recognized\n", info->Chipset);
877	return FALSE;
878    }
879
880    if (info->Chipset < 0) {
881	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
882		   "Chipset \"%s\" is not recognized\n", pScrn->chipset);
883	return FALSE;
884    }
885    xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
886	       "Chipset: \"%s\" (ChipID = 0x%04x)\n",
887	       pScrn->chipset,
888	       info->Chipset);
889
890    for (i = 0; i < sizeof(RADEONCards) / sizeof(RADEONCardInfo); i++) {
891	if (info->Chipset == RADEONCards[i].pci_device_id) {
892	    RADEONCardInfo *card = &RADEONCards[i];
893	    info->ChipFamily = card->chip_family;
894	    break;
895	}
896    }
897
898#ifdef RENDER
899    info->RenderAccel = xf86ReturnOptValBool(info->Options, OPTION_RENDER_ACCEL,
900					     info->Chipset != PCI_CHIP_RN50_515E &&
901					     info->Chipset != PCI_CHIP_RN50_5969);
902#endif
903    return TRUE;
904}
905
906static int radeon_get_drm_master_fd(ScrnInfoPtr pScrn)
907{
908    RADEONInfoPtr  info   = RADEONPTR(pScrn);
909#ifdef XF86_PDEV_SERVER_FD
910    RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
911#endif
912    struct pci_device *dev = info->PciInfo;
913    char *busid;
914    int fd;
915
916#ifdef XF86_PDEV_SERVER_FD
917    if (pRADEONEnt->platform_dev) {
918        fd = xf86_get_platform_device_int_attrib(pRADEONEnt->platform_dev,
919                                                 ODEV_ATTRIB_FD, -1);
920        if (fd != -1)
921            return fd;
922    }
923#endif
924
925#if XORG_VERSION_CURRENT >= XORG_VERSION_NUMERIC(1,9,99,901,0)
926    XNFasprintf(&busid, "pci:%04x:%02x:%02x.%d",
927                dev->domain, dev->bus, dev->dev, dev->func);
928#else
929    busid = XNFprintf("pci:%04x:%02x:%02x.%d",
930		      dev->domain, dev->bus, dev->dev, dev->func);
931#endif
932
933    fd = drmOpen(NULL, busid);
934    if (fd == -1)
935	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
936		   "[drm] Failed to open DRM device for %s: %s\n",
937		   busid, strerror(errno));
938
939    free(busid);
940    return fd;
941}
942
943static Bool radeon_open_drm_master(ScrnInfoPtr pScrn)
944{
945    RADEONInfoPtr  info   = RADEONPTR(pScrn);
946    RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
947    drmSetVersion sv;
948    int err;
949
950    if (pRADEONEnt->fd) {
951	xf86DrvMsg(pScrn->scrnIndex, X_INFO,
952		   " reusing fd for second head\n");
953
954	info->drmmode.fd = info->dri2.drm_fd = pRADEONEnt->fd;
955	pRADEONEnt->fd_ref++;
956        return TRUE;
957    }
958
959    info->dri2.drm_fd = radeon_get_drm_master_fd(pScrn);
960    if (info->dri2.drm_fd == -1)
961	return FALSE;
962
963    /* Check that what we opened was a master or a master-capable FD,
964     * by setting the version of the interface we'll use to talk to it.
965     * (see DRIOpenDRMMaster() in DRI1)
966     */
967    sv.drm_di_major = 1;
968    sv.drm_di_minor = 1;
969    sv.drm_dd_major = -1;
970    sv.drm_dd_minor = -1;
971    err = drmSetInterfaceVersion(info->dri2.drm_fd, &sv);
972    if (err != 0) {
973	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
974		   "[drm] failed to set drm interface version.\n");
975	drmClose(info->dri2.drm_fd);
976	info->dri2.drm_fd = -1;
977
978	return FALSE;
979    }
980
981    pRADEONEnt->fd = info->dri2.drm_fd;
982    pRADEONEnt->fd_ref = 1;
983    info->drmmode.fd = info->dri2.drm_fd;
984    return TRUE;
985}
986
987static Bool r600_get_tile_config(ScrnInfoPtr pScrn)
988{
989    RADEONInfoPtr  info   = RADEONPTR(pScrn);
990    struct drm_radeon_info ginfo;
991    int r;
992    uint32_t tmp;
993
994    if (info->ChipFamily < CHIP_FAMILY_R600)
995	return FALSE;
996
997    memset(&ginfo, 0, sizeof(ginfo));
998    ginfo.request = RADEON_INFO_TILING_CONFIG;
999    ginfo.value = (uintptr_t)&tmp;
1000    r = drmCommandWriteRead(info->dri2.drm_fd, DRM_RADEON_INFO, &ginfo, sizeof(ginfo));
1001    if (r)
1002	return FALSE;
1003
1004    info->tile_config = tmp;
1005    info->r7xx_bank_op = 0;
1006    if (info->ChipFamily >= CHIP_FAMILY_CEDAR) {
1007	if (info->dri2.pKernelDRMVersion->version_minor >= 7) {
1008	    switch (info->tile_config & 0xf) {
1009	    case 0:
1010                info->num_channels = 1;
1011                break;
1012	    case 1:
1013                info->num_channels = 2;
1014                break;
1015	    case 2:
1016                info->num_channels = 4;
1017                break;
1018	    case 3:
1019                info->num_channels = 8;
1020                break;
1021	    default:
1022                return FALSE;
1023	    }
1024
1025	    switch((info->tile_config & 0xf0) >> 4) {
1026	    case 0:
1027		info->num_banks = 4;
1028		break;
1029	    case 1:
1030		info->num_banks = 8;
1031		break;
1032	    case 2:
1033		info->num_banks = 16;
1034		break;
1035	    default:
1036		return FALSE;
1037	    }
1038
1039	    switch ((info->tile_config & 0xf00) >> 8) {
1040	    case 0:
1041                info->group_bytes = 256;
1042                break;
1043	    case 1:
1044                info->group_bytes = 512;
1045                break;
1046	    default:
1047                return FALSE;
1048	    }
1049	} else
1050	    return FALSE;
1051    } else {
1052	switch((info->tile_config & 0xe) >> 1) {
1053	case 0:
1054	    info->num_channels = 1;
1055	    break;
1056	case 1:
1057	    info->num_channels = 2;
1058	    break;
1059	case 2:
1060	    info->num_channels = 4;
1061	    break;
1062	case 3:
1063	    info->num_channels = 8;
1064	    break;
1065	default:
1066	    return FALSE;
1067	}
1068	switch((info->tile_config & 0x30) >> 4) {
1069	case 0:
1070	    info->num_banks = 4;
1071	    break;
1072	case 1:
1073	    info->num_banks = 8;
1074	    break;
1075	default:
1076	    return FALSE;
1077	}
1078	switch((info->tile_config & 0xc0) >> 6) {
1079	case 0:
1080	    info->group_bytes = 256;
1081	    break;
1082	case 1:
1083	    info->group_bytes = 512;
1084	    break;
1085	default:
1086	    return FALSE;
1087	}
1088    }
1089
1090    info->have_tiling_info = TRUE;
1091    return TRUE;
1092}
1093
1094static void RADEONSetupCapabilities(ScrnInfoPtr pScrn)
1095{
1096#ifdef RADEON_PIXMAP_SHARING
1097    RADEONInfoPtr  info = RADEONPTR(pScrn);
1098    uint64_t value;
1099    int ret;
1100
1101    pScrn->capabilities = 0;
1102
1103    /* PRIME offloading requires acceleration */
1104    if (info->r600_shadow_fb)
1105	return;
1106
1107    ret = drmGetCap(info->dri2.drm_fd, DRM_CAP_PRIME, &value);
1108    if (ret == 0) {
1109	if (value & DRM_PRIME_CAP_EXPORT)
1110	    pScrn->capabilities |= RR_Capability_SourceOutput | RR_Capability_SinkOffload;
1111	if (value & DRM_PRIME_CAP_IMPORT)
1112	    pScrn->capabilities |= RR_Capability_SinkOutput | RR_Capability_SourceOffload;
1113    }
1114#endif
1115}
1116
1117#if GET_ABI_MAJOR(ABI_VIDEODRV_VERSION) >= 10
1118
1119/* When the root window is created, initialize the screen contents from
1120 * console if -background none was specified on the command line
1121 */
1122static Bool RADEONCreateWindow_oneshot(WindowPtr pWin)
1123{
1124    ScreenPtr pScreen = pWin->drawable.pScreen;
1125    ScrnInfoPtr pScrn;
1126    RADEONInfoPtr info;
1127    Bool ret;
1128
1129    if (pWin != pScreen->root)
1130	ErrorF("%s called for non-root window %p\n", __func__, pWin);
1131
1132    pScrn = xf86ScreenToScrn(pScreen);
1133    info = RADEONPTR(pScrn);
1134    pScreen->CreateWindow = info->CreateWindow;
1135    ret = pScreen->CreateWindow(pWin);
1136
1137    if (ret)
1138	drmmode_copy_fb(pScrn, &info->drmmode);
1139
1140    return ret;
1141}
1142
1143#endif
1144
1145Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int flags)
1146{
1147    RADEONInfoPtr     info;
1148    RADEONEntPtr pRADEONEnt;
1149    DevUnion* pPriv;
1150    Gamma  zeros = { 0.0, 0.0, 0.0 };
1151    uint32_t tiling = 0;
1152    int cpp;
1153
1154    if (flags & PROBE_DETECT)
1155        return TRUE;
1156
1157    xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
1158		   "RADEONPreInit_KMS\n");
1159    if (pScrn->numEntities != 1) return FALSE;
1160    if (!RADEONGetRec(pScrn)) return FALSE;
1161
1162    info               = RADEONPTR(pScrn);
1163    info->IsSecondary  = FALSE;
1164    info->pEnt         = xf86GetEntityInfo(pScrn->entityList[pScrn->numEntities - 1]);
1165    if (info->pEnt->location.type != BUS_PCI
1166#ifdef XSERVER_PLATFORM_BUS
1167        && info->pEnt->location.type != BUS_PLATFORM
1168#endif
1169        )
1170        goto fail;
1171
1172    pPriv = xf86GetEntityPrivate(pScrn->entityList[0],
1173				 getRADEONEntityIndex());
1174    pRADEONEnt = pPriv->ptr;
1175
1176    if(xf86IsEntityShared(pScrn->entityList[0]))
1177    {
1178        if(xf86IsPrimInitDone(pScrn->entityList[0]))
1179        {
1180            info->IsSecondary = TRUE;
1181        }
1182        else
1183        {
1184            xf86SetPrimInitDone(pScrn->entityList[0]);
1185        }
1186    }
1187
1188    info->PciInfo = xf86GetPciInfoForEntity(info->pEnt->index);
1189    pScrn->monitor     = pScrn->confScreen->monitor;
1190
1191    if (!RADEONPreInitVisual(pScrn))
1192	goto fail;
1193
1194    xf86CollectOptions(pScrn, NULL);
1195    if (!(info->Options = malloc(sizeof(RADEONOptions_KMS))))
1196	goto fail;
1197
1198    memcpy(info->Options, RADEONOptions_KMS, sizeof(RADEONOptions_KMS));
1199    xf86ProcessOptions(pScrn->scrnIndex, pScrn->options, info->Options);
1200
1201    if (!RADEONPreInitWeight(pScrn))
1202	goto fail;
1203
1204    if (!RADEONPreInitChipType_KMS(pScrn))
1205        goto fail;
1206
1207    if (radeon_open_drm_master(pScrn) == FALSE) {
1208	xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Kernel modesetting setup failed\n");
1209	goto fail;
1210    }
1211
1212    info->dri2.available = FALSE;
1213    info->dri2.enabled = FALSE;
1214    info->dri2.pKernelDRMVersion = drmGetVersion(info->dri2.drm_fd);
1215    if (info->dri2.pKernelDRMVersion == NULL) {
1216	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1217		   "RADEONDRIGetVersion failed to get the DRM version\n");
1218	goto fail;
1219    }
1220
1221    /* Get ScreenInit function */
1222    if (!xf86LoadSubModule(pScrn, "fb"))
1223	return FALSE;
1224
1225    if (!RADEONPreInitAccel_KMS(pScrn))              goto fail;
1226
1227    radeon_drm_queue_init();
1228
1229    info->allowColorTiling2D = FALSE;
1230
1231    RADEONSetupCapabilities(pScrn);
1232
1233    /* don't enable tiling if accel is not enabled */
1234    if (!info->r600_shadow_fb) {
1235	Bool colorTilingDefault =
1236	    xorgGetVersion() >= XORG_VERSION_NUMERIC(1,9,4,901,0) &&
1237	    info->ChipFamily >= CHIP_FAMILY_R300 &&
1238	    /* this check could be removed sometime after a big mesa release
1239	     * with proper bit, in the meantime you need to set tiling option in
1240	     * xorg configuration files
1241	     */
1242	    info->ChipFamily <= CHIP_FAMILY_MULLINS &&
1243	    !info->is_fast_fb;
1244
1245	/* 2D color tiling */
1246	if (info->ChipFamily >= CHIP_FAMILY_R600) {
1247		info->allowColorTiling2D = xf86ReturnOptValBool(info->Options, OPTION_COLOR_TILING_2D,
1248                                                                info->ChipFamily <= CHIP_FAMILY_MULLINS);
1249	}
1250
1251	if (info->ChipFamily >= CHIP_FAMILY_R600) {
1252	    /* set default group bytes, overridden by kernel info below */
1253	    info->group_bytes = 256;
1254	    info->have_tiling_info = FALSE;
1255	    if (info->dri2.pKernelDRMVersion->version_minor >= 6) {
1256		if (r600_get_tile_config(pScrn)) {
1257		    info->allowColorTiling = xf86ReturnOptValBool(info->Options,
1258								  OPTION_COLOR_TILING, colorTilingDefault);
1259		    /* need working DFS for tiling */
1260		    if ((info->ChipFamily == CHIP_FAMILY_PALM) &&
1261			(!info->accel_state->allowHWDFS))
1262			info->allowColorTiling = FALSE;
1263		} else
1264		    info->allowColorTiling = FALSE;
1265	    } else
1266		xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1267			   "R6xx+ KMS Color Tiling requires radeon drm 2.6.0 or newer\n");
1268	} else
1269	    info->allowColorTiling = xf86ReturnOptValBool(info->Options,
1270							  OPTION_COLOR_TILING, colorTilingDefault);
1271    } else
1272	info->allowColorTiling = FALSE;
1273
1274    xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1275	 "KMS Color Tiling: %sabled\n", info->allowColorTiling ? "en" : "dis");
1276    xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1277	 "KMS Color Tiling 2D: %sabled\n", info->allowColorTiling2D ? "en" : "dis");
1278
1279#if USE_GLAMOR
1280    if (info->use_glamor) {
1281	info->shadow_primary = xf86ReturnOptValBool(info->Options,
1282						   OPTION_SHADOW_PRIMARY, FALSE);
1283
1284	if (info->shadow_primary)
1285	    xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "ShadowPrimary enabled\n");
1286    }
1287#endif
1288
1289    if (!info->r600_shadow_fb) {
1290	info->tear_free = xf86ReturnOptValBool(info->Options, OPTION_TEAR_FREE,
1291					       FALSE);
1292
1293	if (info->tear_free)
1294	    xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "TearFree enabled\n");
1295    }
1296
1297    if (info->dri2.pKernelDRMVersion->version_minor >= 8) {
1298	Bool sw_cursor = xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE);
1299
1300	info->allowPageFlip = xf86ReturnOptValBool(info->Options,
1301						   OPTION_PAGE_FLIP, TRUE);
1302
1303	if (sw_cursor || info->tear_free || info->shadow_primary) {
1304	    xf86DrvMsg(pScrn->scrnIndex,
1305		       info->allowPageFlip ? X_WARNING : X_DEFAULT,
1306		       "KMS Pageflipping: disabled%s\n",
1307		       info->allowPageFlip ?
1308		       (sw_cursor ? " because of SWcursor" :
1309			" because of ShadowPrimary/TearFree") : "");
1310	    info->allowPageFlip = FALSE;
1311	} else {
1312	    xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1313		       "KMS Pageflipping: %sabled\n", info->allowPageFlip ? "en" : "dis");
1314	}
1315    }
1316
1317    info->swapBuffersWait = xf86ReturnOptValBool(info->Options,
1318						 OPTION_SWAPBUFFERS_WAIT, TRUE);
1319    xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1320	       "SwapBuffers wait for vsync: %sabled\n", info->swapBuffersWait ? "en" : "dis");
1321
1322    if (xf86ReturnOptValBool(info->Options, OPTION_DELETE_DP12, FALSE)) {
1323        info->drmmode.delete_dp_12_displays = TRUE;
1324    }
1325
1326    if (drmmode_pre_init(pScrn, &info->drmmode, pScrn->bitsPerPixel / 8) == FALSE) {
1327	xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Kernel modesetting setup failed\n");
1328	goto fail;
1329    }
1330
1331    if (info->drmmode.count_crtcs == 1)
1332        pRADEONEnt->HasCRTC2 = FALSE;
1333    else
1334        pRADEONEnt->HasCRTC2 = TRUE;
1335
1336
1337    /* fix up cloning on rn50 cards
1338     * since they only have one crtc sometimes the xserver doesn't assign
1339     * a crtc to one of the outputs even though both outputs have common modes
1340     * which results in only one monitor being enabled.  Assign a crtc here so
1341     * that both outputs light up.
1342     */
1343    if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2) {
1344	xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
1345	int i;
1346
1347	for (i = 0; i < xf86_config->num_output; i++) {
1348	    xf86OutputPtr output = xf86_config->output[i];
1349
1350	    /* XXX: double check crtc mode */
1351	    if ((output->probed_modes != NULL) && (output->crtc == NULL))
1352		output->crtc = xf86_config->crtc[0];
1353	}
1354    }
1355
1356    /* set cursor size */
1357    if (info->ChipFamily >= CHIP_FAMILY_BONAIRE) {
1358	info->cursor_w = CURSOR_WIDTH_CIK;
1359	info->cursor_h = CURSOR_HEIGHT_CIK;
1360    } else {
1361	info->cursor_w = CURSOR_WIDTH;
1362	info->cursor_h = CURSOR_HEIGHT;
1363    }
1364
1365    {
1366	struct drm_radeon_gem_info mminfo;
1367
1368	if (!drmCommandWriteRead(info->dri2.drm_fd, DRM_RADEON_GEM_INFO, &mminfo, sizeof(mminfo)))
1369	{
1370	    info->vram_size = mminfo.vram_visible;
1371	    info->gart_size = mminfo.gart_size;
1372	    xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1373		       "mem size init: gart size :%llx vram size: s:%llx visible:%llx\n",
1374		       (unsigned long long)mminfo.gart_size,
1375		       (unsigned long long)mminfo.vram_size,
1376		       (unsigned long long)mminfo.vram_visible);
1377	}
1378    }
1379
1380    if (!info->use_glamor) {
1381	info->exa_pixmaps = xf86ReturnOptValBool(info->Options,
1382						 OPTION_EXA_PIXMAPS,
1383						 (info->vram_size > (32 * 1024 * 1024) &&
1384						 info->RenderAccel &&
1385                                                 !info->is_fast_fb));
1386	if (info->exa_pixmaps)
1387	    xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1388		       "EXA: Driver will allow EXA pixmaps in VRAM\n");
1389	else
1390	    xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1391		       "EXA: Driver will not allow EXA pixmaps in VRAM\n");
1392    }
1393
1394    /* no tiled scanout on r6xx+ yet */
1395    if (info->allowColorTiling) {
1396	if (info->ChipFamily >= CHIP_FAMILY_R600)
1397	    tiling |= RADEON_TILING_MICRO;
1398	else
1399	    tiling |= RADEON_TILING_MACRO;
1400    }
1401    cpp = pScrn->bitsPerPixel / 8;
1402    pScrn->displayWidth =
1403	RADEON_ALIGN(pScrn->virtualX, drmmode_get_pitch_align(pScrn, cpp, tiling));
1404
1405    /* Set display resolution */
1406    xf86SetDpi(pScrn, 0, 0);
1407
1408    if (!xf86SetGamma(pScrn, zeros)) return FALSE;
1409
1410    if (!xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) {
1411	if (!xf86LoadSubModule(pScrn, "ramdac")) return FALSE;
1412    }
1413
1414    if (pScrn->modes == NULL
1415#ifdef XSERVER_PLATFORM_BUS
1416        && !pScrn->is_gpu
1417#endif
1418        ) {
1419      xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No modes.\n");
1420      goto fail;
1421   }
1422
1423    return TRUE;
1424 fail:
1425    RADEONFreeRec(pScrn);
1426    return FALSE;
1427
1428}
1429
1430static Bool RADEONCursorInit_KMS(ScreenPtr pScreen)
1431{
1432    ScrnInfoPtr    pScrn = xf86ScreenToScrn(pScreen);
1433    RADEONInfoPtr  info  = RADEONPTR(pScrn);
1434
1435    return xf86_cursors_init (pScreen, info->cursor_w, info->cursor_h,
1436			      (HARDWARE_CURSOR_TRUECOLOR_AT_8BPP |
1437			       HARDWARE_CURSOR_AND_SOURCE_WITH_MASK |
1438			       HARDWARE_CURSOR_SOURCE_MASK_INTERLEAVE_1 |
1439			       HARDWARE_CURSOR_UPDATE_UNHIDDEN |
1440			       HARDWARE_CURSOR_ARGB));
1441}
1442
1443void
1444RADEONBlank(ScrnInfoPtr pScrn)
1445{
1446    xf86CrtcConfigPtr   xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
1447    xf86OutputPtr output;
1448    xf86CrtcPtr crtc;
1449    int o, c;
1450
1451    for (c = 0; c < xf86_config->num_crtc; c++) {
1452       crtc = xf86_config->crtc[c];
1453       for (o = 0; o < xf86_config->num_output; o++) {
1454           output = xf86_config->output[o];
1455           if (output->crtc != crtc)
1456               continue;
1457
1458           output->funcs->dpms(output, DPMSModeOff);
1459       }
1460      crtc->funcs->dpms(crtc, DPMSModeOff);
1461    }
1462}
1463
1464void
1465RADEONUnblank(ScrnInfoPtr pScrn)
1466{
1467    xf86CrtcConfigPtr   xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
1468    xf86OutputPtr output;
1469    xf86CrtcPtr crtc;
1470    int o, c;
1471    for (c = 0; c < xf86_config->num_crtc; c++) {
1472       crtc = xf86_config->crtc[c];
1473       if(!crtc->enabled)
1474              continue;
1475       crtc->funcs->dpms(crtc, DPMSModeOn);
1476       for (o = 0; o < xf86_config->num_output; o++) {
1477           output = xf86_config->output[o];
1478           if (output->crtc != crtc)
1479               continue;
1480           output->funcs->dpms(output, DPMSModeOn);
1481       }
1482    }
1483}
1484
1485
1486static Bool RADEONSaveScreen_KMS(ScreenPtr pScreen, int mode)
1487{
1488    ScrnInfoPtr  pScrn = xf86ScreenToScrn(pScreen);
1489    Bool         unblank;
1490
1491    xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
1492		   "RADEONSaveScreen(%d)\n", mode);
1493
1494    unblank = xf86IsUnblank(mode);
1495    if (unblank) SetTimeSinceLastInputEvent();
1496
1497    if ((pScrn != NULL) && pScrn->vtSema) {
1498	if (unblank)
1499	    RADEONUnblank(pScrn);
1500	else
1501	    RADEONBlank(pScrn);
1502    }
1503    return TRUE;
1504}
1505
1506static Bool radeon_set_drm_master(ScrnInfoPtr pScrn)
1507{
1508    RADEONInfoPtr  info  = RADEONPTR(pScrn);
1509#ifdef XF86_PDEV_SERVER_FD
1510    RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
1511#endif
1512    int err;
1513
1514#ifdef XF86_PDEV_SERVER_FD
1515    if (pRADEONEnt->platform_dev &&
1516            (pRADEONEnt->platform_dev->flags & XF86_PDEV_SERVER_FD))
1517        return TRUE;
1518#endif
1519
1520    err = drmSetMaster(info->dri2.drm_fd);
1521    if (err)
1522        ErrorF("Unable to retrieve master\n");
1523
1524    return err == 0;
1525}
1526
1527static void radeon_drop_drm_master(ScrnInfoPtr pScrn)
1528{
1529    RADEONInfoPtr  info  = RADEONPTR(pScrn);
1530#ifdef XF86_PDEV_SERVER_FD
1531    RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
1532
1533    if (pRADEONEnt->platform_dev &&
1534            (pRADEONEnt->platform_dev->flags & XF86_PDEV_SERVER_FD))
1535        return;
1536#endif
1537
1538    drmDropMaster(info->dri2.drm_fd);
1539}
1540
1541/* Called at the end of each server generation.  Restore the original
1542 * text mode, unmap video memory, and unwrap and call the saved
1543 * CloseScreen function.
1544 */
1545static Bool RADEONCloseScreen_KMS(CLOSE_SCREEN_ARGS_DECL)
1546{
1547    ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen);
1548    RADEONInfoPtr  info  = RADEONPTR(pScrn);
1549    RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
1550
1551    xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
1552		   "RADEONCloseScreen\n");
1553
1554    /* Clear mask of assigned crtc's in this generation */
1555    pRADEONEnt->assigned_crtcs = 0;
1556
1557    drmmode_uevent_fini(pScrn, &info->drmmode);
1558    radeon_drm_queue_close(pScrn);
1559    radeon_cs_flush_indirect(pScrn);
1560
1561    DeleteCallback(&FlushCallback, radeon_flush_callback, pScrn);
1562
1563    if (info->accel_state->exa) {
1564	exaDriverFini(pScreen);
1565	free(info->accel_state->exa);
1566	info->accel_state->exa = NULL;
1567    }
1568
1569    radeon_sync_close(pScreen);
1570
1571    if (info->accel_state->use_vbos)
1572        radeon_vbo_free_lists(pScrn);
1573
1574    radeon_drop_drm_master(pScrn);
1575
1576    drmmode_fini(pScrn, &info->drmmode);
1577    if (info->dri2.enabled)
1578	radeon_dri2_close_screen(pScreen);
1579
1580    radeon_glamor_fini(pScreen);
1581
1582    pScrn->vtSema = FALSE;
1583    xf86ClearPrimInitDone(info->pEnt->index);
1584    pScreen->BlockHandler = info->BlockHandler;
1585    pScreen->CloseScreen = info->CloseScreen;
1586    return (*pScreen->CloseScreen)(CLOSE_SCREEN_ARGS);
1587}
1588
1589
1590void RADEONFreeScreen_KMS(FREE_SCREEN_ARGS_DECL)
1591{
1592    SCRN_INFO_PTR(arg);
1593    RADEONInfoPtr  info  = RADEONPTR(pScrn);
1594
1595    xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
1596		   "RADEONFreeScreen\n");
1597
1598    /* when server quits at PreInit, we don't need do this anymore*/
1599    if (!info) return;
1600
1601    RADEONFreeRec(pScrn);
1602}
1603
1604Bool RADEONScreenInit_KMS(SCREEN_INIT_ARGS_DECL)
1605{
1606    ScrnInfoPtr    pScrn = xf86ScreenToScrn(pScreen);
1607    RADEONInfoPtr  info  = RADEONPTR(pScrn);
1608    int            subPixelOrder = SubPixelUnknown;
1609    MessageType from;
1610    Bool value;
1611    int driLevel;
1612    const char *s;
1613    void *front_ptr;
1614
1615    pScrn->fbOffset = 0;
1616
1617    miClearVisualTypes();
1618    if (!miSetVisualTypes(pScrn->depth,
1619			  miGetDefaultVisualMask(pScrn->depth),
1620			  pScrn->rgbBits,
1621			  pScrn->defaultVisual)) return FALSE;
1622    miSetPixmapDepths ();
1623
1624    if (!radeon_set_drm_master(pScrn))
1625        return FALSE;
1626
1627    info->directRenderingEnabled = FALSE;
1628    if (info->r600_shadow_fb == FALSE)
1629        info->directRenderingEnabled = radeon_dri2_screen_init(pScreen);
1630
1631    info->surf_man = radeon_surface_manager_new(info->dri2.drm_fd);
1632    if (!info->bufmgr)
1633        info->bufmgr = radeon_bo_manager_gem_ctor(info->dri2.drm_fd);
1634    if (!info->bufmgr) {
1635	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1636		   "failed to initialise GEM buffer manager");
1637	return FALSE;
1638    }
1639    drmmode_set_bufmgr(pScrn, &info->drmmode, info->bufmgr);
1640
1641    if (!info->csm)
1642        info->csm = radeon_cs_manager_gem_ctor(info->dri2.drm_fd);
1643    if (!info->csm) {
1644	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1645		   "failed to initialise command submission manager");
1646	return FALSE;
1647    }
1648
1649    if (!info->cs)
1650        info->cs = radeon_cs_create(info->csm, RADEON_BUFFER_SIZE/4);
1651    if (!info->cs) {
1652	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1653		   "failed to initialise command submission buffer");
1654	return FALSE;
1655    }
1656
1657    radeon_cs_set_limit(info->cs, RADEON_GEM_DOMAIN_GTT, info->gart_size);
1658    radeon_cs_space_set_flush(info->cs, (void(*)(void *))radeon_cs_flush_indirect, pScrn);
1659
1660    if (!radeon_setup_kernel_mem(pScreen)) {
1661	xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "radeon_setup_kernel_mem failed\n");
1662	return FALSE;
1663    }
1664    front_ptr = info->front_bo->ptr;
1665
1666    if (info->r600_shadow_fb) {
1667	info->fb_shadow = calloc(1,
1668				 pScrn->displayWidth * pScrn->virtualY *
1669				 ((pScrn->bitsPerPixel + 7) >> 3));
1670	if (info->fb_shadow == NULL) {
1671	    xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1672                       "Failed to allocate shadow framebuffer\n");
1673	    info->r600_shadow_fb = FALSE;
1674	} else {
1675	    if (!fbScreenInit(pScreen, info->fb_shadow,
1676			      pScrn->virtualX, pScrn->virtualY,
1677			      pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth,
1678			      pScrn->bitsPerPixel))
1679		return FALSE;
1680	}
1681    }
1682
1683    if (info->r600_shadow_fb == FALSE) {
1684	/* Init fb layer */
1685	if (!fbScreenInit(pScreen, front_ptr,
1686			  pScrn->virtualX, pScrn->virtualY,
1687			  pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth,
1688			  pScrn->bitsPerPixel))
1689	    return FALSE;
1690    }
1691
1692    xf86SetBlackWhitePixels(pScreen);
1693
1694    if (pScrn->bitsPerPixel > 8) {
1695	VisualPtr  visual;
1696
1697	visual = pScreen->visuals + pScreen->numVisuals;
1698	while (--visual >= pScreen->visuals) {
1699	    if ((visual->class | DynamicClass) == DirectColor) {
1700		visual->offsetRed   = pScrn->offset.red;
1701		visual->offsetGreen = pScrn->offset.green;
1702		visual->offsetBlue  = pScrn->offset.blue;
1703		visual->redMask     = pScrn->mask.red;
1704		visual->greenMask   = pScrn->mask.green;
1705		visual->blueMask    = pScrn->mask.blue;
1706	    }
1707	}
1708    }
1709
1710    /* Must be after RGB order fixed */
1711    fbPictureInit (pScreen, 0, 0);
1712
1713#ifdef RENDER
1714    if ((s = xf86GetOptValString(info->Options, OPTION_SUBPIXEL_ORDER))) {
1715	if (strcmp(s, "RGB") == 0) subPixelOrder = SubPixelHorizontalRGB;
1716	else if (strcmp(s, "BGR") == 0) subPixelOrder = SubPixelHorizontalBGR;
1717	else if (strcmp(s, "NONE") == 0) subPixelOrder = SubPixelNone;
1718	PictureSetSubpixelOrder (pScreen, subPixelOrder);
1719    }
1720#endif
1721
1722    value = FALSE;
1723    from = X_DEFAULT;
1724
1725    if (!info->r600_shadow_fb) {
1726	if (xf86GetOptValBool(info->Options, OPTION_DRI3, &value))
1727	    from = X_CONFIG;
1728
1729	if (xf86GetOptValInteger(info->Options, OPTION_DRI, &driLevel) &&
1730	    (driLevel == 2 || driLevel == 3)) {
1731	    from = X_CONFIG;
1732	    value = driLevel == 3;
1733	}
1734    }
1735
1736    if (value) {
1737	value = radeon_sync_init(pScreen) &&
1738	    radeon_present_screen_init(pScreen) &&
1739	    radeon_dri3_screen_init(pScreen);
1740
1741	if (!value)
1742	    from = X_WARNING;
1743    }
1744
1745    xf86DrvMsg(pScrn->scrnIndex, from, "DRI3 %sabled\n", value ? "en" : "dis");
1746
1747    pScrn->vtSema = TRUE;
1748    xf86SetBackingStore(pScreen);
1749
1750    if (info->directRenderingEnabled) {
1751	xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct rendering enabled\n");
1752    } else {
1753	xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
1754		   "Direct rendering disabled\n");
1755    }
1756
1757    if (info->r600_shadow_fb) {
1758	xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Acceleration disabled\n");
1759	info->accelOn = FALSE;
1760    } else {
1761	xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
1762		       "Initializing Acceleration\n");
1763	if (RADEONAccelInit(pScreen)) {
1764	    xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Acceleration enabled\n");
1765	    info->accelOn = TRUE;
1766	} else {
1767	    xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1768		       "Acceleration initialization failed\n");
1769	    xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Acceleration disabled\n");
1770	    info->accelOn = FALSE;
1771	}
1772    }
1773
1774    /* Init DPMS */
1775    xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
1776		   "Initializing DPMS\n");
1777    xf86DPMSInit(pScreen, xf86DPMSSet, 0);
1778
1779    xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
1780		   "Initializing Cursor\n");
1781
1782    /* Set Silken Mouse */
1783    xf86SetSilkenMouse(pScreen);
1784
1785    /* Cursor setup */
1786    miDCInitialize(pScreen, xf86GetPointerScreenFuncs());
1787
1788    if (!xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) {
1789	if (RADEONCursorInit_KMS(pScreen)) {
1790	}
1791    }
1792
1793    /* DGA setup */
1794#ifdef XFreeXDGA
1795    /* DGA is dangerous on kms as the base and framebuffer location may change:
1796     * http://lists.freedesktop.org/archives/xorg-devel/2009-September/002113.html
1797     */
1798    /* xf86DiDGAInit(pScreen, info->LinearAddr + pScrn->fbOffset); */
1799#endif
1800    if (info->r600_shadow_fb == FALSE) {
1801        /* Init Xv */
1802        xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
1803                       "Initializing Xv\n");
1804        RADEONInitVideo(pScreen);
1805    }
1806
1807    if (info->r600_shadow_fb == TRUE) {
1808        if (!shadowSetup(pScreen)) {
1809	    xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1810		       "Shadowfb initialization failed\n");
1811            return FALSE;
1812        }
1813    }
1814    pScrn->pScreen = pScreen;
1815
1816#if GET_ABI_MAJOR(ABI_VIDEODRV_VERSION) >= 10
1817    if (serverGeneration == 1 && bgNoneRoot && info->accelOn) {
1818	info->CreateWindow = pScreen->CreateWindow;
1819	pScreen->CreateWindow = RADEONCreateWindow_oneshot;
1820    }
1821#endif
1822
1823    /* Provide SaveScreen & wrap BlockHandler and CloseScreen */
1824    /* Wrap CloseScreen */
1825    info->CloseScreen    = pScreen->CloseScreen;
1826    pScreen->CloseScreen = RADEONCloseScreen_KMS;
1827    pScreen->SaveScreen  = RADEONSaveScreen_KMS;
1828    info->BlockHandler = pScreen->BlockHandler;
1829    pScreen->BlockHandler = RADEONBlockHandler_oneshot;
1830
1831    if (!AddCallback(&FlushCallback, radeon_flush_callback, pScrn))
1832        return FALSE;
1833
1834    info->CreateScreenResources = pScreen->CreateScreenResources;
1835    pScreen->CreateScreenResources = RADEONCreateScreenResources_KMS;
1836
1837#ifdef RADEON_PIXMAP_SHARING
1838    pScreen->StartPixmapTracking = PixmapStartDirtyTracking;
1839    pScreen->StopPixmapTracking = PixmapStopDirtyTracking;
1840#endif
1841
1842   if (!xf86CrtcScreenInit (pScreen))
1843       return FALSE;
1844
1845   /* Wrap pointer motion to flip touch screen around */
1846//    info->PointerMoved = pScrn->PointerMoved;
1847//    pScrn->PointerMoved = RADEONPointerMoved;
1848
1849    if (!drmmode_setup_colormap(pScreen, pScrn))
1850	return FALSE;
1851
1852   /* Note unused options */
1853    if (serverGeneration == 1)
1854	xf86ShowUnusedOptions(pScrn->scrnIndex, pScrn->options);
1855
1856    drmmode_init(pScrn, &info->drmmode);
1857
1858    xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
1859		   "RADEONScreenInit finished\n");
1860
1861    info->accel_state->XInited3D = FALSE;
1862    info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN;
1863
1864    return TRUE;
1865}
1866
1867Bool RADEONEnterVT_KMS(VT_FUNC_ARGS_DECL)
1868{
1869    SCRN_INFO_PTR(arg);
1870    RADEONInfoPtr  info  = RADEONPTR(pScrn);
1871
1872    xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
1873		   "RADEONEnterVT_KMS\n");
1874
1875    radeon_set_drm_master(pScrn);
1876
1877    info->accel_state->XInited3D = FALSE;
1878    info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN;
1879
1880    pScrn->vtSema = TRUE;
1881
1882    if (!drmmode_set_desired_modes(pScrn, &info->drmmode, TRUE))
1883	return FALSE;
1884
1885    return TRUE;
1886}
1887
1888
1889void RADEONLeaveVT_KMS(VT_FUNC_ARGS_DECL)
1890{
1891    SCRN_INFO_PTR(arg);
1892    RADEONInfoPtr  info  = RADEONPTR(pScrn);
1893
1894    xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
1895		   "RADEONLeaveVT_KMS\n");
1896
1897    radeon_drop_drm_master(pScrn);
1898
1899    xf86RotateFreeShadow(pScrn);
1900    drmmode_scanout_free(pScrn);
1901
1902    xf86_hide_cursors (pScrn);
1903    info->accel_state->XInited3D = FALSE;
1904    info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN;
1905
1906    xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
1907		   "Ok, leaving now...\n");
1908}
1909
1910
1911Bool RADEONSwitchMode_KMS(SWITCH_MODE_ARGS_DECL)
1912{
1913    SCRN_INFO_PTR(arg);
1914    Bool ret;
1915    ret = xf86SetSingleMode (pScrn, mode, RR_Rotate_0);
1916    return ret;
1917
1918}
1919
1920void RADEONAdjustFrame_KMS(ADJUST_FRAME_ARGS_DECL)
1921{
1922    SCRN_INFO_PTR(arg);
1923    RADEONInfoPtr  info        = RADEONPTR(pScrn);
1924    drmmode_adjust_frame(pScrn, &info->drmmode, x, y);
1925    return;
1926}
1927
1928static Bool radeon_setup_kernel_mem(ScreenPtr pScreen)
1929{
1930    ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen);
1931    RADEONInfoPtr info = RADEONPTR(pScrn);
1932    xf86CrtcConfigPtr   xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
1933    int cpp = info->pixel_bytes;
1934    uint32_t screen_size;
1935    int pitch, base_align;
1936    uint32_t tiling_flags = 0;
1937    struct radeon_surface surface;
1938
1939    if (info->accel_state->exa != NULL) {
1940	xf86DrvMsg(pScreen->myNum, X_ERROR, "Memory map already initialized\n");
1941	return FALSE;
1942    }
1943    if (!info->use_glamor && info->r600_shadow_fb == FALSE) {
1944        info->accel_state->exa = exaDriverAlloc();
1945        if (info->accel_state->exa == NULL) {
1946	    xf86DrvMsg(pScreen->myNum, X_ERROR, "exaDriverAlloc failed\n");
1947	    return FALSE;
1948	}
1949    }
1950
1951    if (info->allowColorTiling && !info->shadow_primary) {
1952	if (info->ChipFamily >= CHIP_FAMILY_R600) {
1953		if (info->allowColorTiling2D) {
1954			tiling_flags |= RADEON_TILING_MACRO;
1955		} else {
1956			tiling_flags |= RADEON_TILING_MICRO;
1957		}
1958	} else
1959	    tiling_flags |= RADEON_TILING_MACRO;
1960    }
1961    pitch = RADEON_ALIGN(pScrn->virtualX, drmmode_get_pitch_align(pScrn, cpp, tiling_flags)) * cpp;
1962    screen_size = RADEON_ALIGN(pScrn->virtualY, drmmode_get_height_align(pScrn, tiling_flags)) * pitch;
1963    base_align = drmmode_get_base_align(pScrn, cpp, tiling_flags);
1964	if (info->ChipFamily >= CHIP_FAMILY_R600) {
1965		if(!info->surf_man) {
1966			xf86DrvMsg(pScreen->myNum, X_ERROR,
1967				   "failed to initialise surface manager\n");
1968			return FALSE;
1969		}
1970		memset(&surface, 0, sizeof(struct radeon_surface));
1971		surface.npix_x = pScrn->virtualX;
1972		surface.npix_y = pScrn->virtualY;
1973		surface.npix_z = 1;
1974		surface.blk_w = 1;
1975		surface.blk_h = 1;
1976		surface.blk_d = 1;
1977		surface.array_size = 1;
1978		surface.last_level = 0;
1979		surface.bpe = cpp;
1980		surface.nsamples = 1;
1981		surface.flags = RADEON_SURF_SCANOUT;
1982		/* we are requiring a recent enough libdrm version */
1983		surface.flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
1984		surface.flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
1985		surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
1986		if (tiling_flags & RADEON_TILING_MICRO) {
1987			surface.flags = RADEON_SURF_CLR(surface.flags, MODE);
1988			surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
1989		}
1990		if (tiling_flags & RADEON_TILING_MACRO) {
1991			surface.flags = RADEON_SURF_CLR(surface.flags, MODE);
1992			surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
1993		}
1994		if (radeon_surface_best(info->surf_man, &surface)) {
1995			xf86DrvMsg(pScreen->myNum, X_ERROR,
1996				   "radeon_surface_best failed\n");
1997			return FALSE;
1998		}
1999		if (radeon_surface_init(info->surf_man, &surface)) {
2000			xf86DrvMsg(pScreen->myNum, X_ERROR,
2001				   "radeon_surface_init failed\n");
2002			return FALSE;
2003		}
2004		pitch = surface.level[0].pitch_bytes;
2005		screen_size = surface.bo_size;
2006		base_align = surface.bo_alignment;
2007		tiling_flags = 0;
2008		switch (surface.level[0].mode) {
2009		case RADEON_SURF_MODE_2D:
2010			tiling_flags |= RADEON_TILING_MACRO;
2011			tiling_flags |= surface.bankw << RADEON_TILING_EG_BANKW_SHIFT;
2012			tiling_flags |= surface.bankh << RADEON_TILING_EG_BANKH_SHIFT;
2013			tiling_flags |= surface.mtilea << RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT;
2014			if (surface.tile_split)
2015				tiling_flags |= eg_tile_split(surface.tile_split)
2016						<< RADEON_TILING_EG_TILE_SPLIT_SHIFT;
2017			break;
2018		case RADEON_SURF_MODE_1D:
2019			tiling_flags |= RADEON_TILING_MICRO;
2020			break;
2021		default:
2022			break;
2023		}
2024		info->front_surface = surface;
2025	}
2026    {
2027	int cursor_size;
2028	int c;
2029
2030	cursor_size = info->cursor_w * info->cursor_h * 4;
2031	cursor_size = RADEON_ALIGN(cursor_size, RADEON_GPU_PAGE_SIZE);
2032	for (c = 0; c < xf86_config->num_crtc; c++) {
2033	    /* cursor objects */
2034            if (info->cursor_bo[c] == NULL) {
2035                info->cursor_bo[c] = radeon_bo_open(info->bufmgr, 0,
2036                                                    cursor_size, 0,
2037                                                    RADEON_GEM_DOMAIN_VRAM, 0);
2038                if (!info->cursor_bo[c]) {
2039                    ErrorF("Failed to allocate cursor buffer memory\n");
2040                    return FALSE;
2041                }
2042
2043                if (radeon_bo_map(info->cursor_bo[c], 1)) {
2044                    ErrorF("Failed to map cursor buffer memory\n");
2045                }
2046
2047                drmmode_set_cursor(pScrn, &info->drmmode, c, info->cursor_bo[c]);
2048            }
2049        }
2050    }
2051
2052    screen_size = RADEON_ALIGN(screen_size, RADEON_GPU_PAGE_SIZE);
2053
2054    if (info->front_bo == NULL) {
2055        info->front_bo = radeon_bo_open(info->bufmgr, 0, screen_size,
2056                                        base_align,
2057                                        info->shadow_primary ?
2058                                        RADEON_GEM_DOMAIN_GTT :
2059                                        RADEON_GEM_DOMAIN_VRAM,
2060                                        tiling_flags ? RADEON_GEM_NO_CPU_ACCESS : 0);
2061        if (info->r600_shadow_fb == TRUE) {
2062            if (radeon_bo_map(info->front_bo, 1)) {
2063                ErrorF("Failed to map cursor buffer memory\n");
2064            }
2065        }
2066#if X_BYTE_ORDER == X_BIG_ENDIAN
2067	switch (cpp) {
2068	case 4:
2069	    tiling_flags |= RADEON_TILING_SWAP_32BIT;
2070	    break;
2071	case 2:
2072	    tiling_flags |= RADEON_TILING_SWAP_16BIT;
2073	    break;
2074	}
2075	if (info->ChipFamily < CHIP_FAMILY_R600 &&
2076	    info->r600_shadow_fb && tiling_flags)
2077	    tiling_flags |= RADEON_TILING_SURFACE;
2078#endif
2079	if (tiling_flags)
2080            radeon_bo_set_tiling(info->front_bo, tiling_flags, pitch);
2081    }
2082
2083    pScrn->displayWidth = pitch / cpp;
2084
2085    xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Front buffer size: %dK\n", info->front_bo->size/1024);
2086    radeon_kms_update_vram_limit(pScrn, screen_size);
2087    return TRUE;
2088}
2089
2090void radeon_kms_update_vram_limit(ScrnInfoPtr pScrn, uint32_t new_fb_size)
2091{
2092    xf86CrtcConfigPtr   xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
2093    RADEONInfoPtr info = RADEONPTR(pScrn);
2094    uint64_t remain_size_bytes;
2095    int c;
2096
2097    for (c = 0; c < xf86_config->num_crtc; c++) {
2098	if (info->cursor_bo[c] != NULL) {
2099	    new_fb_size += (64 * 4 * 64);
2100	}
2101    }
2102
2103    remain_size_bytes = info->vram_size - new_fb_size;
2104    remain_size_bytes = (remain_size_bytes / 10) * 9;
2105    if (remain_size_bytes > 0xffffffff)
2106	remain_size_bytes = 0xffffffff;
2107    radeon_cs_set_limit(info->cs, RADEON_GEM_DOMAIN_VRAM,
2108			(uint32_t)remain_size_bytes);
2109
2110    xf86DrvMsg(pScrn->scrnIndex, X_INFO, "VRAM usage limit set to %uK\n",
2111	       (uint32_t)remain_size_bytes / 1024);
2112}
2113
2114/* Used to disallow modes that are not supported by the hardware */
2115ModeStatus RADEONValidMode(SCRN_ARG_TYPE arg, DisplayModePtr mode,
2116                           Bool verbose, int flag)
2117{
2118    SCRN_INFO_PTR(arg);
2119    RADEONInfoPtr info = RADEONPTR(pScrn);
2120    RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
2121
2122    /*
2123     * RN50 has effective maximum mode bandwidth of about 300MiB/s.
2124     * XXX should really do this for all chips by properly computing
2125     * memory bandwidth and an overhead factor.
2126    */
2127    if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2) {
2128       if (xf86ModeBandwidth(mode, pScrn->bitsPerPixel) > 300)
2129          return MODE_BANDWIDTH;
2130    }
2131    /* There are problems with double scan mode at high clocks
2132     * They're likely related PLL and display buffer settings.
2133     * Disable these modes for now.
2134     */
2135    if (mode->Flags & V_DBLSCAN) {
2136       if ((mode->CrtcHDisplay >= 1024) || (mode->CrtcVDisplay >= 768))
2137           return MODE_CLOCK_RANGE;
2138   }
2139    return MODE_OK;
2140}
2141