s3v.h revision 1d54945d
11d54945dSmrg/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/s3virge/s3v.h,v 1.31 2003/02/04 02:20:49 dawes Exp $ */ 21d54945dSmrg 31d54945dSmrg/* 41d54945dSmrgCopyright (C) 1994-1999 The XFree86 Project, Inc. All Rights Reserved. 51d54945dSmrg 61d54945dSmrgPermission is hereby granted, free of charge, to any person obtaining a copy of 71d54945dSmrgthis software and associated documentation files (the "Software"), to deal in 81d54945dSmrgthe Software without restriction, including without limitation the rights to 91d54945dSmrguse, copy, modify, merge, publish, distribute, sublicense, and/or sell copies 101d54945dSmrgof the Software, and to permit persons to whom the Software is furnished to do 111d54945dSmrgso, subject to the following conditions: 121d54945dSmrg 131d54945dSmrgThe above copyright notice and this permission notice shall be included in all 141d54945dSmrgcopies or substantial portions of the Software. 151d54945dSmrg 161d54945dSmrgTHE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 171d54945dSmrgIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FIT- 181d54945dSmrgNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 191d54945dSmrgXFREE86 PROJECT BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 201d54945dSmrgAN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 211d54945dSmrgWITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 221d54945dSmrg 231d54945dSmrgExcept as contained in this notice, the name of the XFree86 Project shall not 241d54945dSmrgbe used in advertising or otherwise to promote the sale, use or other dealings 251d54945dSmrgin this Software without prior written authorization from the XFree86 Project. 261d54945dSmrg*/ 271d54945dSmrg 281d54945dSmrg#ifndef _S3V_H 291d54945dSmrg#define _S3V_H 301d54945dSmrg 311d54945dSmrg#include <string.h> 321d54945dSmrg 331d54945dSmrg/* All drivers should typically include these */ 341d54945dSmrg#include "xf86.h" 351d54945dSmrg#include "xf86_OSproc.h" 361d54945dSmrg 371d54945dSmrg/* All drivers need this */ 381d54945dSmrg 391d54945dSmrg/* Everything using inb/outb, etc needs "compiler.h" */ 401d54945dSmrg#include "compiler.h" 411d54945dSmrg 421d54945dSmrg/* Drivers for PCI hardware need this */ 431d54945dSmrg#include "xf86PciInfo.h" 441d54945dSmrg 451d54945dSmrg/* Drivers that need to access the PCI config space directly need this */ 461d54945dSmrg#include "xf86Pci.h" 471d54945dSmrg 481d54945dSmrg#include "xf86Cursor.h" 491d54945dSmrg 501d54945dSmrg#include "vgaHW.h" 511d54945dSmrg 521d54945dSmrg#include "s3v_macros.h" 531d54945dSmrg 541d54945dSmrg/* All drivers initialising the SW cursor need this */ 551d54945dSmrg#include "mipointer.h" 561d54945dSmrg 571d54945dSmrg/* All drivers using the mi colormap manipulation need this */ 581d54945dSmrg#include "micmap.h" 591d54945dSmrg 601d54945dSmrg/* fb support */ 611d54945dSmrg 621d54945dSmrg#include "fb.h" 631d54945dSmrg 641d54945dSmrg/* Drivers using the XAA interface ... */ 651d54945dSmrg#include "xaa.h" 661d54945dSmrg#include "xaalocal.h" 671d54945dSmrg#include "xf86cmap.h" 681d54945dSmrg#include "xf86i2c.h" 691d54945dSmrg 701d54945dSmrg#include "vbe.h" 711d54945dSmrg 721d54945dSmrg#include "xf86xv.h" 731d54945dSmrg#include <X11/extensions/Xv.h> 741d54945dSmrg#include "fourcc.h" 751d54945dSmrg 761d54945dSmrg#ifndef _S3V_VGAHWMMIO_H 771d54945dSmrg#define _S3V_VGAHWMMIO_H 781d54945dSmrg 791d54945dSmrg#define VGAIN8(addr) MMIO_IN8(ps3v->MapBase,(S3V_MMIO_REGSIZE + (addr))) 801d54945dSmrg#define VGAIN16(addr) MMIO_IN16(ps3v->MapBase,(S3V_MMIO_REGSIZE + (addr))) 811d54945dSmrg#define VGAIN(addr) MMIO_IN32(ps3v->MapBase,(S3V_MMIO_REGSIZE + (addr))) 821d54945dSmrg#define VGAOUT8(addr,val) MMIO_OUT8(ps3v->MapBase,(S3V_MMIO_REGSIZE + (addr)),\ 831d54945dSmrg val) 841d54945dSmrg#define VGAOUT16(addr,val) MMIO_OUT16(ps3v->MapBase,\ 851d54945dSmrg (S3V_MMIO_REGSIZE + (addr)), val) 861d54945dSmrg#define VGAOUT(addr, val) MMIO_OUT32(ps3v->MapBase,\ 871d54945dSmrg (S3V_MMIO_REGSIZE + (addr)), val) 881d54945dSmrg 891d54945dSmrg#define INREG(addr) MMIO_IN32(ps3v->MapBase, addr) 901d54945dSmrg#define OUTREG(addr, val) MMIO_OUT32(ps3v->MapBase, addr, val) 911d54945dSmrg#define NEW_INREG(addr) MMIO_IN32(s3vMmioMem, addr) 921d54945dSmrg#define NEW_OUTREG(addr, val) MMIO_OUT32(s3vMmioMem, addr, val) 931d54945dSmrg 941d54945dSmrg#endif /*_S3V_VGAHWMMIO_H*/ 951d54945dSmrg 961d54945dSmrg/******************* s3v_i2c ****************************/ 971d54945dSmrg 981d54945dSmrgBool S3V_I2CInit(ScrnInfoPtr pScrn); 991d54945dSmrg 1001d54945dSmrg/******************* s3v_accel ****************************/ 1011d54945dSmrg 1021d54945dSmrgvoid S3VGEReset(ScrnInfoPtr pScrn, int from_timeout, int line, char *file); 1031d54945dSmrg 1041d54945dSmrg 1051d54945dSmrg/*********************************************/ 1061d54945dSmrg/* locals */ 1071d54945dSmrg 1081d54945dSmrg/* Some S3 ViRGE structs */ 1091d54945dSmrg#include "newmmio.h" 1101d54945dSmrg 1111d54945dSmrg/* More ViRGE defines */ 1121d54945dSmrg#include "regs3v.h" 1131d54945dSmrg 1141d54945dSmrg/*********************************************/ 1151d54945dSmrg 1161d54945dSmrg 1171d54945dSmrg 1181d54945dSmrg/* Driver data structure; this should contain all needed info for a mode */ 1191d54945dSmrg/* used to be in s3v_driver.h for pre 4.0 */ 1201d54945dSmrgtypedef struct { 1211d54945dSmrg unsigned char SR08, SR0A, SR0F; 1221d54945dSmrg unsigned char SR10, SR11, SR12, SR13, SR15, SR18; /* SR9-SR1C, ext seq. */ 1231d54945dSmrg unsigned char SR29; 1241d54945dSmrg unsigned char SR54, SR55, SR56, SR57; 1251d54945dSmrg unsigned char Clock; 1261d54945dSmrg unsigned char s3DacRegs[0x101]; 1271d54945dSmrg unsigned char CR31, CR33, CR34, CR36, CR3A, CR3B, CR3C; 1281d54945dSmrg unsigned char CR40, CR41, CR42, CR43, CR45; 1291d54945dSmrg unsigned char CR51, CR53, CR54, CR55, CR58, CR5D, CR5E; 1301d54945dSmrg unsigned char CR63, CR65, CR66, CR67, CR68, CR69, CR6D; /* Video attrib. */ 1311d54945dSmrg unsigned char CR7B, CR7D; 1321d54945dSmrg unsigned char CR85, CR86, CR87; 1331d54945dSmrg unsigned char CR90, CR91, CR92, CR93; 1341d54945dSmrg unsigned char ColorStack[8]; /* S3 hw cursor color stack CR4A/CR4B */ 1351d54945dSmrg unsigned int STREAMS[22]; /* Streams regs */ 1361d54945dSmrg unsigned int MMPR0, MMPR1, MMPR2, MMPR3; /* MIU regs */ 1371d54945dSmrg} S3VRegRec, *S3VRegPtr; 1381d54945dSmrg 1391d54945dSmrg 1401d54945dSmrg/*********************************/ 1411d54945dSmrg/* S3VPortPrivRec */ 1421d54945dSmrg/*********************************/ 1431d54945dSmrg 1441d54945dSmrgtypedef struct { 1451d54945dSmrg unsigned char brightness; 1461d54945dSmrg unsigned char contrast; 1471d54945dSmrg FBAreaPtr area; 1481d54945dSmrg RegionRec clip; 1491d54945dSmrg CARD32 colorKey; 1501d54945dSmrg CARD32 videoStatus; 1511d54945dSmrg Time offTime; 1521d54945dSmrg Time freeTime; 1531d54945dSmrg int lastPort; 1541d54945dSmrg} S3VPortPrivRec, *S3VPortPrivPtr; 1551d54945dSmrg 1561d54945dSmrg 1571d54945dSmrg/*************************/ 1581d54945dSmrg/* S3VRec */ 1591d54945dSmrg/*************************/ 1601d54945dSmrg 1611d54945dSmrgtypedef struct tagS3VRec { 1621d54945dSmrg /* accel additions */ 1631d54945dSmrg CARD32 AccelFlags; 1641d54945dSmrg CARD32 AccelCmd; 1651d54945dSmrg CARD32 SrcBaseY, DestBaseY; 1661d54945dSmrg CARD32 Stride; 1671d54945dSmrg CARD32 CommonCmd; 1681d54945dSmrg CARD32 FullPlaneMask; 1691d54945dSmrg GCPtr CurrentGC; 1701d54945dSmrg /* fb support */ 1711d54945dSmrg DrawablePtr CurrentDrawable; 1721d54945dSmrg /* end accel stuff */ 1731d54945dSmrg /* ViRGE specifics -start- */ 1741d54945dSmrg /* Xv support */ 1751d54945dSmrg XF86VideoAdaptorPtr adaptor; 1761d54945dSmrg S3VPortPrivPtr portPrivate; 1771d54945dSmrg 1781d54945dSmrg /* S3V console saved mode registers */ 1791d54945dSmrg S3VRegRec SavedReg; 1801d54945dSmrg /* XServer video state mode registers */ 1811d54945dSmrg S3VRegRec ModeReg; 1821d54945dSmrg /* HW Cursor info */ 1831d54945dSmrg xf86CursorInfoPtr CursorInfoRec; 1841d54945dSmrg /* Flag indicating ModeReg has been */ 1851d54945dSmrg /* duped from console state. */ 1861d54945dSmrg Bool ModeStructInit; 1871d54945dSmrg /* Is STREAMS processor needed for */ 1881d54945dSmrg /* this mode? */ 1891d54945dSmrg Bool NeedSTREAMS; 1901d54945dSmrg /* Is STREAMS running now ? */ 1911d54945dSmrg Bool STREAMSRunning; 1921d54945dSmrg /* Compatibility variables */ 1931d54945dSmrg int vgaCRIndex, vgaCRReg; 1941d54945dSmrg int Width, Bpp,Bpl, ScissB; 1951d54945dSmrg /* XAA */ 1961d54945dSmrg unsigned PlaneMask; 1971d54945dSmrg int bltbug_width1, bltbug_width2; 1981d54945dSmrg /* In units as noted, set in PreInit */ 1991d54945dSmrg int videoRambytes; 2001d54945dSmrg int videoRamKbytes; 2011d54945dSmrg /* In Kbytes, set in PreInit */ 2021d54945dSmrg int MemOffScreen; 2031d54945dSmrg /* Holds the virtual memory address */ 2041d54945dSmrg /* returned when the MMIO registers */ 2051d54945dSmrg /* are mapped with xf86MapPciMem */ 2061d54945dSmrg unsigned char * MapBase; 2071d54945dSmrg unsigned char * MapBaseDense; 2081d54945dSmrg 2091d54945dSmrg /* Same as MapBase, except framebuffer*/ 2101d54945dSmrg unsigned char * FBBase; 2111d54945dSmrg /* Current visual FB starting location */ 2121d54945dSmrg unsigned char * FBStart; 2131d54945dSmrg /* Cursor storage location */ 2141d54945dSmrg CARD32 FBCursorOffset; 2151d54945dSmrg /* Saved CR53 value */ 2161d54945dSmrg unsigned char EnableMmioCR53; 2171d54945dSmrg /* Extended reg unlock storage */ 2181d54945dSmrg unsigned char CR38,CR39,CR40; 2191d54945dSmrg /* Flag indicating if vgaHWMapMem was */ 2201d54945dSmrg /* used successfully for this screen */ 2211d54945dSmrg Bool PrimaryVidMapped; 2221d54945dSmrg int HorizScaleFactor; 2231d54945dSmrg Bool bankedMono; 2241d54945dSmrg /* Memory Clock */ 2251d54945dSmrg int MCLK; 2261d54945dSmrg /* input reference Clock */ 2271d54945dSmrg int REFCLK; 2281d54945dSmrg /* MX LCD clock */ 2291d54945dSmrg int LCDClk; 2301d54945dSmrg /* MX reference clock scale */ 2311d54945dSmrg double refclk_fact; 2321d54945dSmrg /* Limit the number of errors */ 2331d54945dSmrg /* printed using a counter */ 2341d54945dSmrg int GEResetCnt; 2351d54945dSmrg /* Accel WaitFifo function */ 2361d54945dSmrg void (*pWaitFifo)(struct tagS3VRec *, int); 2371d54945dSmrg /* Accel WaitCmd function */ 2381d54945dSmrg void (*pWaitCmd)(struct tagS3VRec *); 2391d54945dSmrg 2401d54945dSmrg /*************************/ 2411d54945dSmrg /* ViRGE options -start- */ 2421d54945dSmrg /*************************/ 2431d54945dSmrg OptionInfoPtr Options; 2441d54945dSmrg /* Enable PCI burst mode for reads? */ 2451d54945dSmrg Bool pci_burst; 2461d54945dSmrg /* Diasable PCI retries */ 2471d54945dSmrg Bool NoPCIRetry; 2481d54945dSmrg /* Adjust fifo for acceleration? */ 2491d54945dSmrg Bool fifo_conservative; 2501d54945dSmrg Bool fifo_moderate; 2511d54945dSmrg Bool fifo_aggressive; 2521d54945dSmrg /* Set memory options */ 2531d54945dSmrg Bool slow_edodram; 2541d54945dSmrg Bool slow_dram; 2551d54945dSmrg Bool fast_dram; 2561d54945dSmrg Bool fpm_vram; 2571d54945dSmrg /* Disable Acceleration */ 2581d54945dSmrg Bool NoAccel; 2591d54945dSmrg /* Adjust memory ras precharge */ 2601d54945dSmrg /* timing */ 2611d54945dSmrg Bool ShowCache; 2621d54945dSmrg Bool early_ras_precharge; 2631d54945dSmrg Bool late_ras_precharge; 2641d54945dSmrg /* MX LCD centering */ 2651d54945dSmrg Bool lcd_center; 2661d54945dSmrg /* hardware cursor enabled */ 2671d54945dSmrg Bool hwcursor; 2681d54945dSmrg Bool UseFB; 2691d54945dSmrg Bool mx_cr3a_fix; 2701d54945dSmrg Bool XVideo; 2711d54945dSmrg /* ViRGE options -end- */ 2721d54945dSmrg /***********************/ 2731d54945dSmrg /* ViRGE specifics -end- */ 2741d54945dSmrg 2751d54945dSmrg /* Used by ViRGE driver, but generic */ 2761d54945dSmrg 2771d54945dSmrg /* Pointer used to save wrapped */ 2781d54945dSmrg /* CloseScreen function. */ 2791d54945dSmrg CloseScreenProcPtr CloseScreen; 2801d54945dSmrg /* XAA info Rec */ 2811d54945dSmrg XAAInfoRecPtr AccelInfoRec; 2821d54945dSmrg /* PCI info vars. */ 2831d54945dSmrg pciVideoPtr PciInfo; 2841d54945dSmrg PCITAG PciTag; 2851d54945dSmrg /* Chip info, set using PCI */ 2861d54945dSmrg /* above. */ 2871d54945dSmrg int Chipset; 2881d54945dSmrg int ChipRev; 2891d54945dSmrg /* DGA2 */ 2901d54945dSmrg DGAModePtr DGAModes; 2911d54945dSmrg int numDGAModes; 2921d54945dSmrg Bool DGAactive; 2931d54945dSmrg int DGAViewportStatus; 2941d54945dSmrg I2CBusPtr I2C; 2951d54945dSmrg vbeInfoPtr pVbe; 2961d54945dSmrg Bool shadowFB; 2971d54945dSmrg int rotate; 2981d54945dSmrg unsigned char * ShadowPtr; 2991d54945dSmrg int ShadowPitch; 3001d54945dSmrg void (*PointerMoved)(int index, int x, int y); 3011d54945dSmrg 3021d54945dSmrg /* Used by ViRGE driver, but generic -end- */ 3031d54945dSmrg 3041d54945dSmrg 3051d54945dSmrg} S3VRec, *S3VPtr; 3061d54945dSmrg 3071d54945dSmrg 3081d54945dSmrg#define S3VPTR(p) ((S3VPtr)((p)->driverPrivate)) 3091d54945dSmrg 3101d54945dSmrg 3111d54945dSmrg/* #define S3V_DEBUG */ 3121d54945dSmrg 3131d54945dSmrg#ifdef S3V_DEBUG 3141d54945dSmrg#define PVERB5(arg) ErrorF(arg) 3151d54945dSmrg#define VERBLEV 1 3161d54945dSmrg#else 3171d54945dSmrg#define PVERB5(arg) xf86ErrorFVerb(5, arg) 3181d54945dSmrg#define VERBLEV 5 3191d54945dSmrg#endif 3201d54945dSmrg 3211d54945dSmrg 3221d54945dSmrg/******************* regs3v *******************************/ 3231d54945dSmrg 3241d54945dSmrg/* cep kjb */ 3251d54945dSmrg#define VertDebug 1 3261d54945dSmrg 3271d54945dSmrg/* #ifndef MetroLink */ 3281d54945dSmrg#if !defined (MetroLink) && !defined (VertDebug) 3291d54945dSmrg#define VerticalRetraceWait() do { \ 3301d54945dSmrg VGAOUT8(vgaCRIndex, 0x17); \ 3311d54945dSmrg if ( VGAIN8(vgaCRReg) & 0x80 ) { \ 3321d54945dSmrg while ((VGAIN8(vgaIOBase + 0x0A) & 0x08) == 0x00) ; \ 3331d54945dSmrg while ((VGAIN8(vgaIOBase + 0x0A) & 0x08) == 0x08) ; \ 3341d54945dSmrg while ((VGAIN8(vgaIOBase + 0x0A) & 0x08) == 0x00) ; \ 3351d54945dSmrg }\ 3361d54945dSmrg} while (0) 3371d54945dSmrg 3381d54945dSmrg#else 3391d54945dSmrg#define SPIN_LIMIT 1000000 3401d54945dSmrg#define VerticalRetraceWait() do { \ 3411d54945dSmrg VGAOUT8(vgaCRIndex, 0x17); \ 3421d54945dSmrg if ( VGAIN8(vgaCRReg) & 0x80 ) { \ 3431d54945dSmrg volatile unsigned long _spin_me; \ 3441d54945dSmrg for (_spin_me = 0; \ 3451d54945dSmrg ((VGAIN8(vgaIOBase + 0x0A) & 0x08) == 0x00) && _spin_me <= SPIN_LIMIT; \ 3461d54945dSmrg _spin_me++) ; \ 3471d54945dSmrg if (_spin_me > SPIN_LIMIT) \ 3481d54945dSmrg ErrorF("s3v: warning: VerticalRetraceWait timed out(1:3).\n"); \ 3491d54945dSmrg for (_spin_me = 0; \ 3501d54945dSmrg ((VGAIN8(vgaIOBase + 0x0A) & 0x08) == 0x08) && _spin_me <= SPIN_LIMIT; \ 3511d54945dSmrg _spin_me++) ; \ 3521d54945dSmrg if (_spin_me > SPIN_LIMIT) \ 3531d54945dSmrg ErrorF("s3v: warning: VerticalRetraceWait timed out(2:3).\n"); \ 3541d54945dSmrg for (_spin_me = 0; \ 3551d54945dSmrg ((VGAIN8(vgaIOBase + 0x0A) & 0x08) == 0x00) && _spin_me <= SPIN_LIMIT; \ 3561d54945dSmrg _spin_me++) ; \ 3571d54945dSmrg if (_spin_me > SPIN_LIMIT) \ 3581d54945dSmrg ErrorF("s3v: warning: VerticalRetraceWait timed out(3:3).\n"); \ 3591d54945dSmrg } \ 3601d54945dSmrg} while (0) 3611d54945dSmrg#endif 3621d54945dSmrg 3631d54945dSmrg 3641d54945dSmrg/*********************************************************/ 3651d54945dSmrg 3661d54945dSmrg 3671d54945dSmrg/* Various defines which are used to pass flags between the Setup and 3681d54945dSmrg * Subsequent functions. 3691d54945dSmrg */ 3701d54945dSmrg 3711d54945dSmrg#define NO_MONO_FILL 0x00 3721d54945dSmrg#define NEED_MONO_FILL 0x01 3731d54945dSmrg#define MONO_TRANSPARENCY 0x02 3741d54945dSmrg 3751d54945dSmrg/* prototypes */ 3761d54945dSmrg/* s3v_dac.c */ 3771d54945dSmrgextern void S3VCommonCalcClock(ScrnInfoPtr pScrn, DisplayModePtr mode, 3781d54945dSmrg long freq, int min_m, int min_n1, int max_n1, 3791d54945dSmrg int min_n2, int max_n2, long freq_min, long freq_max, 3801d54945dSmrg unsigned char * mdiv, unsigned char * ndiv); 3811d54945dSmrg 3821d54945dSmrg/* s3v_accel.c */ 3831d54945dSmrgextern Bool S3VAccelInit(ScreenPtr pScreen); 3841d54945dSmrgextern Bool S3VAccelInit32(ScreenPtr pScreen); 3851d54945dSmrgvoid S3VAccelSync(ScrnInfoPtr); 3861d54945dSmrgvoid S3VWaitFifoGX2(S3VPtr ps3v, int slots ); 3871d54945dSmrgvoid S3VWaitFifoMain(S3VPtr ps3v, int slots ); 3881d54945dSmrgvoid S3VWaitCmdGX2(S3VPtr ps3v); 3891d54945dSmrgvoid S3VWaitDummy(S3VPtr ps3v); 3901d54945dSmrg 3911d54945dSmrg/* s3v_hwcurs.c */ 3921d54945dSmrgextern Bool S3VHWCursorInit(ScreenPtr pScreen); 3931d54945dSmrg 3941d54945dSmrg/* s3v_driver.c */ 3951d54945dSmrgvoid S3VAdjustFrame(int scrnIndex, int x, int y, int flags); 3961d54945dSmrgBool S3VSwitchMode(int scrnIndex, DisplayModePtr mode, int flags); 3971d54945dSmrg 3981d54945dSmrg/* s3v_dga.c */ 3991d54945dSmrgBool S3VDGAInit(ScreenPtr pScreen); 4001d54945dSmrg 4011d54945dSmrg/* in s3v_shadow.c */ 4021d54945dSmrgvoid s3vPointerMoved(int index, int x, int y); 4031d54945dSmrgvoid s3vRefreshArea(ScrnInfoPtr pScrn, int num, BoxPtr pbox); 4041d54945dSmrgvoid s3vRefreshArea8(ScrnInfoPtr pScrn, int num, BoxPtr pbox); 4051d54945dSmrgvoid s3vRefreshArea16(ScrnInfoPtr pScrn, int num, BoxPtr pbox); 4061d54945dSmrgvoid s3vRefreshArea24(ScrnInfoPtr pScrn, int num, BoxPtr pbox); 4071d54945dSmrgvoid s3vRefreshArea32(ScrnInfoPtr pScrn, int num, BoxPtr pbox); 4081d54945dSmrg 4091d54945dSmrg/* s3v_xv.c X Video Extension support */ 4101d54945dSmrgvoid S3VInitVideo(ScreenPtr pScreen); 4111d54945dSmrgint S3VQueryXvCapable(ScrnInfoPtr); 4121d54945dSmrg 4131d54945dSmrg#endif /*_S3V_H*/ 4141d54945dSmrg 4151d54945dSmrg 4161d54945dSmrg/*EOF*/ 4171d54945dSmrg 4181d54945dSmrg 419