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    Searched defs:HWRITE4 (Results 1 - 7 of 7) sorted by relevancy

  /src/sys/arch/arm/xscale/
pxa2x0_ohci.c 54 #define HWRITE4(sc,r,v) bus_space_write_4((sc)->sc.iot, (sc)->sc.ioh, (r), (v))
247 HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) | USBHC_HR_FHR);
252 HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) & ~(USBHC_HR_FHR));
256 HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) | USBHC_HR_FSBIR);
263 HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) & ~(USBHC_HR_SSE));
265 HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) &
267 HWRITE4(sc, USBHC_HIE, USBHC_HIE_RWIE | USBHC_HIE_UPRIE);
279 HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) | USBHC_HR_FHR);
284 HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) & ~(USBHC_HR_FHR));
  /src/sys/dev/acpi/
qcomipcc.c 39 #define HWRITE4(sc, reg, val) \
158 HWRITE4(sc, IPCC_RECV_SIGNAL_CLEAR, reg);
217 HWRITE4(sc, IPCC_RECV_SIGNAL_ENABLE,
228 HWRITE4(sc, IPCC_RECV_SIGNAL_DISABLE,
257 HWRITE4(sc, IPCC_SEND_ID,
qcomiic.c 50 #define HWRITE4(sc, reg, val) \
198 HWRITE4(sc, GENI_TX_FIFO, word);
222 HWRITE4(sc, GENI_M_IRQ_CLEAR, stat);
223 HWRITE4(sc, GENI_I2C_TX_TRANS_LEN, cmdlen);
225 HWRITE4(sc, GENI_M_CMD0, m_cmd);
244 HWRITE4(sc, GENI_M_IRQ_CLEAR, stat);
245 HWRITE4(sc, GENI_I2C_RX_TRANS_LEN, buflen);
247 HWRITE4(sc, GENI_M_CMD0, m_cmd);
258 HWRITE4(sc, GENI_M_IRQ_CLEAR, stat);
259 HWRITE4(sc, GENI_I2C_TX_TRANS_LEN, buflen)
    [all...]
qcomspmi.c 105 #define HWRITE4(sc, obj, reg, val) \
294 HWRITE4(sc, QCSPMI_REG_OBSRVR,
367 HWRITE4(sc, QCSPMI_REG_CHNLS, SPMI_CHAN_OFF(sc, apid) +
374 HWRITE4(sc, QCSPMI_REG_CHNLS, SPMI_CHAN_OFF(sc, apid) +
380 HWRITE4(sc, QCSPMI_REG_CHNLS, SPMI_CHAN_OFF(sc, apid) + SPMI_COMMAND,
  /src/sys/arch/arm/rockchip/
rk_tcphy.c 101 #define HWRITE4(sc, reg, val) \
104 HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
106 HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
306 HWRITE4(sc, PMA_CMN_CTRL1, 0x830);
308 HWRITE4(sc, XCVR_DIAG_LANE_FCM_EN_MGN(i), 0x90);
309 HWRITE4(sc, TX_RCVDET_EN_TMR(i), 0x960);
310 HWRITE4(sc, TX_RCVDET_ST_TMR(i), 0x30);
315 HWRITE4(sc, CMN_DIAG_HSCLK_SEL, reg);
318 HWRITE4(sc, CMN_PLL0_VCOCAL_INIT, 0xf0);
319 HWRITE4(sc, CMN_PLL0_VCOCAL_ITER, 0x18)
    [all...]
rk3399_pcie.c 121 #define HWRITE4(sc, reg, val) \
310 HWRITE4(sc, PCIE_CLIENT_BASIC_STRAP_CONF, PCBSC_PGS_GEN1);
312 HWRITE4(sc, PCIE_CLIENT_BASIC_STRAP_CONF, PCBSC_PGS_GEN2);
315 HWRITE4(sc, PCIE_CLIENT_BASIC_STRAP_CONF,
341 HWRITE4(sc, PCIE_CLIENT_BASIC_STRAP_CONF, PCBSC_LINK_TRAIN_EN);
361 HWRITE4(sc, PCIE_RC_CONFIG_LCSR, HREAD4(sc, PCIE_RC_CONFIG_LCSR) | PCIE_LCSR_RETRAIN);
380 HWRITE4(sc, PCIE_RC_BASE + PCI_CLASS_REG,
385 HWRITE4(sc, PCIE_LM_VENDOR_ID, PCI_VENDOR_ROCKCHIP);
386 HWRITE4(sc, PCIE_RC_BASE + PCI_CLASS_REG,
389 HWRITE4(sc, PCIE_LM_RCBAR, PCIE_LM_RCBARPIE | PCIE_LM_RCBARPIS)
    [all...]
  /src/sys/dev/sdmmc/
sdhc.c 163 hwrite4(struct sdhc_host *hp, bus_size_t o, uint32_t val) function in typeref:typename:void
171 #define HWRITE4(hp, reg, val) hwrite4(hp, reg, val)
178 do if ((bits) != 0) HWRITE4((hp), (reg), HREAD4((hp), (reg)) & ~(bits)); while (0)
184 do if ((bits) != 0) HWRITE4((hp), (reg), HREAD4((hp), (reg)) | (bits)); while (0)
354 HWRITE4(hp, SDHC_MMC_BOOT, 0);
355 HWRITE4(hp, SDHC_HOST_CTL, SDHC_USDHC_BURST_LEN_EN |
357 HWRITE4(hp, SDHC_WATERMARK_LEVEL,
483 HWRITE4(hp, SDHC_NINTR_STATUS, SDHC_CMD_TIMEOUT_ERROR << 16);
683 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, 0)
    [all...]

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