| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_rv740_dpm.c | 198 u32 mpll_dq_func_cntl = pi->clk_regs.rv770.mpll_dq_func_cntl; local in function:rv740_populate_mclk_value
233 mpll_dq_func_cntl &= ~(CLKR_MASK |
238 mpll_dq_func_cntl |= CLKR(dividers.ref_div);
239 mpll_dq_func_cntl |= YCLK_POST_DIV(dividers.post_div);
240 mpll_dq_func_cntl |= CLKF(dividers.whole_fb_div);
241 mpll_dq_func_cntl |= CLKFRAC(dividers.frac_fb_div);
242 mpll_dq_func_cntl |= IBIAS(ibias);
279 mclk->mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
308 pi->clk_regs.rv770.mpll_dq_func_cntl
325 u32 mpll_dq_func_cntl = pi->clk_regs.rv770.mpll_dq_func_cntl; local in function:rv740_populate_smc_acpi_state
[all...] |
| radeon_cypress_dpm.c | 490 u32 mpll_dq_func_cntl = local in function:cypress_populate_mclk_value
491 pi->clk_regs.rv770.mpll_dq_func_cntl;
537 mpll_dq_func_cntl &= ~(CLKR_MASK |
542 mpll_dq_func_cntl |= CLKR(dividers.ref_div);
543 mpll_dq_func_cntl |= YCLK_POST_DIV(dividers.post_div);
544 mpll_dq_func_cntl |= CLKF(dividers.whole_fb_div);
545 mpll_dq_func_cntl |= CLKFRAC(dividers.frac_fb_div);
546 mpll_dq_func_cntl |= IBIAS(ibias);
549 mpll_dq_func_cntl &= ~PDNB;
551 mpll_dq_func_cntl |= PDNB
1345 u32 mpll_dq_func_cntl = local in function:cypress_populate_smc_acpi_state
[all...] |
| rv770_dpm.h | 39 u32 mpll_dq_func_cntl; member in struct:rv770_clock_registers
|
| si_dpm.h | 101 u32 mpll_dq_func_cntl; member in struct:si_clock_registers
|
| ci_dpm.h | 139 u32 mpll_dq_func_cntl; member in struct:ci_clock_registers
|
| ni_dpm.h | 43 u32 mpll_dq_func_cntl; member in struct:ni_clock_registers
|
| radeon_rv770_dpm.c | 400 u32 mpll_dq_func_cntl = local in function:rv770_populate_mclk_value
401 pi->clk_regs.rv770.mpll_dq_func_cntl;
460 mpll_dq_func_cntl &= ~(CLKR_MASK |
465 mpll_dq_func_cntl |= CLKR(encoded_reference_dividers[dividers.ref_div - 1]);
466 mpll_dq_func_cntl |= YCLK_POST_DIV(postdiv_yclk);
467 mpll_dq_func_cntl |= CLKF(clkf);
468 mpll_dq_func_cntl |= CLKFRAC(clkfrac);
469 mpll_dq_func_cntl |= IBIAS(ibias);
480 mclk->mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
928 u32 mpll_dq_func_cntl local in function:rv770_populate_smc_acpi_state
[all...] |
| radeon_ni_dpm.c | 1197 ni_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
1701 cpu_to_be32(ni_pi->clock_registers.mpll_dq_func_cntl);
1804 u32 mpll_dq_func_cntl = ni_pi->clock_registers.mpll_dq_func_cntl; local in function:ni_populate_smc_acpi_state
1875 mpll_dq_func_cntl &= ~PDNB;
1911 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
2175 u32 mpll_dq_func_cntl = ni_pi->clock_registers.mpll_dq_func_cntl; local in function:ni_populate_mclk_value
2218 mpll_dq_func_cntl &= ~(CLKR_MASK
[all...] |
| radeon_ci_dpm.c | 1895 pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
2804 u32 mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl; local in function:ci_calculate_mclk_params
2828 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
2829 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
2872 mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
3083 cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl);
|
| radeon_si_dpm.c | 3585 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
4387 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4505 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; local in function:si_populate_smc_acpi_state
4589 cpu_to_be32(mpll_dq_func_cntl);
4888 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; local in function:si_populate_mclk_value
4912 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
4913 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/ |
| amdgpu_ci_smumgr.c | 1038 uint32_t mpll_dq_func_cntl = data->clock_registers.vMPLL_DQ_FUNC_CNTL; local in function:ci_calculate_mclk_params
1066 mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl,
1067 MPLL_DQ_FUNC_CNTL, YCLK_SEL, mpll_param.yclk_sel);
1068 mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl,
1069 MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
1113 mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
|
| amdgpu_iceland_smumgr.c | 1062 uint32_t mpll_dq_func_cntl = data->clock_registers.vMPLL_DQ_FUNC_CNTL; local in function:iceland_calculate_mclk_params
1093 /* MPLL_DQ_FUNC_CNTL setup*/
1094 mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl,
1095 MPLL_DQ_FUNC_CNTL, YCLK_SEL, mpll_param.yclk_sel);
1096 mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl,
1097 MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
1165 mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
|
| amdgpu_tonga_smumgr.c | 805 uint32_t mpll_dq_func_cntl = data->clock_registers.vMPLL_DQ_FUNC_CNTL; local in function:tonga_calculate_mclk_params
843 /* MPLL_DQ_FUNC_CNTL setup*/
844 mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl,
845 MPLL_DQ_FUNC_CNTL, YCLK_SEL,
847 mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl,
848 MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV,
916 mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_si_dpm.c | 4046 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
4853 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4969 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; local in function:si_populate_smc_acpi_state
5054 cpu_to_be32(mpll_dq_func_cntl);
5352 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; local in function:si_populate_mclk_value
5376 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
5377 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel)
[all...] |
| si_dpm.h | 361 u32 mpll_dq_func_cntl; member in struct:ni_clock_registers
505 u32 mpll_dq_func_cntl; member in struct:rv770_clock_registers
917 u32 mpll_dq_func_cntl; member in struct:si_clock_registers
|
